JPH0331993Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a CRT display device that displays a character and a background of the character superimposed on an image.

When displaying characters using a CRT that displays images, such as when displaying characters using a CRT (cathode ray tube) in a television receiver,
In addition to displaying a video and a character separately, methods that display a character superimposed on a video are also used. In that case, in order to clearly display the character, the background BS is
is added and displayed. Figure 1 shows
This is an example in which a character CS with white text on a black background is displayed superimposed on the video VS.

FIG. 2 is a block diagram showing the configuration of a conventional CRT display device that displays characters added with a background superimposed on an image. Second
In the figure, reference numeral 11 denotes a display controller, which collectively controls the display of characters on the CRT. Reference numeral 12 denotes a RAM in which addresses in the character generator of characters to be displayed on the CRT are stored. Reference numeral 13 denotes a character generator, which is a ROM in which display data corresponding to the characters to be displayed are written. In the case of the figure, addresses of 128 types of characters are specified on address lines _A0 to _A6 . Assuming that each character is composed of 7 x 9 dots as shown in Fig. 3, nine columns of characters are specified by row (ROW) address lines _R0 to _R3 , and the data is The horizontal arrangement of is parallel data D ₀
~ _D6 is output.

14 is a shift register for parallel-to-serial conversion; when a pulse is applied from the display controller 11, parallel data D ₀ to D ₆ are loaded from the character generator 13 to the shift register 14, and the serial character is converted in accordance with the clock pulse CK. Output as a signal. This operation is not performed when there is no pulse. Reference numeral 15 denotes a level conversion circuit for shifting the level of the character signal output from the shift register 14 to correspond to the white level of the video signal. 16 is CRT
The display has a CRT and horizontal and vertical deflection systems.

On the other hand, the video signal is input from the input terminal VIDEO IN, and is input to the synchronization separation circuit 18 via the buffer 17. The synchronization separation circuit 18 separates a horizontal synchronization signal and a vertical synchronization signal from the video signal.
The signal is supplied to the display controller 11 as a display timing signal, and is also supplied to the horizontal and vertical deflection systems of the CRT display 16.

The video signal from the buffer 17 is applied to the video amplification circuit 20 via a combining circuit 21 made of diodes. The video amplification circuit 20 receives the video signal.
The image is amplified to the CRT drive level and supplied to the CRT display 16, and the image is displayed on the CRT.

In addition, the background signal of the character is transmitted from the display controller 11 to the NAND gate (NAND 2).
2 to one input of the shift register 14.
The character signal outputted from the NAND 22 is inverted by a NOT gate (NOT) 23 and is applied to the other input of the NAND 22. Therefore, NAND22
The background signal is output only when there is no character signal, and the background signal is cut off when there is a character signal. A level conversion circuit 19 converts the output of the NAND 22 into a voltage corresponding to the black level of the video signal. Conversion circuit 1
The output of 9 is applied to the synthesis circuit 21 to forcibly lower the video signal to the black level. As a result, as shown in FIG. 1, the character CS is displayed in white letters on the black background BS.

Display on the CRT display 16 is performed as follows. First, display controller 1
1, the address (A ₀ to _{A 6} ) of the character to be displayed in the character generator 13 is written as data to the part of the RAM 12 at the address corresponding to the display position on the screen, and the part where the character is not displayed is written as data. The address of the space is written.

The address data to be written is in RAM12.
After setting the address data to the DATAIN terminal, the display controller 11
Set the READ/ line to “L” and write address data to RAM12. In this way,
Address information of the character is input into the RAM 12 at an address portion corresponding to the location to be displayed on the CRT.

The display controller 11 addresses the RAM 12 in accordance with the scanning of the CRT display 16 based on the horizontal synchronization signal H.SYNC and the vertical synchronization signal V.SYNC from the synchronization separation circuit 18, and further specifies the row address to read the character. LOAD column data D ₀ to _{D 6} to shift register 14
A clock pulse for shifting is loaded as a pulse and also sent from the display controller 11.
Output as a serial character signal with CK.

This character signal is level-converted by a level conversion circuit 15 and supplied to a synthesis circuit 21, where the video signal level is raised to a white level via a diode OR. A video signal is supplied from the buffer 17 to the configuration circuit 21 . Further, the background signal is supplied from the level conversion circuit 19 to the synthesis circuit 21 as described above.

The video amplification circuit 20 generates a composite video signal in which a character signal to which a background has been added is superimposed on the video signal.
The signal is amplified to the CRT drive level and supplied to the CRT display 16, and a synthesized image as shown in FIG. 1 is displayed in which the character CS, in which a black level background BS is added to the CRT, is superimposed on the image VS. In addition,
When the background signal from the display controller 11 is stopped, a character without a background is displayed using the character signal from the level conversion circuit 15.

Conventional CRT display devices that display composite images have the above-mentioned configuration, so if the background of a character is to be made black, the display controller 11 sends a background signal to make the background black in accordance with the character display position. It was necessary to send out the background signal separately, and therefore the configuration of the display controller 11 was complicated, and the control operation for outputting the background signal in accordance with the position of the character was also complicated.
In particular, when characters are displayed randomly on the screen or when there are a large number of characters, the control operation becomes extremely complicated.

The present invention was made in order to eliminate the drawbacks of conventional CRT display devices for displaying composite images. By adding a
The purpose is to provide a display device.

Hereinafter, the present invention will be explained in detail based on an embodiment shown in FIGS. 4 to 7.

FIG. 4 is a block diagram showing the configuration of the CRT display device of the present invention.The configuration is the same as that in FIG. 2 except for the character/background signal generator 30 surrounded by a dotted line. Common parts will be described with the same reference numerals.

In Fig. 4, parts that are common to Fig. 2 will be briefly explained. 11 is a display controller that collectively controls to display characters on the CRT, and 12 is a character generator for the characters to be displayed on the CRT. 15 is a level conversion circuit that shifts the level of the character signal outputted from the character/background signal generation section 30 to correspond to the white level of the video signal; 16 is a CFT and horizontal/vertical deflection system; 17 is a buffer for the video signal; 18 is a synchronization separation circuit that separates the horizontal synchronization signal H.SYNC and the vertical synchronization signal V.SYNC from the video signal and supplies it to the display controller 11 and the CRT display 16; 19 is a NAND 22 A level conversion circuit 22 converts the background signal output from the character/background signal generator 30 into a voltage equivalent to the black level of the video signal, and a level converter circuit 22 converts the background signal output from the character/background signal generator 30 into a signal obtained by inverting the character signal output from the character/background signal generator 30 using a NOT gate (NOT) 23. A NAND gate (NAND) 21 is made up of diodes D ₁ to _{D 3} and cuts the background signal when there is a character signal from the signal. A synthesis circuit 20 synthesizes background signals and outputs a synthesized video signal;
This is a video amplification circuit that amplifies the video to the CRT level and displays it on the CRT display 16.

Character/background signal generation section 3 surrounded by dotted lines
0, 25 is a character generator, 2
6 is a shift register for parallel-to-serial conversion, 27 is a NOT gate (NOT), 28 is a NAND gate (NAND), and 29 is a D-type flip-flop (D-type flip-flop).
It is a latch circuit consisting of FF).

The character generator 25 uses, as character data, character data related to the character itself and an identification bit added thereto indicating whether the character at the specified address is a space or has character data. .

Figure 5 shows that the character data is
The explanation is given by taking as an example the case of a ×9 dot configuration. Character data regarding characters having a 7×9 dot configuration is output as column data D ₀ to D ₆ using row (ROW) addresses 0001 to 1001. In this invention, the character data D ₇
An identification bit is added that indicates whether the character at the specified address is a space or contains character data. Therefore,
As shown in Figure 5a, when there is character data, the _D7 bit is ``1'' (shown in black), and as shown in Figure 5b, when the character is a space, the <sub>D7</sub> bit is ``1'' (shown in black). is "0" (shown in white), and the row addresses "0000" and "1010" are data added to add a background above and below the character.

Next, the operation of the character/background signal generating section 30 will be explained. As in the case of FIG. 2, the display controller 11 stores the address (A ₀ to A ₆ ) of the character to be displayed in the character generator 25 as data in the part of the RAM 12 corresponding to the position to be displayed on the screen. write,
Space addresses are written in areas where characters are not displayed. The address data to write is
After setting the address data to the DATA IN terminal of the RAM 12, the display controller 11 sets the READ/line to “L”.
Write address data to RAM12.

The display controller 11 addresses the RAM 12 in accordance with the scanning of the CRT display 16 based on the horizontal synchronization signal H.SYNC and vertical synchronization signal V.SYNC from the synchronization separation circuit 18, and further addresses the row address (R ₀ to R ₃ ) and shift the character pattern string data _D0 to _D7 from the character generator 25 to the shift register 26.
Load with LOAD pulse.

The shift register 26 has an 8-bit configuration, and the pattern string data D ₀ to D ₇ input to A to H from the character generator 25 are supplied from the display controller 11 when the pulse is at the "L" level. Loaded internally at the rising edge of clock pulse CK. At the same time, the H data is output to the output terminal OUT, and thereafter, at the rising edge of the clock pulse CK, the data is sequentially shifted in the order of G→F→E→...→A and is output as a serial character signal. After A, the "L" level is automatically output.

FIG. 6 shows a timing chart of the above-mentioned operation. The pulse and clock pulse CK are sent from the display controller 11 to the shift register 26 at the timing shown in FIG. Also, the frequency of clock pulse CK is
It is determined by the size of one dot displayed on the CRT screen.

Character generator 25 address line
A ₀ -A ₆ are set before the pulse is output, and these address lines A ₀ -A ₆ are sequentially set in accordance with the display characters. In addition,
Output of shift register 26 shown in FIG.
At OUT, the "L" before G (H end) and the "L" after A are for placing a space between the next character.

In this manner, the shift register 26 converts the column data D ₀ to D ₆ sent in parallel from the character generator 25 into serial character signals, and sequentially outputs the serial data signals.

On the other hand, the identification bit D ₇ output from the character generator 25 together with the character data D ₀ to D ₆ is the D
Added to the terminal. In addition, the pulse output from the display controller 11 is NAND
Connect the clock pulse CK to one input terminal of 28.
The clock pulse inverted by NOT27 is
Added to the other input terminal of NAND28, NAND
The output of 28 is applied to the CK terminal of D/FF.

Therefore, as shown in FIG. 6, at the timing of data loading to the shift register 26, that is, at the time _t0 when the pulse is "L" and the clock pulse rises, the identification bit is loaded into the latch circuit 29 consisting of D and FF. D ₇ data is latched. Identification bit _D7 becomes "1" or "H" level when there is a character display, and becomes "0" or "L" level when it is a space. In this case, "L" is output from the latch circuit 29 and applied to one input terminal of the NAND 22. Since a signal obtained by inverting the character signal by NOT 23 is applied to the other input terminal of NAND 22, the signal is output from NAND 22. The "L" level background signal is cut off when there is a character signal.

The operations after NAND22 are the same as in the case of FIG. In other words, when there is a character display, during each column data period of character data (6th
t ₀ to t ₁ in the figure) The latch circuit 29 outputs “H”.
Add to NAND22. The NAND 22 outputs an "L" level background signal when there is no data bit constituting a character among the column data D ₀ to D ₆ (that is, G to A) bits of the character. This "L" level background signal is level-converted by the level conversion circuit 19 and applied to the synthesis circuit 21, which turns on the diode _D3 and forcibly lowers the video signal applied to the diode _D2 to the black level. If there are data bits that constitute a character in the ₆ bits of character column data D ₀ to D, NOT
Since the output of NAND 23 becomes "L", the output of NAND 22 becomes "H". Therefore, the diode D ₃ of the combining circuit 21 is turned off, and the character signal applied to the diode D ₁ is applied to the video amplifying circuit 20 as it is. In this way, as shown in FIG. 7, the character part is white and the other parts are black, that is, the character is displayed in white letters against a black background. Furthermore, the number of data columns is increased by one column at the top and bottom compared to FIG. 3, and background signals are output from both the top and bottom, so that the background can be added to the top and bottom to clearly display the character.

In addition, if the background is not required, the latch circuit 29
If you clear the D/FF clear terminal CL of
Only characters can be displayed. By applying clearing appropriately, characters with a background and characters without a background can be mixed and displayed.

Further, in the embodiment, a character having a 7×9 dot configuration has been described as an example, but the present invention is not limited to this configuration.

Furthermore, the present invention can be used for color CRT display devices as well as monochrome ones, such as:
In color CRT display devices that can directly drive R (red), G (green), and B (blue) by superimposing them on the image, it is possible to add any color to the characters and background, allowing for a variety of displays. be able to.

As explained above, according to the present invention, an identification bit is added to the character generator to distinguish whether it is a character display or a space, so that when adding a background to a character, the display controller Since no special processing is required, the display controller can be easily designed, and a background can be easily added to the character no matter how the character is displayed.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of a composite screen that superimposes and displays a character with a background added to the video, Figure 2 is a block diagram of a CRT display device that displays a conventional composite screen, and Figure 3 is a character generator. An explanatory diagram of the pattern, Figure 4 is a block diagram of a CRT display device that displays the composite screen of the present invention,
Figure 5 is an explanatory diagram of the character data of the character generator used in the present invention, and Figure 6 is an explanatory diagram of the character data of the character generator used in the present invention.
FIG. 7 is a time chart showing the operation of the figure, and FIG. 7 shows an example of character display according to the present invention. 11... Display controller, 12...
RAM, 13...Character generator, 14
...Shift register for parallel-to-serial conversion, 15...Level conversion circuit, 16...CRT display, 17
...Batua, 18...Synchronization separation circuit, 19...
Level conversion circuit, 20... Video amplification circuit, 21...
...Synthesis circuit, 22...NAND gate (NAND),
23... Not gate (NOT), 25... Character generator, 26... Shift register for parallel-to-serial conversion, 27... Not gate (NOT), 28
... NAND gate (NAND), 29 ... latch circuit, 30 ... character/background signal generation section.

Claims (1)

[Scope of utility model registration request] In a CRT display device that is controlled by a display controller and displays a character and the background of this character on a video image superimposed on a CRT, an identification bit indicating whether or not the addressed character is a space is stored in the character's own data. a character generator that outputs the identification bit at the timing of loading the character data into the shift register; a shift register that loads the character data, converts it into a serial character signal, and outputs the serial character signal; a latch circuit for holding the output identification bit; a background signal generating means for outputting a background signal of the character using the output of the latch circuit as a control signal; and a character signal output from the shift register and a background signal generating means. A CRT characterized in that it is equipped with a synthesis circuit that outputs a composite video signal in which a character signal to which a background is added from a background signal and a video signal output from the video signal is superimposed on the video signal.
Display device.