JPH033195A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To increase an access speed at the time of reading and, simultaneously, to prevent a recording data destruction at the time of writing by making the input threshold of a data value selecting switch circuit for writing higher than the input threshold value of a data line selecting switch circuit for reading. CONSTITUTION:A common data line and a data line selecting switch circuit are provided separately for a common data line CLR for reading, a data line selecting switch circuit 3R for reading and a common data line CLW for writing and a data line selecting switch circuit 3W for writing, and only the input threshold of the switch circuit 3R is increased by the intervention of a high threshold executing circuit 6. Thus, an action threshold at the time of reading and an action threshold at the time of writing are independently set, respectively, and the fear of a stored data destruction at the time of writing can be made small without lowering the access speed at the time of reading.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a technology that is effective when applied to semiconductor storage devices and also RAM (random access memory), such as bipolar 0MO8 type RAM. It concerns techniques that can be effectively utilized.

[Conventional technology] FIG. 3 shows an example of the configuration of a conventional semiconductor memory device.

The semiconductor memory device shown in the figure is configured as a RAM, in which memory cells 1 are arranged in the row and column directions. Word lines are wired to select the memory cells 1 from the row and column directions. WL, the data line DL, the common data line CL, and a word line selection drive circuit (X decoder/driver) that randomly selects and drives the word line WL 2° between the data line DL and the common data line CL Data line selection switch circuit 3 interposed in the data line selection switch circuit 3) A data line selection port 1%l (Y decoder) 4 which selectively selects this data line selection switch circuit 3 and turns it on; It has a read/write circuit 5 for reading and writing data (References: Nikkei Electronics, March 9, 1987 issue, published by Nikkei BP,
, 416), pp. 4134-141).

[Problems to be Solved by the Invention] However, the inventors have found that the above-mentioned technique has the following problems.

That is, since the common data line and the data line selection switch circuit are shared for writing and reading, respectively,
As shown in FIG. 4, the operating threshold VthR during reading and the operating threshold Vthw during writing are the same.

Therefore, in order to increase the noise resistance margin during writing, it is effective to increase the input threshold of the data line selection switch circuit 3; however, increasing the input threshold of the data line selection switch circuit 3 , a problem arises in that the access speed during reading is reduced.

On the other hand, lowering the input threshold of the data line selection switch circuit 3 increases the access speed during reading, but increases the risk of malfunction due to noise such as power supply voltage fluctuations, and The risk of destroying data stored in memory cells increases.

An object of the present invention is to provide a technique that reduces the risk of data destruction during writing without reducing the access speed during reading.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a common data line and a data line selection switch circuit are provided separately for reading and writing, respectively, and the input threshold of the write data line selection switch circuit and the input threshold of the read data line selection switch circuit are The values are made to be different from each other, and the former is made higher in absolute value than the latter.

[Operation] According to the above-described means, by increasing the input threshold of the write data line selection switch circuit, it is possible to reduce the possibility that data stored in memory cells in non-selected columns will be destroyed during writing. At the same time, the input threshold of the read data line selection switch circuit can be set to an appropriate value without sacrificing the access speed during read.

This achieves the objective of reducing the risk of memory data destruction during writing without reducing the access speed during reading.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a main part of a semiconductor memory device to which the technique of the present invention is applied.

The semiconductor memory device shown in the figure is configured as a bipolar CMo5 type RAM, and first of all, its basic components are memory cells 1) arranged in rows and columns. Word line WL and data line D wired to select from direction and column direction
L, a common data line CL, a word line selection drive circuit (X decoder/driver) that selectively selects and drives the word line WL 2) a data line interposed between the data gWL and the common data line CL; Selection switch circuit 3) A data line selection circuit (Y decoder) 4 that selectively selects and turns on the data line selection switch circuit 3, reads and writes stored data via the common data line CL. It has a read/write circuit 5 and the like.

Here, in the semiconductor memory device of the embodiment shown in FIG.
The common data line CL and the data line selection switch circuit 3 are used for reading (CLR and 3R) and for writing (
CLW and 3W). That is, the read common data line CLR1 read data line selection switch circuit 3R.

A write common data line CLW and a write data line selection switch circuit 3W are provided. The read data line selection switch circuit 3R includes a p-channel MOS transistor Ml,
The write data line selection switch circuit 3W is composed of n-channel MOS transistors M3. It is composed of M4.

Furthermore, in addition to the above-described configuration, a high threshold voltage circuit 6 is interposed on the input side of the write data line selection switch circuit 3R, and the input threshold of the write data line selection switch circuit 3R is are selectively enhanced. This high input thresholding circuit 6 includes CMOS transistors M5. M
The input threshold is increased by making the gate width and channel length ratios of each of the six inverters different from each other.

As a result, as shown in FIG. 2, the operating threshold value VthR during reading and the operating value Vthw during writing are set independently.

As described above, the write data line selection switch circuit 3
By selectively increasing only the input threshold of R,
It is possible to reduce the risk of data stored in memory cells in non-selected columns being destroyed due to malfunctions during writing, and at the same time, the input threshold of the read data line selection switch circuit can be adjusted at the expense of the access speed during reading. It becomes possible to set the value to an appropriate value.

This makes it possible to reduce the risk of memory data destruction during writing without reducing the access speed during reading.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, the high threshold voltage circuit 6 may be a circuit other than a CMOS inverter.

The above explanation will mainly focus on the bipolar/eMo field of application which is the background of the invention made by the present inventor.
Although the case where the present invention is applied to an S-type RAM has been described, the present invention is not limited thereto.

For example, it can be applied to 0MO8 type or ECL type RAM.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, it is possible to reduce the risk of memory data destruction during writing without reducing the access speed during reading.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a schematic configuration of a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a diagram showing the operation of the data line selection switch circuit in the above device. FIG. 3 is a diagram showing an example of the configuration of a conventional semiconductor memory device. FIG. 4 is a diagram showing the operation of the data line selection switch circuit in the above device. It is a diagram. 1...Memory cell, 2...Word line selection drive circuit, 3R...Read data line selection switch circuit,
3W...Write data line selection switch circuit, 4...
...Data line selection circuit, 5...Read/write circuit, 6
...High threshold voltage circuit, WL...Word line, D
L...Data line, CLR...Council data line for writing. CLW: Read data line, CL: Common data line. Diagram

Claims (1)

[Scope of Claims] 1) Memory cells arranged in the row and column direction, word lines and data lines wired to select the memory cells from the row and column directions, and a common data line; A word line selection drive circuit that selectively selects a word line and makes a fuss; a data line selection switch circuit interposed between the data line and the common data line; and a data line selection switch circuit that selectively selects a word line. A semiconductor memory device comprising a data line selection circuit that selects and turns on, and a circuit that reads and writes stored data via the common data line, the common data line and data line selection switch circuit are provided separately for reading and writing, and the input threshold of the write data line selection switch circuit and the input threshold of the read data line selection switch circuit are made different from each other,
A semiconductor memory device characterized in that the former is made higher in absolute value than the latter to selectively increase only the noise resistance margin during writing. 2) The semiconductor memory according to claim 1, characterized in that a high threshold value increasing circuit is interposed on the input side of the write data line selection switch circuit in order to increase the input threshold value thereof. Device. 3) In order to increase the input threshold of the write data line selection switch circuit, the input threshold is increased by making the gate width and channel length ratios of the CMOS transistors on the input side different from each other. 3. The semiconductor memory device according to claim 1, further comprising an inverter interposed therebetween.