JP3179822B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device capable of preventing an error when a memory cell reads data.

[0002]

2. Description of the Related Art In a semiconductor memory having dynamic memory cells, one of word lines is generally selected by a row address, and after the level of the word line rises, data of the memory cell is transferred to a bit line. afterwards,
The bit line sense amplifier corresponding to the column address becomes active, bit line sensing is performed, and data is read.

In such a dynamic memory, a word line driving circuit for driving a word line and a bit line sense amplifier driving circuit are usually arranged as peripheral blocks around a memory cell.

[0004] With the dramatic increase in memory capacity in recent years, word lines for instructing writing / reading to memory cells and bit lines for transmitting read signals from memory cells have become longer and more numerous. Wiring resistance and load capacity are increasing. For this reason, there are problems such as a relative decrease in the driving capability of the word line drive circuit, a decrease in the bit line S / N, and a signal delay.

In order to prevent this, it has been proposed to divide the memory cell region into a plurality. In FIG. 1, a plurality of memory cell arrays 3a to 3h are formed by dividing a cell region on a memory chip into eight, and a row decoder, a sense amplifier / column (column) decoder, and a word line driving circuit are arranged in each memory cell array. Things are shown.

According to the configuration shown in FIG. 1, an address signal supplied from the outside is temporarily held in a row address buffer 1 and a column address buffer 2. The row address buffer 1 supplies a row address signal to the row decoders 4a to 4h of each memory cell array. When the output of each row decoder is the same, the row decoder can be shared. The column address buffer 2 applies a column address signal to the sense amplifier /
It is supplied to the column decoders 5a to 5h.

FIG. 2 shows a detailed configuration for operating the memory cell array. In this case, it is assumed that there are n memory cell arrays. Word line drive circuits 6a-6n corresponding to memory cell arrays 3a-3n
Is provided, and the word line driving signal output from the memory cell is supplied to the word line of the memory cell to drive the word line. Row decoders 4a to 4n for decoding row address signals from the row address buffer 1 are provided between the word line drive circuits 6a to 6n and the memory cell arrays 3a to 3n, and the addresses to be driven by the row decoders are provided. A line is selected.

As described above, since the bit line sense amplifier must be activated after the level of the selected word line has completely risen, any one of the word line driving circuits, here, the output generation from the 6a to the delay circuit 1
0 to operate the sense amplifier driving circuit 11 gives a predetermined delay time t _1, the so driving each sense amplifier to provide an output of the sense amplifier drive circuit in the sense amplifier / column decoder 5a~5h of each array I have to. Here, as the delay time t ₁ , a time sufficient for completing the reading to the bit line after the level of the selected word line rises is selected.

FIG. 3 is a signal waveform diagram showing a relationship among a word line drive signal W _i , a sense amplifier drive signal SE, bit line potentials B and / B at the time of data reading.

A selection signal W _i for selecting a word line is indicated by a solid line, and a drive signal SE of the sense amplifier is output after a predetermined time t _i from the time of occurrence.

When a drive signal is supplied to the word line selected by the row decoder, the data held in the bit line pair B and bar B is read from the memory cell connected to the word line, and the bit line potential is changed. A slight change occurs, and the potential change of the bit line pair is amplified by driving the sense amplifier, thereby completing the data reading.

The row decoders 4a to 4n, the word line driving circuits 6a to 6n, the delay circuit 10, and the sense amplifier driving circuit 11 form a word line control means 100.

As described above, when the storage area of the memory is divided, the word line and the bit line in one memory cell are shortened, and the wiring resistance and capacitance thereof can be reduced, and the word line driving circuits 6a to 6n , The load capacity can be reduced, and the speed of data access can be increased.

[0014]

However, there are cases where the power supply voltage V _CC and the ground voltage V _SS fluctuate due to the operation of the internal circuit of the memory. This When variously occurring on a memory chip, generation timing of the output W _i of word line drive circuit varies as shown by a chain line or two-dot chain line in FIG. 6. Since the above-described delay time t ₁ of the delay circuit 10 is set on the assumption that each memory cell array operates under a stable power supply voltage, the output of the word line drive circuit used as a reference for the delay by the delay circuit 10 An output of the word line drive circuit may be generated at a time later than the generation time. In this case, the allowance time from the word line drive output that occurred late to the drive of the sense amplifier is shorter than the set optimum time t ₁ . Therefore,
Incorrect sensing of the bit line is induced, which may destroy the data of the memory cell to be refreshed. Such a problem is particularly remarkable in a multiport memory or a field memory having a large number of circuits that operate asynchronously with the word line driving circuit.

Therefore, an object of the present invention is to provide a method for controlling a bit line by a sense amplifier driving circuit even when the output generation timing of each word line driving circuit varies due to a fluctuation of a power supply voltage or the like in a memory chip. An object of the present invention is to provide a semiconductor memory device capable of suppressing erroneous sensing.

[0016]

According to the semiconductor memory device of the present invention, there are provided a plurality of memory cell arrays in which dynamic memory cells are arranged in a matrix, and a plurality of memory cell arrays provided for each of the memory cell arrays. A plurality of word line driving circuits for driving word lines arranged in the direction, a plurality of sense amplifiers for deriving outputs to bit lines arranged in the column direction of each memory cell array to a logic level, and the plurality of words Drive signal detecting means for generating an output signal when all of the plurality of word line drive circuits are activated by taking the logical product of the outputs of the line drive circuits;
A delay circuit for delaying the output signal of the drive signal detecting means by a time sufficient for the charge to move from the corresponding memory cell to the bit line when the word line is driven and the potential of the bit line to slightly change; A sense amplifier drive circuit for driving the plurality of sense amplifiers by receiving an output signal of the drive signal detection means delayed by the delay circuit.

[0017]

According to the present invention, after detecting that all the word line drive signals generated from the plurality of word line drive circuits provided in each of the plurality of memory cell arrays have risen, the generation of the detection signal is output. Is done. Then, this detection signal is delayed by a predetermined time by the delay circuit and supplied to the sense amplifier drive circuit to drive the sense amplifier group.

As a result, when the generation timing of the drive signals output from the plurality of word line drive circuits varies due to power supply noise or the like, the memory cell is determined based on the last generated word line drive signal. Since the sense amplifier operates after a lapse of time during which the reading of the signal from the memory is reliably performed, erroneous sensing is prevented.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4 is a block diagram showing one embodiment of the present invention. The conventional word line control means 10 shown in FIG.
0 shows an improved part of the configuration of FIG. In FIG. 4, FIG.
The same reference numerals are given to the portions corresponding to and the detailed description thereof will be omitted.

In FIG. 4, word line drive circuits 6a to 6a
The output of n is connected to a corresponding word line via a row decoder and is also input to an AND gate 7. Therefore,
The AND gate 7 outputs a high-level signal when all of the word line drive circuits 6a to 6n are generating drive signals, and forms drive signal detection means. The output of the AND gate 7 is supplied to the delay circuit 10 as a detection signal. In the case of this embodiment generates the detection signal, the output at the time when the power supply voltage reaches the level of V _DD / 2 as V _DD is set the threshold of the AND gate to invert.
Delay time t ₂ set in this delay circuit 10
As in the conventional case, the word line is driven and the memory cell C
charges from _i to bit line pair is set sufficient time to the potential of the bit line pair to move to small changes, this value may be the same as the time mentioned above t _1. The delay circuit 10
When the time t ₂ elapses after the output of the AND gate is generated, the sense amplifier drive circuit 11 is instructed to operate. The sense amplifier drive circuit 11 supplies a drive signal to the sense amplifier / column decoders 5a to 5n. Other configurations are the same as those of the conventional circuit shown in FIG.

Accordingly, W _i ′ shown by a chain line in FIG.
The slowest generated driving signal of the word line drive circuit 6a~6n after lapse of time t ₂ as a reference, the sense amplifier 5a~5n of each memory cell array is driven as. Therefore, even if the drive signal of the word line drive circuit varies in each of the divided regions of the memory chip due to fluctuations in the power supply voltage or the like, the sense operation of the sense amplifier waits until the last bit line pair is read. Is started, erroneous sensing of the sense amplifier is avoided.

FIG. 5 is a block diagram showing another example of the word line control means 100, and includes word line driving circuits 6a to 6n.
Are connected to input terminals of a NOR gate 9 via inverters 8a to 8n, respectively. Such a logic gate circuit is equivalent to a simple AND gate, as is clear from De Morgan's theorem.

This embodiment has an advantage in that a so-called back gate bias effect caused by a large number of transistors connected in series can be avoided by not using a multi-input AND gate.

[0025]

As described above, in the semiconductor memory device of the present invention, the sense amplifier is operated after a lapse of a predetermined time after the drive signals are output from all the word line drive circuits. In other words, the configuration is such that the sense amplifier is operated after a predetermined read time from the memory cell has elapsed with reference to the drive signal output most recently. Therefore, since the sense amplifier operates after all of the reading of the minute signal held in the memory cell to the bit line pair is performed, erroneous sensing is performed even if the generation timing of the drive signal due to power supply noise or the like occurs. It is unlikely that a sufficient sense margin can be secured.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example in which a memory chip is divided into a plurality of memory cell arrays to form a memory.

FIG. 2 is a block diagram showing a configuration of a conventional word line control means 100.

FIG. 3 is a signal waveform diagram for explaining operation of the circuit.

FIG. 4 is a block diagram showing a configuration of a main part in the embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a main part in another embodiment of the present invention.

[Description of Signs] 3a-3n Memory cell array 4a-4n Row decoder 5a-5n Sense amplifier / column decoder 6a-6n Word line drive circuit 7 AND gate 9 OR gate 10 Delay circuit 11 Sense amplifier drive circuit

Claims (3)

(57) [Claims] 1. A plurality of memory cell arrays dynamic memory cells arranged in a matrix, wherein provided for each memory cell array, a plurality of word for driving a word line arranged in a row direction of the memory cell array < a logic line driving circuit; a plurality of sense amplifiers for deriving an output to a bit line arranged in a column direction of each memory cell array to a logic level; and a logical product of outputs of the plurality of word line driving circuits taking
When all of the plurality of word line drive circuits are activated
A driving signal detecting means for generating an output signal when the word line is driven to transfer a charge from the corresponding memory cell to the bit line to cause a slight change in the potential of the bit line. And a delay circuit for delaying the drive signal by a time sufficient for the output of the drive signal detecting means.
And a sense amplifier driving circuit for driving the plurality of sense amplifiers when a signal is supplied. 2. The semiconductor memory device according to claim 1, wherein said drive signal detecting means forms an AND gate. 3. The semiconductor memory device according to claim 1, wherein said drive signal detecting means is a NOR gate having an inverted input.