JPH0331037B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a positional deviation detection circuit for interlaced television signals.

Literature “Revue de Radio−diffusion
't'el'evisior' (April/May, 1978, pp. 35-42)
discloses a positional deviation detection circuit of the above-mentioned type, in which the delay circuit is an image delay circuit, and information on a certain number of time-sequential lines is compared by a comparison circuit to the corresponding time of the preceding image.
It is configured to sequentially compare information on a certain number of lines.

An object of the present invention is to reduce the number of circuit components.

Accordingly, the positional deviation detection circuit according to the invention comprises field delay means for receiving television signals, and connected to said field delay means, which detects information from image lines A, B, C of one field and adjacent fields of another field. A plurality of difference code signals (S
[A-B], S[B-C], S[C-D]); and a comparison means that is connected to the comparison means and sequentially generates difference code signals (S[A-B], S[B]). -C], S[C-
D]) is characterized by comprising a sign reversal detecting means for generating a control signal when the signals are different from each other, and an output means connected to the sign reversing detecting means and generating a positional deviation instruction signal in response to the control signal. shall be.

When using signal inversion detection circuits, it is sufficient to use field delay circuits instead of image delay circuits, resulting in a significant reduction in the number of circuit components and, moreover, for example doubling the number of lines. It has also been found beneficial to use it in circuits where field memories are used, such as in interpolation circuits for.

The invention will be explained below with reference to the drawings.

In FIG. 1, an interlaced television signal is applied to input terminal 3 of field delay circuit 5. In FIG.
At any desired instant, it is necessary to detect whether or not the display object (or object) has moved or shifted in the image projected or displayed by the television signal.

In FIG. 2, the background area where such a display object is displayed with diagonal lines is shown as a white area, and this white area occupies the position indicated by I during one field period of the image, and does not appear during the next field period. shall occupy the position shown.

The field delay circuit 5 has an output terminal 7 at which an undelayed input signal is generated, and an output terminal 7 at which an undelayed input signal is generated.
It has an output terminal 9 that appears with a delay of L).

FIG. 2 shows a portion of a number of image lines in the corner of the display object, and information B from the line having a number n-1 according to the position where it occurs in the image.
is generated at the output terminal 7 of the delay circuit 5, and information A from a line having a number n corresponding to the position where it occurs in the image is generated at the output terminal 9 of the delay circuit 5.

The output terminals 7 and 9 of the delay circuit 5 are connected to the comparison circuit 15.
are connected to input terminals 11 and 13, respectively. This comparison circuit includes three subtraction circuits 17, 19, and 21. The two input terminals of the subtraction circuit 17 are connected to the input terminals 11 and 13 of the comparison circuit 15, respectively, and the information from the image line n and the image line (n-
1) is generated at the output terminal 23 of the comparison circuit 15 connected to the subtraction circuit 17.

The subtraction circuit 19 has an input terminal directly connected to the input terminal 11 of the comparison circuit 15 and an input terminal connected to the input terminal 13 via a delay line 25 having a delay time of one line period L. The information C from the line shown in FIG. 2, which has a number n-2 according to its position, is produced in a connection path from this delay line to the input terminal of the subtractor circuit 19, and the information C from the line shown in FIG. A comparator circuit 1 connected to an output terminal of a subtraction circuit 19 calculates the difference B-C of information from n-2.
The signal is generated at the output terminal 27 of 5.

Furthermore, the subtraction circuit 21 has an input terminal connected to the input terminal 13 via a delay line 25, and another input terminal connected to the input terminal 11 of the comparison circuit 15 via a delay line 29 having a delay time of one line period L. It has an input terminal. Through this delay line 29,
The information D from the line shown in FIG. 2, which has the number n-3 according to its position in the image, is supplied to the corresponding input terminal of the subtraction circuit 21, and the information from the image line n-2 and the line n- Difference with information from 3 C-D
is generated at the output terminal 31 of the comparison circuit 15 connected to the output terminal of the subtraction circuit 21.

Image lines n and n-2 in FIG. 2 occur in the field in which the display object is in position I, and therefore these lines are the lines that reproduce the black background. Since image lines n-1 and n-3 occur in the field in which the display object is located,
These lines are bright in the area being displayed. Therefore, for example, if we consider two sub-regions, lines n, n-1,
n-2 and n-3 are in the dark, bright, dark and light states alternately, and this state is represented by 0, 1,
Indicated by 0,1. Therefore, output terminal 2 of the comparison circuit
Differences in information A-B, B- in 3, 27 and 31
C and CD become -1, +1 and -1 sequentially,
These differences therefore provide information on the polarity or sign reversal of the displaced (or misaligned) regions both horizontally and vertically.

Output terminals 23, 27 and 31 of comparison circuit 15 are connected to input terminals 37, 39 and 41 of output circuit 42, respectively. These input terminals 37, 39 and 4
1 to the input terminal 4 of the limiter circuit 49, 51, 53
3, 45, and 47, respectively, and the multiplier 6
It is also connected to input terminals 55, 57, and 59 of terminals 1, 63, and 65, respectively.

Difference code signals S[A-B], S[B-C], and S[CD] representing the signs of the differences A-B, B-C, and CD, respectively
are generated at the output terminals 67, 69, 71 of the limiter circuits 49, 51, 53, respectively, and these difference sign signals are applied to the other input terminals 73, 75, 77 of the multipliers (or amplifiers) 61, 63, 65, respectively. and output terminals 79 and 8 of the output circuit 42, respectively.
1 and 83, respectively.

As a result, absolute value signals representing the absolute values |A-B|, |B-C|, |CD| of the signals at input terminals 55, 57, and 59 are generated in amplifiers 61, 63, and 65, respectively. As is clear from FIG. 2 and the above explanation, this absolute value has a non-zero value in the displacement region.

91, 93, 95 indicate limit value circuits, whose input terminals 79, 99, 101 are connected to amplifiers 61, 6.
3 and 65, respectively. It is then checked whether the output value of each amplifier different from zero exceeds a predetermined limit value defined by the limit value generator 109. still,
This limit value generation source 109 is the limit value circuit 91,9
3, 95 other input terminal 103, 105, 10
7 respectively.

Output terminal 11 of limit value circuit 91, 93, 95
1, 113, and 115 are connected to corresponding input terminals of AND gate 117, respectively. The output terminal of this AND gate is connected to the input terminal of AND gate 119.

This AND gate 117 informs the three limit value circuits 9 that the signal in the displacement region exceeds the limit value.
If 1, 93, 95 is detected, AND gate 1
19 is supplied with a signal of logical value "1".

126 is a sign inversion detection circuit whose input terminals 121, 123, 125 are connected to output terminals 79, 81, 83 of the output circuit 42, respectively. In this sign reversal detection circuit 126, the input terminal 121
is connected to the input terminal of the exclusive OR gate 127,
The other input terminal of this OR gate is connected to the input terminal 123 of the sign reversal detection circuit and to the input terminal of another exclusive OR gate 129. The other input terminal of this latter OR gate is connected to the input terminal 125 of the sign reversal detection circuit. exclusive or gate 12
The output terminals of 7 and 129 are connected to the corresponding input terminals of the AND gate 131, and the output terminals of this AND gate are connected to the output terminals 13 of the sign inversion detection circuit 126.
3 and the input terminal 5 of the output circuit 42 to the other input terminal of the AND gate 119. The output terminal of the AND gate 119 is the output terminal 1 of the output circuit.
37 to generate a signal with a logical value of "1" in the displacement region.

In other words, these exclusive OR gates generate a logic "1" signal when one of their input terminals is supplied with a logic "1" signal and the other input terminal is supplied with a logic "0" signal. generate a signal. When the signals at the input terminals 121, 123, and 125 alternately take the logical values of "0", "1", and "0" in this order, as in the case of the displacement region shown in FIG. , exclusive or gate 127, 12
8 Therefore, a signal of logical value "1" is generated from AND gate 131, and in the displacement region, AND gate 1
17 produces a signal with a logic value of "1", so in this displacement region, the logic value of the output terminal 137 of the output circuit becomes "1", and this output terminal 137 generates a positional deviation indicating signal.

Since this positional deviation display signal is generated for displacement in both the horizontal and vertical directions, separate detection in both directions is not necessary.

In the illustrated embodiment, the same limit value is selected for each limit value circuit 91, 93, and 95, but it is also possible to use different limit values for each limit value circuit if desired. it is obvious.

In the above-described embodiment, the number of position-sequential image lines checked to detect positional deviation (or movement) is four, but it is clear that the minimum number of lines can be three. It is also clear that more than four lines may be selected as required.

Furthermore, the number of pixels in the horizontal direction used for positional deviation detection may be increased as required. For this purpose, for example, a circuit is provided at the output terminal 137 which produces a signal of logic "1" when a desired number of consecutive pixels produces a signal of logic "1" at the output terminal 137. You can also do that.

Furthermore, when using the basic idea of the invention based on the possibility of using field delay effects when using signal inversion detection circuits, if desired,
It is clear that subcircuits of different configurations may be used.

Furthermore, if the comparator circuit 15 is adapted to the field delay, (1 field period) + (1/2 line period) may be used as the field delay, if necessary, so that the position - A comparison of information from sequential lines can be made.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a positional deviation detection circuit according to the present invention, and FIG. 2 is a diagram for explaining phenomena utilized in the circuit of the present invention. 5... Field delay circuit, 15... Comparison circuit, 17, 19, 21... Subtraction circuit, 25, 29
...Delay line, 42...Output circuit, 49, 51, 5
3... Limiter circuit, 61, 63, 65... Multiplier (or amplifier), 91, 93, 95... Limit value circuit, 109... Limit value generation source, 117, 119
. . . AND gate, 126 . . . Sign inversion detection circuit, 127, 129 . . . Exclusive OR gate.

Claims (1)

[Scope of Claims] 1. A positional deviation detection circuit for an interlaced television signal, comprising: field delay means 5 for receiving a television signal; A plurality of difference code signals (S
[A-B], S[B-C], S[CD]) comparison means 17, 49; 19, 51; 21, 53
and said comparison means 17, 49; 19, 51; 21,
53, and the sequential difference sign signal (S[A-
B], S[B-C], S[C-D]) are different from each other, sign inversion detection means 12 generates a control signal.
6; and an output means 119 connected to the sign reversal detecting means and generating a positional deviation instruction signal in response to the control signal. 2. The positional deviation detection circuit according to claim 1, wherein the field delay means has a time delay of a period obtained by subtracting one line period from the field period. 3. The positional deviation detection circuit according to claim 1 or 2, wherein the sign inversion circuit includes at least one gate circuit having an exclusive OR gate function.