JPH0330533A - Multiplexing system for digital signal - Google Patents

Abstract

PURPOSE:To decrease the number of IC and to reduce a mounting area by serially connecting shift registers corresponding to the number of signals to be multiplexed and taking-out the multiplexed signals from the shift register in the final step. CONSTITUTION:When a common shift clock K is inputted to a shift clock terminal (h) after a latch signal R is supplied to respective shift registers 1,2,...,16 and respective signals S1-S64 are set, one type of data appear in a serial output terminal (e) of the shift register for each clock. Each time the shift clock K is inputted, the signals S4, S3, S2 and S1 are successively sent to a serial output terminal (f). Operation is samely executed for the shift register in the next step and the signals set to the shift register itself and signals sent from the shift register in the preceding step or before are sent as the output data. Thus, the increasing rate of the IC is fixed corresponding to the increase in the number of the signals to be multiplexed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal multiplexing system.

[Prior Art] FIG. 5 is a circuit diagram of a conventional digital signal multiplexing system. In the figure, (21) and (22) are the first stage 4-channel multiplexer, and (23).

(24) is a second-stage 4-channel multiplexer. (25) is a 4-channel multiplexer in the third stage. (2B) and (27) each reduce the input frequency by 1/
This is a frequency divider that divides the frequency by 4, and is connected in series to divide the clock frequency by 1/4, and then further divides the frequency by 1/4.

FIG. 6 is a time chart showing the operation in the digital signal multiplexing method of FIG. 5.

The multiplexer (21) has four signals (SL) to (B4
) is input and sequentially switched to output a multiplexed signal (A1). Similarly, the multiplexer (22) manually inputs four signals (B5) to (B8) and outputs the multiplexed signal (A2
) is output. Next, the second stage multiplexer (23)
are four respective multiplexed signals (A1) to (A4)
is input and sequentially switched to further multiplexed signal (B1
) is output. The signal (A3) is the signal (B9) to (S12
) is a multiplexed signal, and the signal (A4) is the signal (S
ta) to (St(i) are multiplexed signals.

Therefore, the signal (Bl) is multiplexed with a total of 1B channels (4 channels x 4 channels), and the signals (81), ... (813), (B2), ... (S
l4) (B3), ... (S15), C84>,
...(81G) are multiplexed.

Further, the third-stage multiplexer (25) receives four multiplexed signals (Bl) to (B4) and sequentially switches them to output a further multiplexed signal (C1).

Here, each of the signals (B1) to (B4) is a multiplexed signal of 16 channels, and therefore, the signal (C1) is a signal in which a total of B4 channels are multiplexed (1B channel x 4 channels). signal (Sl) as shown.
,...(S49) ,(85),...(S53)
(B9),...(S57), (813),...
・(881)... are multiplexed.

In this way, many channels were multiplexed by using multiplexers in the same stage.

[Problems to be Solved by the Invention] In conventional digital signal multiplexing systems, for example, a second-stage multiplexer is required to combine a 4-channel multiplexed signal and another 4-channel multiplexed signal into one signal. As the number of channels to be multiplexed increases, the number of multiplexers increases from not only the first stage to the second stage (13 stages), and as the number of stages increases further, a k-th frequency divider etc. that creates a signal to control the multiplexer is required. There is a problem in that an extra circuit is required, and the number of ICs is proportional to the number of channels.

This invention was made in order to eliminate the above-mentioned problem that a large number of ICs are required in proportion to the number of channels, and by reducing the number of multiplexing stages, the number of ICs is minimized. The purpose of this invention is to provide a digital signal multiplexing method with high implementation efficiency.

[Means for Solving the Problems] The digital signal multiplexing method according to the present invention is a multiplexing method for digital signals in which a plurality of shift registers each having several channels of parallel input terminals, serial input terminals, and serial output terminals are connected to one shift register. The shift registers are connected in series by connecting the serial output terminal of the register to the serial input terminal of another shift register. Then, multiplexed signals are input to the parallel input terminals of each shift register, and a common latch signal and shift clock signal are supplied to all shift registers.

[Function] In this invention, the signal supplied to the parallel input terminal of each shift register is set in each shift register by the latch signal O (supply).The signal supplied to the parallel input terminal of each shift register is set in each shift register by supplying the shift clock signal. The set signals are sequentially sent out, and the signals set in all the shift registers are sequentially sent out from the serial output terminal of the final stage shift register.

[Embodiment] FIG. 1 is a circuit diagram of a digital signal multiplexing device according to an embodiment of the present invention. In the figure, (1),
(2) and (1G) are shift registers, which have parallel input terminals (a) to (d), serial input terminal (e), serial output terminal (f), latch terminal (g), and shift clock terminal (11). have each.

Signals (St) to (B4) are connected to parallel input terminals (a) to (d) of shift register (1), and signal (B5)
~ (8g) or parallel input terminal (a) of shift register (2)
) to (d), and in the same way, the signal (B9)
~(SG(1) is connected to a shift register (not shown), and finally, signals (S61) to (S134) are connected to parallel input terminals (a) to (d) of the shift register (16). .

Furthermore, the serial output terminal (r) of the shift register (1) is connected to the serial input terminal (C) of the shift register (2), and the serial output terminal (r) of the shift register (2) is connected to the next shift register (Fig. connected to the series input terminal (not shown). Thereafter, the serial output terminal of the shift register is connected to the serial input terminal of the next stage shift register in the same manner. In this way, shift registers (1), (2)...(1
6) are connected in series, and the latch signal R and shift clock K are connected to the latch terminal (g) and the shift clock terminal T.
- (h) are commonly connected.

FIG. 2 is an explanatory diagram showing the contents of each shift register at the time of latching. The latch signal R is applied to each shift register (1),
(2) When supplied to the latch terminal (g) of (1G), the signals (Sl) to (B4
) is set, and the data of signals (S5) to (S8) are set in the shift register (2). Similarly, the data after the signal (S9) is set in the corresponding shift register, and the data of the signals (SGI) to (S[i4) are set in the shift register (tC) of each stage.

FIG. 3 is a term chart 1 showing the output data of each register. As mentioned above, each shift register (1
), (2)...(16) is supplied with the latch signal R and each signal (Sl) to (Sti4) is set, then the shift registers (1), (2), (1G
), when a shift clock K is commonly input to the shift clock terminal (11) of the shift registers, one piece of data appears at the serial output terminal (e) of the shift register for each clock.

In the shift register (1), every time the shift clock I is input, a signal (S4) is sent to the serial output terminal (r).
-(S3) -(S2) -(Sl) are sent out in sequence and sent to the data input terminal (0) of the shift register (2) as data output.

Also in the shift register (2), every time the shift clock K is input, a signal (S8) − is sent to the serial output terminal (r).
(S7) - (SG) - (S5) are sent out sequentially,
It is sent as data output E to the serial input terminal of the next stage shift register (not shown), and furthermore, the signal (S4) - (sa) input manually from the shift register <1)
(S2)-(Sl) is also sent as data output E to the serial input terminal of the next stage shift register. In this way, the encoder (2) outputs the signal (S8) as the data output E.
~(Sl) are sent out sequentially.

The same goes for the next-stage shift register, which sends out the signal set in itself and the signals sent from the previous-stage and previous shift registers as output data.

Therefore, the final stage shift register (1G) receives the latched signals (364) to (SGI) when the latch signal R is input.
In addition, the signals (S[io) to (Sl) sent out from the previous stage and the shift registers before it are sent out sequentially in synchronization with the shift clock K.

As described above, after setting each parallel input signal to the shift registers (1), (2), ... (16) simultaneously in one latch operation, the shift clock K corresponding to the number of channels is manually set. As a result, the multiplexed signal is output from the serial output terminal of the final stage shift register.

In addition, the increase in the number of channels is proportional to the number of channels.
This can be done by connecting registers one after the other in series.

FIG. 4 is a diagram showing the relationship between the number of No. 15s to be multiplexed and the number of ICs. In the conventional multiplexing system (see Figure 5), as the number of signals to be multiplexed increases, the number of circuits such as multiplexers, that is, the number of ICs, increases at an increasing rate. The rate remains constant.

[Effects of the Invention] As described above, according to the present invention, shift registers are connected in series according to the number of signals to be multiplexed, and the multiplexed signal is taken out from the final stage shift register. The number of ICs only increases monotonically as the number of signals to be multiplexed increases, and the number of ICs can be reduced compared to the conventional method.

The following effects are obtained by reducing the number of ICs.

(a) The mounting area can be reduced.

(b) Wiring man-hours during production of substrate patterns can be reduced.

(c) Current consumption can be reduced.

(d) Cost reduction.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a digital No. 13 multiplexing system + 14 diagram according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the contents of each shift register at launch, and FIG. 3 is an explanatory diagram showing the contents of each shift register at launch. Figure 4 is a diagram showing the relationship between the number of multiplexed signals and the number of ICs; Figure 5 is a circuit configuration diagram of a conventional digital signal multiplexing system; Figure 6 is a time chart showing output data;
The figure is a time chart showing the output signals of each multiplexer. In the figure, (1), (2), and (1G) are shift registers.舅servant 0 ■ ト■ C1') Nonono 4”J (+u 1ttlJ 1llu^
11ri), Deception Gi 11IJ Yariba υ

Claims (1)

[Claims] It has a plurality of shift registers each having several channels of parallel input terminals, serial input terminals, and serial output terminals, and connects the serial output terminals of the shift registers to the serial input terminals of other shift registers to serially connect the shift registers. A digital signal multiplexing method characterized in that the signals to be multiplexed are input to the parallel input terminals of each shift register, and a common latch signal and a shift clock signal are supplied to the shift registers.