JPH03201052A - Board identification system - Google Patents

Abstract

PURPOSE:To minimize the number of working poles of a connector and at the same time to easily identify a sub-board by sending serially the identification information given from the sub-board in response to the transmission of information carried out by a main board. CONSTITUTION:A sub-board 8 contains a dip switch 5 which can set the identification information on its own board and a board identification code setting shift register 4. The register 4 outputs a board identification code equivalent to one bit onto a data bit signal 3 with reception of the supply of a data output clock signal 1 equivalent to one pulse. Then the register 4 works so as to shift the board identification code by one bit. Therefore the board identification code is sent to the signal 3 as the serial data and then inputted to a main board 7 through the connector. Thus the sub-board 8 is easily identified from the board 7 while minimizing the number of working poles of a connector.

Description

TECHNICAL FIELD The present invention relates to a board identification system, and more particularly to a board identification system in an apparatus including a main board and a sub-board forming an expansion option board of the main board.

BACKGROUND ART In general, a method for identifying an expansion board is to provide an expansion board identification setting bit on the main board, and to set the expansion board identification bit each time an expansion board is mounted on the main board. However, in this type of board identification method, the main board has an expansion board identification bit, and when the expansion board is installed, the expansion board identification bit on the main board is set. Moreover, there is a drawback that the setting contents need to be changed every time the mounting configuration of the expansion board is changed.

Also, if the connector has a parallel bus,
There is also a method in which an identification bit is provided on the expansion board and the expansion board identification bit set for each expansion board is read out from the main board via a parallel bus. However, with this method, depending on the number of types of expansion boards, a plurality of bits are required to identify the boards, and a new parallel bus must be provided. This has the disadvantage that most of the poles of the connector may be used.

Purpose of the Invention The present invention was made in order to solve the above-mentioned conventional drawbacks, and its purpose is to minimize the number of pins used in the connector while making it possible to easily identify the sub-board from the main board. An object of the present invention is to provide a board identification system.

Configuration of the Invention A board identification system according to the present invention includes a main board,
A board identification system for a device including a sub-board that can be connected to the main board, wherein the sub-board serially sends identification information of its own board to the main board in response to information sent from the main board. It is characterized by having an identification information sending means.

In another board identification system according to the present invention, the identification information sending means of the sub-board includes a slot address generating means for generating a slot address indicating a connection position of the own board on the main board; a comparison means for comparing address information of
The present invention is characterized in that it includes sending means for serially sending identification information of the own board to the main board when the comparison result of the comparing means shows a match.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of a board identification system according to the present invention. In the figure, 7 is a main board, and 8 is a sub board.

The main board 7 has one slot consisting of a connector (not shown). A subboard 8, which is one of many types of expansion subboards, is connected to that slot. Further, the main board 7 is provided with a microprocessor 6.

The sub-board 8 includes a dip switch 5 in which identification information of the own board can be set, and a shift register 4 for setting a board identification code. This sub-board performs one function by being connected to a slot (not shown) of the main board. Therefore, various functions can be realized by replacing the sub-board with another type of sub-board as necessary. Further, identification information is assigned to each type of sub-board, and the main board can recognize the type of sub-board by obtaining the identification information, and only then can it operate.

The shift register 4 for setting the board identification code has a well-known shift register configuration, so when one pulse of the data output clock signal 1 is supplied, one bit of the board identification code is transferred onto the data bit signal 3. It operates to output and shift the board identification code set in the shift register 4 by one bit. Therefore, the board identification code is sent out as serial data on the data bit signal 3, and is input to the main board 7 via a connector (not shown). It is assumed that a three-state buffer (not shown) is provided at the output stage of the shift register 4.

Further, control signals supplied via a connector (not shown) between the main board 7 and the sub-board 8 are a data output clock signal 1, a data output enable signal 2, and a data bit signal 3. When the data output enable signal 2 is enabled, the board identification code can be output to the data bit signal 3.

The timing of outputting the board identification code on the data bit signal 3 is controlled by the data output clock signal 1. When the data output clock signal 1 is supplied, the board identification code set in the board identification code setting shift register 4 is output on the data bit signal 3 as serial data.

The data output clock signal 1 and the data output enable signal 2 are controlled by the microprocessor 6 on the main board 7.
will do.

The operation of the system of this embodiment having such a configuration will be explained using FIG. 2. Figure 2 shows data bit signal 3
3 is a conceptual diagram showing the relationship between the board identification code sent above and the value set in the shift register 4. FIG.

The board identification code set in the board identification code setting shift register 4 is specified in advance by the dip switch 5. Now, when the data output enable signal 2 is enabled, it causes the dip switch 5 to
Setting value rl101. J is set in the shift register 4 (FIG. 2(a)). In this state, the 3-state buffer 20 is enabled, and one bit of the board identification code, ie, " 1
" is output.

Next, when the data output clock signal 1 is applied while the data output enable signal 2 is enabled, the value of the shift register 4 is shifted by 1 bit, and the next 1 bit of the board identification code, that is, "0" is transferred to the data bit signal 3. (FIG. 2(b)). Thereafter, this operation is performed until all bits of the board identification code, ie, rll0IJ are read out.

However, if data output enable signal 2 becomes disabled during the shift operation, data bit signal 3
No board identification code is output on the screen. Furthermore, when the data output enable signal 2 becomes enabled again after that, the shift register 4 is newly set, and the board identification code can be read from the beginning. Note that the series of operations for reading the board identification code described above is performed by the microprocessor 6 on the main board 7.

Further, a micro sequencer may be provided in place of the microprocessor 6.

As described above, in this embodiment, it is possible to identify a sub-board mounted as an expansion board or an expansion option board of the main board. Furthermore, by using a shift register, an identification code, which is identification information, can be sent serially, making it easy to identify sub-boards that do not have a parallel bus consisting of a plurality of bits. Note that since it is sent serially, only one connector pole is needed.

FIG. 3 is a block diagram showing the configuration of a second embodiment of the board identification system according to the present invention, and parts equivalent to those in FIG. 1 are designated by the same reference numerals. In this example, a plurality of slots are provided on the main board, and sub-boards are arbitrarily connected to these slots to configure the device.

Further, it is assumed that each slot is given a slot address in advance. Furthermore, in the case of this example, a system is adopted in which a slot address is specified on the main board side, and the subboard mounted in the specified slot sends out identification information.

The dip switch 10 is provided to realize this method. These are a slot address register 11 and an address comparison circuit 12. That is, they are provided on each sub-board, and when connecting to a slot on the main board, the address of that slot is set in the dip switch 10. Then, the slot address sent from the main board side is compared with the address set in the dip switch, and only if the comparison result shows a match, the shift register 4 is used to transfer the identification information of the own board. It is sent to the main board side.

In addition, in the figure, main board 7 - expansion sub board 8
Control signals supplied through a connector (not shown) between them are a data output clock signal 1, an address output enable signal 2, a data bit signal 3, and a data output enable signal.

In this configuration, when the address output enable signal 2 becomes enabled, the slot address is output on the data bit signal 3. Note that at this time, the data output enable signal 9 is in a disabled state.

When the address output enable signal 2 becomes enabled, all sub-bots take in the slot address output on the data bit signal 3 into the slot address register 11. The slot address register 11 has a shift register configuration, and when the data output clock signal 1 is supplied, one bit of the slot address outputted in synchronization with one data output clock signal 1 is transferred to the slot address register 11. The next slot address is taken in and shifted by one bit by data output clock signal 1, which is the timing to take in the next slot address.

Note that the data output clock signal 1, address output enable signal 2, and data output enable signal 9 are controlled as follows.
The microprocessor 6 on the main board 7 performs this.

When the slot address for all pits is latched in the slot address register 11, the address comparison circuit 12 compares the value of the register with the value set by the slot address setting dip switch 10. As mentioned above, the slot address setting dip switch 10 of the sub-board is set with a unique address for each slot. Therefore, the outputs of the address comparator circuits 12 of a plurality of sub-boards do not simultaneously indicate a match.

Next, the comparison operation in the address comparison circuit will be explained in detail.

FIG. 4 is a block diagram showing the relationship between the value set in the slot address register and the slot address. The figure shows a case where a total of two sub-boards 80 and 81 are mounted on the main board.

The slot address output on the data bit signal 3 is latched into the slot address registers 110, 111 on each sub-board as described above. Also, the slot address of the sub-board is set using the slot address setting dip switch 100. lot for each slot.
A fixed address value is set.

In this example, it is assumed that the sub-board 80 is set to a slot address of r l0IOJ, and the sub-board 81 is set to a slot address of r l0IIJ. Therefore, when r l0IOJ is latched in the slot address registers 110 and 111, respectively, as shown in the figure, in the sub-board 80, the address comparison circuit 120 determines whether the slot addresses match, and the sub-board 80
1, the address comparison circuit 121 determines whether the slot addresses do not match. When the address comparison circuit determines that the slot addresses match, output of the board identification code of the sub-board to the data bit signal 3 is permitted.

Returning to FIG. 3, when the data output enable signal 9 is enabled, the board identification code can be output on the data bit signal 3. At this time, address output enable signal 2 is in a disabled state.

The timing of outputting the board identification code on the data bit signal 3 is controlled by the data output clock signal 1. When the data output clock signal 1 is supplied, the board identification code set in the board identification code setting shift register 4 is output on the data bit signal 3 as serial data.

Note that the control of the data output clock signal 1, address output enable signal 2, and data output enable signal 9 is performed by the microprocessor 6 of the main board 7.

The board identification code setting shift register 4 has a shift register configuration similar to the first embodiment described above, so when one pulse of the data output clock signal 1 is supplied, it sets one bit of the board identification code. It operates to output on the data bit signal 3 and shift the board identification code set in the shift register 4 by one bit. Therefore, the board identification code is sent out as serial data on the data bit signal 3 and is input to the main board 7 via a connector (not shown). In this example, as in the first embodiment, a 3-state buffer (not shown) is provided at the output stage of the shift register 4, and a shift operation is performed as shown in FIG. shall be.

In other words, since there are multiple slots in this embodiment,
The system uses a system in which a slot address is specified from the main board, and only the sub-boards connected to that slot send out identification information. Therefore, in order to identify the subboards of all slots, it is sufficient to send out the addresses of all slots in order.

As described above, in this embodiment as well, it is possible to identify a sub-board mounted as an expansion board or an expansion option board of the main board. Furthermore, as in the case of the first embodiment, the identification code, which is identification information, can be transmitted serially, making it easy to identify sub-boards that do not have a parallel bus consisting of multiple bits.

Furthermore, the day knob switch, shift register, etc. in the first and second embodiments are separated from other circuits on the sub-board, so they are highly independent and can have the same circuit configuration. Therefore, modularization is possible.

Therefore, multiple sub-boards that do not have the same bus configuration can be identified using the same method. If this system is adopted in a device that needs to identify the expansion board that is present and perform initial settings according to the type of expansion board, it will be possible to easily identify the subboard.

As described in detail, the present invention serially sends identification information from the sub board in response to information sent from the main board, thereby making it easy to connect the sub board while minimizing the number of pins used in the connector. This has the effect of making it possible to identify the board.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a board identification system according to a first embodiment of the present invention, FIG. 2 is a conceptual diagram showing identification information sent from a shift register, and FIG. 3 is a block diagram showing the configuration of a board identification system according to a first embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of the board identification system according to the embodiment. FIG. 4 is a block diagram showing the comparison operation in the second embodiment. Explanation of symbols of main parts 4...Board identification code setting shift register 5.10...Dip switch 11...
・Slot address register 12...Address comparison circuit input NEC Corporation

Claims (2)

[Claims] (1) A board identification system for a device including a main board and a sub-board that can be connected to the main board, wherein the sub-board identifies its own board to the main board in response to information sent from the main board. A board identification system comprising identification information sending means for serially sending out identification information. (2) The identification information sending means of the sub-board compares the slot address with the address information from the main board and the slot address generating means that generates a slot address indicating the connection position of the own board on the main board. The board identification system according to claim 1, further comprising a comparison means and a sending means for serially sending the identification information of the own board to the main board when the comparison result of the comparing means indicates a match. .