JPH033018U - - Google Patents

Info

Publication number
JPH033018U
JPH033018U JP6461189U JP6461189U JPH033018U JP H033018 U JPH033018 U JP H033018U JP 6461189 U JP6461189 U JP 6461189U JP 6461189 U JP6461189 U JP 6461189U JP H033018 U JPH033018 U JP H033018U
Authority
JP
Japan
Prior art keywords
power supply
panels
power
activation information
startup
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6461189U
Other languages
Japanese (ja)
Other versions
JP2503299Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6461189U priority Critical patent/JP2503299Y2/en
Publication of JPH033018U publication Critical patent/JPH033018U/ja
Application granted granted Critical
Publication of JP2503299Y2 publication Critical patent/JP2503299Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Control Of Voltage And Current In General (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例の構成図、第２図は
第１図の実施例の要部の起動制御回路の回路図、
第３図は第２図のＮＡＮＤゲート回路の動作説明
図である。 １……電源盤制御回路、２……トランジスタ、
３……Ｘｉ情報受信端子、４……Ｙｉ，Ｚｉ，Ｗ
ｉ，Ｐｉ報受信端子、５……ＮＡＮＤゲート回路
、６〜９……ダイオード、１０……ツエナーダイ
オード、１１〜１４……抵抗、１５〜１９……ス
イツチ、２０〜２４……電源盤、２５……電源入
力端子、２６……電源出力端子。 Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of a starting control circuit of the main part of the embodiment of Fig. 1,
FIG. 3 is an explanatory diagram of the operation of the NAND gate circuit of FIG. 2. 1...Power panel control circuit, 2...Transistor,
3...X i information receiving terminal, 4...Y i , Z i , W
i , Pi information reception terminal, 5...NAND gate circuit, 6-9...diode, 10...Zener diode, 11-14...resistor, 15-19...switch, 20-24...power board, 25...Power input terminal, 26...Power output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数台の電源盤を同時に並列起動させる電源盤
起動制御回路において、前記電源盤の起動スイツ
チ投入情報を出力する送信回路と、前記複数の電
源盤の起動スイツチ投入情報を受信し論理処理す
る論理回路と、前記論理回路の制御により動作す
る電源盤出力制御回路とを前記複数の電源盤のそ
れぞれに備えたことを特徴とする電源盤起動制御
回路。 In a power supply panel startup control circuit that simultaneously starts multiple power supply panels in parallel, a transmission circuit outputs startup switch activation information of the power supply panels, and a logic circuit receives and logically processes startup switch activation information of the plurality of power supply panels. and a power panel output control circuit that operates under the control of the logic circuit, each of the plurality of power panels.
JP6461189U 1989-06-01 1989-06-01 Power board start control circuit Expired - Lifetime JP2503299Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6461189U JP2503299Y2 (en) 1989-06-01 1989-06-01 Power board start control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6461189U JP2503299Y2 (en) 1989-06-01 1989-06-01 Power board start control circuit

Publications (2)

Publication Number Publication Date
JPH033018U true JPH033018U (en) 1991-01-14
JP2503299Y2 JP2503299Y2 (en) 1996-06-26

Family

ID=31595708

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6461189U Expired - Lifetime JP2503299Y2 (en) 1989-06-01 1989-06-01 Power board start control circuit

Country Status (1)

Country Link
JP (1) JP2503299Y2 (en)

Also Published As

Publication number Publication date
JP2503299Y2 (en) 1996-06-26

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