JPS5847930U - Double press clear circuit - Google Patents
Double press clear circuitInfo
- Publication number
- JPS5847930U JPS5847930U JP14042181U JP14042181U JPS5847930U JP S5847930 U JPS5847930 U JP S5847930U JP 14042181 U JP14042181 U JP 14042181U JP 14042181 U JP14042181 U JP 14042181U JP S5847930 U JPS5847930 U JP S5847930U
- Authority
- JP
- Japan
- Prior art keywords
- turned
- clear circuit
- time
- press clear
- double
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の実施例を示す回路図、第２図は動作説
明図である。
１・・・ＯＲ回路を示す、２・・・ＡＮＤ回路を示す、
３・・・ＮＯＴを示す、Ｘ・・・シーケンサの入力を示
す、−Ｙｏ・・・シーケンサの出力を示す、Ｙ工・・・
シーケンサの中間出力を示す、Ｙ２． Ｙ３・・・シー
ケンサの中間出力を示す。FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is an operation explanatory diagram. 1... indicates an OR circuit, 2... indicates an AND circuit,
3...Indicates NOT, X...Indicates sequencer input, -Yo...Indicates sequencer output, Y...
Y2. shows the intermediate output of the sequencer. Y3: Indicates the intermediate output of the sequencer.
Claims (1)
て、−個のモーメンタリ−ａ接点を有するスイッチがシ
ーケンスの入力として、一度目のＯＮのとき、二度目の
ＯＮのとき、二度目のＯＮのとき、Ｎ度目のＯＮのとき
繰返していったとき、誉の出力が順次０Ｎ−ＯＦＦを繰
返すことを特徴とする二度押しクリア回路。 ２ 実用新案登録請求の範囲第１項において、前記出力
がＯＮのとき、停電で自動的にＯＦＦにクリアされる停
電時力ＯＦＦになることを特徴とする二度押しクリア回
路。[Claims for Utility Model Registration] 1. In an operating circuit controlled by a manually operated switch, when a switch having - momentary A contacts is turned ON for the first time, when it is turned ON for a second time, as a sequence input, A double-press clear circuit characterized in that the output of Homare sequentially repeats 0N-OFF when it is turned on for the second time and when it is turned on for the Nth time. 2. The double-press clear circuit according to claim 1, characterized in that when the output is ON, it is automatically cleared to OFF in the event of a power outage, resulting in a power OFF state in the event of a power outage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14042181U JPS5847930U (en) | 1981-09-24 | 1981-09-24 | Double press clear circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14042181U JPS5847930U (en) | 1981-09-24 | 1981-09-24 | Double press clear circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5847930U true JPS5847930U (en) | 1983-03-31 |
Family
ID=29933582
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14042181U Pending JPS5847930U (en) | 1981-09-24 | 1981-09-24 | Double press clear circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5847930U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009016045A (en) * | 2007-06-29 | 2009-01-22 | Panasonic Electric Works Co Ltd | Electronic switch device |
-
1981
- 1981-09-24 JP JP14042181U patent/JPS5847930U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009016045A (en) * | 2007-06-29 | 2009-01-22 | Panasonic Electric Works Co Ltd | Electronic switch device |
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