JPH0329992A - Display device - Google Patents

Abstract

PURPOSE:To normally display a picture transmitted with picture elements thinned in the vertical direction by transferring every one-line display data from a dynamic RAM in a dual port memory to a serial memory at intervals of 2''-number of picture elements in accordance with the set value of a register and the counted value of a vertical counter which counts the number of display picture elements in the vertical direction. CONSTITUTION:A control means 4 is provided which transfers every one-line display data from the dynamic RAM is the dual port memory constituting a frame memory 5 to the serial memory at intervals of 2<n>-number of picture elements in accordance with the set value of a register 3 which sets the interval of display picture elements in the vertical direction and the counted value of a vertical counter 2 which counts the number of display picture elements in the vertical direction. Since an address signal and many control signals are shared among frame memories 5, the number of signal lines is reduced even in a color picture display device or the like having plural frame memories 5. Thus, the picture transmitted with picture elements thinned in the vertical direction is normally displayed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention uses video signals to create images or characters (hereinafter referred to as
It relates to a display device that displays (generally referred to as image data) on a CRT, liquid crystal, or the like.

[Prior Art] Conventionally, a frame memory for storing image data,
2. Description of the Related Art A display device is known that includes a D/A converter that converts image data read from a frame memory into an analog signal, and a video signal control section that controls these converters to produce a video signal. In a conventional display device, image data is read out from a frame memory and displayed by the number of display pixels in the vertical direction set in advance in the device. Also,
Color image display devices use RGB method, luminance color difference method (
Each of the Y, I, and Q formats is equipped with three frame memories, and image data is stored in all frame memories.

[Problems to be Solved by the Invention] In conventional color image display devices, there is no need to display the image coarsely. However, in image transmission devices, etc., the image data is compressed and transmitted, and when the received image data is expanded and displayed, there is no problem if the data is written to all frame memories. ,
For example, if image data is transmitted after being thinned out every other pixel, even if it is expanded, only every pixel number will be written to the frame memory on the receiving side, so the entire contents of the frame memory will not be displayed. If it is removed, a problem arises in that the original image cannot be seen.

This problem occurs when, for example, the frame memory is configured with 512 pixels horizontally x 512 pixels vertically.
This occurs when the pixels are thinned out and transmitted, such as 256 pixels x vertically, or 128 pixels horizontally x 128 pixels vertically. In addition, in the luminance color difference method, color difference signals (I
The frequency of the luminance signal (Y signal) is lower than that of the luminance signal (Y signal), and it has almost no effect on image quality even if it is transmitted at two-pixel intervals. Therefore, the same problem occurs when only the color difference signal is transmitted at two-pixel intervals. A problem arises.

Frame memories used in color image display devices include dynamic RAM, static RAM, and dual-boat RAM, but no matter which type of frame memory you choose, three things must be done to solve the above problem. It is necessary to separately supply analog signals and control signals for reading to the frame memory. However, this method has the problem that the number of signal lines increases and it is not easy to implement it into an IC.

The present invention has been made in view of these points, and an object of the present invention is to provide a display device that can normally display an image transmitted by thinning out pixels in the vertical direction. .

[A Thousand Steps to Solve the Problem] In the present invention, in order to solve the above problem, the first step is to solve the problem.
As shown in the figure, there is a frame memory 5 consisting of a dual-board memory that has a dynamic RAM for storing image data and a serial memory for outputting serial data, and a frame memory 5 that stores data read from the frame memory 5 in an analog format. In a display device comprising a D/A converter 6 for converting into a signal, and a video signal control section 31 for controlling these and creating a video signal, a register 3 for setting display pixel intervals in the vertical direction is provided, and a register 3 for setting display pixel intervals in the vertical direction is provided. Depending on the set value of register 3 and the count number of vertical counter 2 that counts the number of display pixels in the vertical direction, transfer of each display line from the dynamic RAM in the dual board 1 to the memory to the serial memory is performed at power-of-two pixel intervals. The present invention is characterized in that it is provided with a control means for controlling.

[Function] According to the present invention, the frame memory 5 is thus stored in accordance with the set value of the register 3 that sets the display pixel interval in the vertical direction and the count number of the vertical counter 2 that counts the number of display pixels in the vertical direction. A control means is provided to transfer each display line from the dynamic RAM in the constituent dual port memory to the serial memory at power-of-two pixel intervals, so that the transmitted image can be displayed normally by thinning out pixels in the vertical direction. It is something that can be done. In particular, even when there are multiple frame memories 5, such as in a color image display device, the present invention allows many of the address signals and control signals to be shared for each frame memory 5, so it is possible to reduce the number of signal lines. It is possible.

[Example] FIG. 1 is a block diagram of one embodiment of the present invention.

The video signal control unit 1 is composed of a vertical counter 2, a setting register 3, a logic circuit 4, and a control circuit necessary for image display. Creating the necessary signals. The vertical counter 2 inputs the horizontal synchronization signal HD obtained from the composite synchronization signal, and as shown in FIG.
The horizontal synchronization signal HD is counted at the rising edge of the signal, and the count value is output. In FIG. 2, count values VA O , VA 1 . , VA 2 is shown. The setting register 3 is a register for setting the pixel spacing in the vertical direction, and its set value is given from the outside. In this embodiment, the setting register 3 is configured with 2 bits, and four display methods can be selected.

The frame memory 5 is a dynamic RAM and is composed of a dual port memory having a serial memory for serial data output, and is connected to the video signal control section 1 for address signals, data signals, and other control signals. The image data output from the frame memory 5 is connected to the digital input of the D/A converter 6, is latched by the rising edge of the clock signal DACLK, and is converted into an analog signal. This analog signal is combined with analog signals and synchronization signals similarly output from other frame memories 5, output as a video signal, and an image is displayed on a display device such as a CRT or liquid crystal.

In the frame memory 5, image data for the next line is transferred from the dynamic RAM in the dual port memory to the serial memory from the end of displaying one line in the horizontal direction to the start of displaying the next line. It is necessary to create a cycle to do so.

In this embodiment, one line of image data is transferred after the horizontal synchronization signal rises. This image data transfer cycle is controlled by a dynamic RAM refresh control signal RAS, a transfer control signal CAS from the dynamic RAM to the serial memory, and other control signals. The serial memory is composed of a ring-shaped shift register, and one line of image data transferred to the serial memory is shifted by a clock signal given to the serial memory, and is sequentially output serially and simultaneously written to the beginning. . Therefore, if there is no image data transfer cycle, the same image data as the previous line will be written again, and the same image as the previous line will be displayed.

Now, in the second display operation, the logic circuit 4 generates a control signal CAS to each frame memory 5 based on the lower three bits I of the count value of the vertical counter 2 and the setting value of the setting register 3. are doing.

In this embodiment, the setting register 3 is composed of 2 bits, and four types of display from mode 0 to mode 3 can be selected for each frame memory 5.

When mode O is all-pixel display, mode 1 is 2-pixel interval display, mode 2 is 4-pixel interval display, and mode 3 is 8-pixel interval display, the control signals CAS and RAS in each mode are
is shown in Figure 2. A reference control signal CASO is input to each logic circuit 4. In all-pixel display mode ○, the reference control signal CASO is changed to the control signal C.
A. Output as S. In mode 1 of two-pixel interval display, when the count value VAO is at the "I Lo, I+ level," the reference control signal CASO is output as the control signal CAS.

In mode 2 of 4-pixel interval display, count values VAO and V
When both AIs are at the "Lou+" level, the reference control signal CASO is output as the control signal CAS. In mode 3 of 8-pixel interval display, the count value VA
O, VA 1, VA 2 are all II LoIUI+
When the signal is at the level, the reference control signal CASO is output as the control signal CAS. In this way, the logic circuit 4
By configuring the control signal CAS, the control signal CAS can be applied to the frame memory 5 at every power-of-two pixel interval.

Then, the control signal C A. In a cycle in which S is not output to the frame memory 5, the dynamic RAM is only refreshed by the control signal RAS, and image data is not transferred from the dynamic RAM to the serial memory for serial data output. Therefore, the same image data is displayed for power-of-two pixels in the vertical direction. It goes without saying that image data is displayed pixel by pixel in the horizontal direction.

As described above, in the present invention, a dual port memory is used as the frame memory 5, and in the horizontal direction, image data is serially output pixel by pixel, and in the vertical direction, power-of-2 pixels are output with the same image data. Since the image can be displayed, the transmitted image can be displayed normally by thinning out the pixels in the vertical direction. For example, if one of the three iL-me memories 5 is used for luminance signals and the other two are used for color difference signals, the luminance signals (Y signals) at ':' Transmits all pixels,
When the color signals (I signal, Q signal) are transmitted in the vertical direction at intervals of 2 times, the setting 1/register . By setting TIt 4 second to 0 and setting the setting register 3 corresponding to the frame memory 5 that stores color difference signals to mode 1, a color image can be displayed normally.

In addition, if the image data transmitted using the RGB method is compressed to 172 or 1/4 pixels in the vertical direction, simply setting each setting register 3 to mode 1 or mode 2 will allow the compressed data to be compressed. Image data can be expanded and displayed normally.

In any of the above cases, the same address signal and control signal can be used in common for each frame memory 5, and the number of signal lines can be reduced. therefore,
The video signal control section 1 can be easily integrated into an IC.

In the above embodiment, an apparatus that realizes display at intervals of up to 8 pixels has been exemplified, but if a coarser display is required, the number of bits in the setting register 3 may be increased and a similar logic circuit 4 may be configured.

[Effects of the Invention] In the display device of the present invention, a frame memory is configured by a set value of a register that sets the display pixel interval in the vertical direction and a count number of a vertical counter that counts the number of display pixels in the vertical direction. Since we have provided a control means that transfers each display line from the dynamic RAM in the dual port memory to the serial memory for serial data output at power-of-two pixel intervals, it is possible to thin out the pixels in the vertical direction and transmit the image. This has the effect that it can be displayed normally.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is an operational waveform diagram of the same. 1 is a video signal control section, 2 is a vertical counter, 3 is a setting register, 4 is a logic circuit, 5 is a frame memory, and 6 is a D/A converter.

Claims (1)

[Claims] (1) Dynamic RAM for storing image data
A frame memory consisting of a dual port memory with a serial memory for serial data output, a D/A converter that converts the data read from the frame memory into an analog signal, and a video signal is created by controlling these. In a display device consisting of a video signal control unit for displaying a dual port, a register is provided to set the display pixel interval in the vertical direction. 1. A display device comprising a control means for transferring each display line from a dynamic RAM in a memory to a serial memory at power-of-two pixel intervals.