JPH07327241A - Video display device - Google Patents

Abstract

PURPOSE:To perform the processing for display in a small circuit scale by displaying a picture on the display device where display elements corresponding to plural colors are mosaicked. CONSTITUTION:RGB signals are sampled in point sequence by a multiplexer 2 and are converted to the signal where RGB are arranged at intervals of the sampling time in time series. This signal is converted at the same timing as this sampling by an A/D converter 3 and is stored as an interlace signal in a frame memory 4 at the same timing. The signal is read out from the frame memory 4 at the speed which is twice as high as the speed of write to the frame memory 4, and it is converted by a D/A converter 5 and is amplified to a liquid crystal driving voltage by an amplifier 6 and is sent to the input line of an LCD 7. The LCD 7 has the RGB mosaic picture element structure and it matched the time-series RGB arrangement of the scan convert signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for displaying an input video signal such as a video signal on a display device having a structure in which color display elements are arranged in a mosaic, and in particular, it is scan-converted into a double speed non-interlace signal for display. The present invention relates to a video display device suitable for application to a video display device displayed on a device.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 7, a device of this type conventionally performs A / D conversion on Y and C signals of an input video signal (video signal) separately by A / D converters 91 and 92. Then, it was stored in the frame memories 94 and 95, read out at a double speed, and then D / A converted by the D / A converters 97 and 98 to perform scan conversion into a double speed non-interlace. And after this, R at the decoder 99
Converted to a GB signal, and RG is displayed on the display device such as LCD 90.
The B signal was supplied for color display. 9
3 is a SYNC separator, and 96 is a timing controller.

[0003]

However, the above conventional example requires a processing circuit including a frame memory or the like for each of the Y signal and the C signal. Therefore, the required capacity of this memory, the circuit scale and the cost as a whole are required. Had the drawback of being bulky. Further, the decoder 99 has a drawback that it cannot process a general-purpose decoder (for normal signal processing) because it processes a double speed signal.

[0004]

A first image display apparatus of the present invention comprises a forming means for forming a dot-sequential color signal in which a plurality of color signals are arranged in a time-series in a dot-sequential manner, and the dot-sequential forming means. And a display device having a structure in which color signals are sent and display elements corresponding to the plurality of colors are arranged in a mosaic manner.

A second image display device of the present invention is the image display device, wherein the array of the plurality of color display elements in the scanning line direction of the mosaic structure of the display device and the dot-sequential color signal are arranged. It is characterized in that the arrangement of a plurality of color signals is made equal. Further, a third video display device of the present invention is the second video display device, wherein the forming means has a storage means for storing the plurality of color signals,
Before writing the plurality of color signals in the storage means, the arrangement of the plurality of color signals of the signals written in the storage means is made equal to the arrangement of the plurality of color display elements of the mosaic structure of the display device. It is characterized by having done.

A fourth video display device of the present invention is the third video display device according to the third video display device, wherein the storage means is provided when the plurality of color signals are written in or read from the storage means. The two-dimensional color array of the signals stored in or the read signal from the storage means is made equal to the two-dimensional array of the color display elements of the mosaic structure of the display device. Characterize.

Further, in a fifth image display device of the present invention, in the third or fourth image display device, a writing speed to the storage means and a reading speed from the storage means are different from each other. Is characterized by.

Further, a sixth video display device of the present invention is characterized in that, in the fifth video display device, the read speed is set to be twice the write speed.

A seventh image display apparatus of the present invention is the image display apparatus according to any one of the third to sixth aspects, wherein the plurality of color signals of the plurality of color signals are added before the forming unit is written in the storage unit. Each of them is sampled dot-sequentially to form the dot-sequential signal, and at least the dot-sequential sampling of the plurality of color signals and the writing to the storage means are performed in synchronization.

An eighth image display apparatus of the present invention is the image display apparatus according to any one of the third to seventh aspects, wherein at least timing control is performed such that reading of the storage means and driving of the display device are synchronized with each other. System or the same timing control system.

Further, a ninth image display device of the present invention is the image display device according to any one of the third to eighth aspects, wherein the signal is delayed from the storage means to the display device. It is characterized in that the timing of reading from the storage means and the timing of writing to each display element of the display device are shifted.

The tenth image display device of the present invention is
In the video display device according to any one of the first to ninth aspects, the forming unit samples each of the plurality of color signals generated in a process of encoding a signal taken out from the image pickup device in a dot-sequential manner, and outputs the dot-sequential signal. Is formed.

The eleventh video display device of the present invention is
In the video display device according to any one of the first to tenth aspects,
The display device is characterized by using a liquid crystal.

[0014]

According to the first image display device of the present invention, a display having a structure in which a plurality of color signals are dot-sequential color signals arranged in time series and the display elements corresponding to the plurality of colors are arranged in a mosaic pattern. By displaying with a device, it is possible to perform a display process with a circuit scale smaller than that of a conventional device, and a general-purpose circuit can be used.

The second image display device of the present invention is the same as the first image display device, wherein the array of the plurality of color display elements and the dot sequential color in the scanning line direction of the mosaic structure of the display device. By making the arrangement of the plurality of color signals of signals equal, the display device drive sequence is simplified and the circuit scale is further reduced. Further, in a third image display device of the present invention, the forming means further has a storage means for storing the plurality of color signals, and the storage means stores the plurality of color signals in the storage means before writing the plurality of color signals in the storage means. By making the arrangement of the plurality of color signals of the written signal equal to the arrangement of the plurality of color display elements of the mosaic structure of the display device, even if the storage capacity is small, the access speed to the storage means is also small. Is configured so that display processing can be performed at the latest.

In the fourth image display device of the present invention, the signals stored in the storage means or the storage means when the plurality of color signals are written in or read out from the storage means. By making the two-dimensional color array of the read signals from the same as the two-dimensional array of the plurality of color display elements of the mosaic structure of the display device, a dot-sequential memory can be realized. It is also possible to process a signal for each scanning line.

Further, in a fifth video display device of the present invention, in the third or fourth video display device, a writing speed to the storage means and a reading speed from the storage means are different from each other. The processing such as scan conversion can be realized by using only a small capacity memory and a general-purpose circuit.

The sixth video display device of the present invention is the same as the fifth video display device, wherein the so-called interlaced signal is converted into a non-interlaced signal by setting the read speed to twice the write speed. Is also realized with a small circuit scale.

A seventh image display device of the present invention is the image display device according to any one of the third to sixth aspects, wherein the plurality of color signals of the plurality of color signals are added before the forming means is written in the storage means. Each of them is sampled dot-sequentially to form the dot-sequential signal, and at least the dot-sequential sampling of the plurality of color signals and the writing to the storage means are performed in synchronization with each other, thereby facilitating the storage address of each color signal. It enables management and facilitates subsequent processing.

The eighth image display device of the present invention is the image display device according to any one of the third to seventh aspects, wherein the signal read from the storage means is transmitted to each display element of the display device. At least the reading of the storage means and the driving of the display device are controlled by a timing control system which is synchronized with each other or the same timing control system so that the writing is performed at a timing without color shift.

The ninth video display device of the present invention is the video display device according to any one of the third to eighth video display devices, wherein the delay time of the signal from the storage means to the display device corresponds to By shifting the read timing from the storage means and the write timing to each display element of the display device, the color misregistration on the display device can be eliminated only by controlling the read timing of the storage element and the drive timing of the display element. It is a thing. A tenth video display device of the present invention is the video display device according to any one of the first to ninth video displays, wherein each of the plurality of color signals generated in the process of encoding the signal extracted from the imaging device is dot-sequentially. By sampling and forming the dot-sequential signal, simplification of the circuit configuration in the display device including the camera is realized.

[0022]

Embodiments of the present invention will be described in detail below with reference to the drawings. [Embodiment 1] FIG. 1 is a system configuration block diagram showing a first embodiment of the present invention. Here, 1 is an RGB decoder to which a composite (denoted as video in the figure) or Y / C video signal is input. This decoder 1 converts the signals into RGB primary color signals, and each primary color signal enters a multiplexer 2. This multiplexer 2
Each RGB signal is sampled sequentially by RGB
.. and RGB are converted into signals lined up in time series for each sampling time. Then, this signal is A / D converted by the A / D converter 3 at the same timing as this sampling, and further stored in the frame memory 4 as an interlaced signal at the same timing. Next, the signal is read from the frame memory 4 at a speed twice as fast as the writing speed to the frame memory 4,
After D / A conversion by the D / A converter 5, it is amplified to a liquid crystal drive voltage by the amplifier 6 and sent to the input line of the LCD 7. By reading at this double speed, the signal is scan-converted to double speed, and D is synchronized with this timing.
/ A convert and write to LCD 7. Here, the LCD 7 has an RGB mosaic pixel structure, and the arrangement in the scanning line direction is RGBRGB ..., Which coincides with the above-described time-series RGB arrangement of scan conversion signals. In the LCD 7, 71 is a horizontal shift register, 72 is a vertical shift register, and 73 is RGB.
Array pixel (display element) 74, horizontal shift register 7
A signal transfer transistor controlled by 1.
Is a vertical signal line connected to the transistor 74, and 76 is a horizontal signal line connected to the vertical shift register 72.

The above is a rough signal flow.
Shows the details of the signal processing here. In the figure, 10
Represents RGB primary color signals in field units.
Reference numeral 11 represents a signal sampled by the multiplexer 2 in time series and dot-sequentially for each field. That is, the signal after sampling is simply RGB in the scanning line direction.
The signals are arranged in time series with the sampling period as a unit. Next, this signal is A / D converted in synchronization with this sampling period and then stored in the frame memory 4 as an interlace signal. At that time, the write timing for one pixel is adjusted back and forth for each scanning line, Mosaic RGB written on the memory 4
The two-dimensional array of signals is made equal to the two-dimensional array of RGB pixels of the LCD 7. The signal processing for making the pixel array of the LCD 7 equal to the two-dimensional array may be performed when the signal is read from the frame memory 4. After that, the frame memory is read at double speed, and D is read.
A / A conversion, amplification, transmission to the LCD 7 and writing to the LCD. At this time, the read cycle, the D / A conversion cycle, and the write cycle of the LCD are all matched, and
Strict timing control is performed so that the RGB array of the signals stored in the frame memory 4 is directly written and displayed in each corresponding RGB pixel on the LCD. For example, FIG. 3 shows read set pulses RRS and L for determining the read start timing of the frame memory.
A timing chart with a horizontal shift register start pulse HST that determines the write start timing of CD is shown. The time difference Δt between the RRS and the active edge of HST is the same as that of the D / A converter 5 that exists in the process from reading to LCD. It is designed to match the total delay time of the amplifier 6. With this configuration, the mosaic RG on the frame memory
The B signal array corresponds 1: 1 to the RGB pixel array of the LCD. Therefore, the capacity of the frame memory required for the scan conversion processing of this embodiment is equal to the number of bytes of pixels of the LCD, which is much smaller than the conventional one.

For example, in the conventional scan conversion processing, two frame memories for Y and C are required as described above, and the proper sampling frequency is more than double the number of pixels of the LCD according to the Nyquist theorem. Therefore, the total memory capacity is required to be four times or more that of this embodiment. [Embodiment 2] FIG. 4 is a block diagram of a scan conversion unit showing a second embodiment of the present invention. The pre-process of the A / D converter 3 and the post-process of the D / A converter 5 are the same as in the first embodiment. Further, FIG. 5 shows an explanatory diagram of the signal processing here. First, the RGB time-series signals 21 A / D converted by the A / D converter 3 are sequentially stored in the three line memories 41. In this example as well, the RGB arrangement in each scanning line direction is the LCD pixel It is sampled to be equal to the RGB array. Next, each line is read twice at twice the speed of writing to the line memory 41 and sent to the register 42 and the arithmetic unit 43. Calculator 43
Then, the average value of the signals of the front and rear lines ((l _n + l _{n + 1} ) /
2) is calculated. That is, the interpolation calculation of the preceding and following lines is performed. Further, the register 42 delays the signal for the time required by the arithmetic unit 43. Then, the double-speed signal 22 from the register 42 and the double-speed output signal 23 from the arithmetic unit 43 are alternately selected by the multiplexer 44 in a 2f _H cycle to obtain the line-interpolated double-speed signal 24. This double speed signal 24 is led to the LCD through the D / A converter 5 as in the first embodiment. However, in this embodiment, since the RGB arrays of the respective scanning line signals are all the same, the two-dimensional R of each pixel of the LCD is written when writing to the LCD.
It is necessary to adjust the write timing for each scan line by one pixel before and after each pixel so as to match the GB arrangement.

As described above, in this embodiment, since the scan conversion uses line interpolation, the image quality is inferior to that of the first embodiment, but the scan conversion type image display device can be realized with a much smaller memory capacity. Further, even for a conventional scan converter that performs processing with a Y / C signal using the same line interpolation, scan conversion can be performed with a smaller memory capacity for the same reason. [Embodiment 3] In this embodiment, the output video signal from the CCD is L
This is an application example in the case of scan conversion display on a CD, and FIG. 6 shows a block diagram of the camera unit. CCD here
Reference numeral 31 is a 4-wire output system in which four complementary colors of W, Ye, Cy, and G are orthogonally arranged, and the W, Ye, Cy, and G signal outputs are transmitted through an amplifier 32 to a matrix 33 in Y, G, R, and B Converted to a signal, then NTSC encoder 34 NT
Converted to SC Y / C signal. Generally, in a video camera or the like, it is necessary to display the signal from the CCD through the monitor on the finder or the like, but in this embodiment, the scan conversion display is performed. That is, the RGB signal before entering the encoder 34 is taken out, the RGB point sequential sampling is performed by the multiplexer 2 as in the first embodiment, and the signal is sent to the subsequent step as in the first embodiment.

This makes it possible to omit the RGB decoder as shown in FIG. 1 when scan-converting and displaying the video signal from the CCD. However, NTS
The output signal (Y / C) from the C encoder 34 is used for another purpose such as recording.

By the way, although an LCD is used as a display device in the above embodiments, the present invention is not limited to this, and any display device having an RGB mosaic structure such as a plasma display or an LED display can be used. Applicable. Further, the pixel array is also a diagonal mosaic array in the present embodiment, but is not limited to this, and is applicable to any array having a mosaic structure such as an RGB delta array and an RGB stripe array. It is possible.

[0028]

As described above, according to the present invention, a display device having a structure in which display elements corresponding to a plurality of colors are arranged in a mosaic is related to display such as scan conversion with a smaller circuit scale. Signal processing becomes possible,
As a result, a video display device with a simpler circuit configuration and lower cost can be realized.

[Brief description of drawings]

FIG. 1 is a system configuration block diagram of a first embodiment of a scan conversion type image display device embodying the present invention.

FIG. 2 is an explanatory diagram of signal processing of FIG.

FIG. 3 is a timing chart of memory reading and display device writing.

FIG. 4 is a system configuration block diagram of a second embodiment of a scan conversion type image display device embodying the present invention.

FIG. 5 is an explanatory diagram of signal processing of FIG.

FIG. 6 is a system configuration block diagram of a third embodiment of a scan conversion type image display device embodying the present invention.

FIG. 7 is a system configuration block diagram of a conventional scan conversion type image display device.

[Explanation of symbols]

 1 RGB Decoder 2 Multiplexer 3 A / D Converter 4 Frame Memory 5 D / A Converter 6 Amplifier 7 LCD 8 Timing Controller 31 CCD 32 Amplifier 33 Matrix Circuit 34 NTSC Encoder 41 Line Memory 42 Register 43 Arithmetic Unit 44 Multiplexer 90 LCD 91 , 92 A / D converter 93 Sync separator 94, 95 Frame memory 96 Timing controller 97, 98 D / A converter 99 Double speed RGB decoder

Claims (11)

[Claims] 1. A forming device for forming a dot-sequential color signal in which each of the plurality of color signals is arranged in a time-series in a dot-sequential manner, and a display element corresponding to the plurality of colors to which the dot-sequential color signal is sent. And a display device having a mosaic-arranged structure. 2. The arrangement of the plurality of color display elements in the scanning line direction of the mosaic structure of the display device and the arrangement of the plurality of color signals of the dot-sequential color signal are equal to each other. The image display device described. 3. The forming means has a storage means for storing the plurality of color signals, and the plurality of color signals of the signals written in the storage means before the plurality of color signals are written in the storage means. 3. The image display device according to claim 2, wherein the arrangement is equal to the arrangement of the plurality of color display elements in the mosaic structure of the display device. 4. A two-dimensional plurality of signals stored in the storage means or read signals from the storage means when the plurality of color signals are written in or read from the storage means. 4. The image display device according to claim 3, wherein the color arrangement is equal to the two-dimensional arrangement of the plurality of color display elements in the mosaic structure of the display device. 5. The video display device according to claim 3, wherein a writing speed to the storage means and a reading speed from the storage means are different from each other. 6. The image display device according to claim 5, wherein the reading speed is twice the writing speed. 7. The forming means samples each of the plurality of color signals dot-sequentially to form the dot-sequential signal before being written in the storage means, and at least the dot-sequential sampling of the plurality of color signals is performed. 7. The image display device according to claim 3, wherein the writing and the writing to the storage unit are performed in synchronization with each other. 8. The method according to claim 3, wherein at least the reading of the storage means and the driving of the display device are controlled by a timing control system which is synchronized with each other or the same timing control system. The video display device according to claim 1. 9. The read timing from the storage means and the write timing to each display element of the display device are shifted corresponding to the delay amount of the signal from the storage means to the display device. Claim 3 ~
The video display device according to claim 8. 10. The forming means forms each of the dot-sequential signals by sampling each of the plurality of color signals generated in a process of encoding a signal extracted from the image pickup device, in a dot-sequential manner. The image display device according to any one of claims 1 to 9. 11. The image display device according to claim 1, wherein the display device uses liquid crystal.