JPH03295332A - Serial interface system - Google Patents

Abstract

PURPOSE:To realize a bi-directional serial interface through simple device configuration, and to lighten the burden of processing by providing the devices of both sides respectively with a parallel/serial converter, a serial/parallel converter, and a control means. CONSTITUTION:Data transfer clock generating means 11, 14a, the parallel/serial converters 14b, 24e, the serial/parallel converters 14c, 24d, and the control means 11, 21 are provided. Then, serial data outputted from the first parallel/serial converter 14b is inputted to the second serial/parallel converter 24d, and the serial data outputted from the second parallel/serial converter 24e is inputted to the first serial/parallel converter 14c. Thus, the bi-directional serial interface can be realized through the simple device configuration, and by executing the input/output of the data at a fixed interval of time, the burden of the processing can be lightened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a serial interface method used for bidirectional data transmission between two digital processing devices.

[Prior Art] For example, in a computer system such as a control device using a microcomputer, there are two types of methods for mutually transmitting data between two digital processing devices: a synchronous transmission method and an asynchronous transmission method. be.

The synchronous transmission method is a method in which a common transfer clock is used between two digital processing devices, and a handshake control line is used to confirm which device will send data.

In addition, in the asynchronous transmission method, a start bit and a stop bit are added before and after the data to be transmitted, and data is exchanged in units of one character data.Basically, data is transmitted in one direction. When data is transmitted bidirectionally, two sets of device configurations are required.

[Problems to be Solved by the Invention] However, these conventional methods require a semiconductor integrated device dedicated to data transmission, which is costly, and requires processing to program the semiconductor device dedicated to data transmission. This results in the inconvenience of being burdened by

Therefore, if we try to reduce device costs without using such semiconductor devices dedicated to data transmission, the data transmitting side must closely monitor the operation timing of the receiving side. On the receiving side, it is necessary to monitor the data input timing so that the received data is not missed, resulting in the inconvenience that the processing load for this becomes extremely large.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a serial interface method that can realize bidirectional data transmission with a simple device configuration and can significantly reduce the processing load.

[Means for Solving the Problems] The present invention includes a data transfer clock generating means that generates a data transfer clock, and a first converter that converts stored parallel data into serial data in synchronization with the data transfer clock and outputs the serial data. a first serial/parallel converter that receives serial data output from the primary device in synchronization with a data transfer clock;
A primary side device +J is provided with a first control means that sends output data to the first parallel/serial converter at a predetermined period and reads input data from the first serial/parallel converter, and is synchronized with the data transfer clock. A second serial/parallel converter inputs the serial data output from the first parallel/serial converter, and converts the stored parallel data into serial data in synchronization with the transfer clock and outputs the serial data. 2nd parallel/
A secondary device is provided with a serial converter and a second control means for setting output data to a second parallel/serial converter at a predetermined period and reading input data from the second serial/parallel converter. The serial data output from the second parallel/serial converter is input to the first serial/parallel converter. Further, while a synchronization signal consisting of a predetermined bit pattern is added to the beginning of the output data of the first and second parallel/serial converters, the primary side device and the secondary side device When the synchronizing signal added to the beginning of the input data of the serial/parallel converter is detected, data input to the first and second serial/parallel converters is started.

[Operation L7] Therefore, a bidirectional serial interface can be realized with a simple device configuration, and since data is input and output at regular time intervals, the processing load is reduced. Also, by adding a synchronization signal to the beginning of the transmitted data,
Since the synchronization signal is used as a trigger for data input, synchronization for data transmission can be easily achieved.

[Example 1] Hereinafter, an example of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a digital processing system according to an embodiment of the invention.

This digital processing system is composed of a digital processing device 1 that performs a main operation and a digital processing device 2 that performs a slave operation.

Digital processing device! 1, a CPU (central processing unit) 11 controls the operation of the digital processing device 1, and a ROM (read only memory) 12 includes:
RAM (Random Access Memory)1
3 constitutes the work area of the CPU II.

The interface device 14 is connected to this digital processing device M1.
The other elements 15 are used to exchange data between the digital processing apparatus 1 and the digital processing apparatus 1. Note that this other element 15 is as follows.

Since it is not directly related to the present invention, detailed explanation thereof will be omitted.

These CPU II, ROM 12, RAM 13, interface device 14, and other devices w15 are interconnected by an internal bus 16, and data exchange between these elements is performed via this internal bus 16. ing.

In the digital processing device 2, the CPU 21 controls the operation of the digital processing device 2, and the ROM 2
2 stores a processing program executed by the CPU 21 and various data necessary for executing the processing program, and a RAM 23 constitutes a work area of the CPU 21.

The interface device 24 is connected to this digital processing device 2.
The other elements 25 are used to exchange data between the digital processing apparatus 2 and the digital processing apparatus 2. Note that this other element 25 is not directly related to the present invention, so a detailed explanation thereof will be omitted.

These CPU21, ROM22, RAM23. Interface device 24. The other devices M25 are interconnected by an internal bus 26, and data exchange between these elements is performed via this internal bus 26.

In the interface device 14, the frequency dividing circuit I4a divides the frequency of the transfer clock signal SP output from the CPU11, and its output signal is the timer interrupt signal T.
I is added to the interrupt signal input terminal of CPU II. Note that the frequency dividing ratio of the frequency dividing circuit 14a is 5. For example, when the period of the transfer clock signal SP is about 1 microsecond,
The period of the timer interrupt signal TI is set to be approximately 5° milliseconds.

Further, the transfer clock signal SP is applied to one input terminal of the parallel/serial converter 14b, serial/parallel converter 14c, synchronization signal detection section 14d, and AND circuit 14e of the interface device i[14, and Processing device 2 interface group! 24
has been added to.

The parallel/serial converter 14b is set with data to be output from the CPU 1i to the digital processing device 2 via the internal bus 16, and is configured to receive a shift clock signal S.
In synchronization with P, the stored data is sequentially 1 from the first bit.
Output bit by bit. This parallel/serial converter 1
The data output from 4b is transmitted data 50,
It is added to the interface device 24 of the digital processing device 2.

Here, the interface device 1 of the digital processing device 1
4 to the interface device 24 of the digital processing device 2
As shown in FIG. 2, the transmission data SD output to the
It has a format in which a synchronization signal 5ync consisting of data ``0'' of the ``] bit is added to the beginning of the data of the bit ``0''. Further, when there is no signal, the transmission data SD and the reception data RD are clamped to data "1".

The synchronization signal detection unit 14d detects the synchronization signal 5ync added to the beginning of the received data RD. When the synchronization signal 5ync is detected, the synchronization signal detection unit 14d outputs the enable signal EA for a period corresponding to eight cycles of the transfer clock signal SP. Raise to logic H level. This enable signal EA is applied to the other input terminal of the AND circuit 14e.

The AND circuit 14e is operable while the enable signal EA is raised to the logic H level, and uses the transfer clock signal SP applied at that time as the transfer clock signal SPa to the serial/parallel converter 14c.
Output to.

The serial/parallel converter 14c inputs the received data RD in synchronization with the transfer clock signal SPa, and its output port is connected to the internal bus 16.

In the interface device 24, the transfer clock signal SP is applied to the synchronization signal detection section 24a, one input terminal of the AND circuit 24b, and one input terminal of the AND circuit 24c.

The synchronization signal detection unit 24a detects the synchronization signal 5ync added to the beginning of the transmission data SD. When the synchronization signal 5ync is detected, the synchronization signal detection unit 24a outputs the enable signal EB for a period corresponding to 8 cycles of the transfer clock signal SP. Then, after a predetermined time TA has elapsed, the enable signal EC is raised to a logic H level for a period corresponding to nine cycles of the transfer clock signal SP. This enable signal EB is applied to the other input terminal of the AND circuit 24b and the interrupt signal input terminal INT of the CPU 21, and the enable signal EC is applied to the other input terminal of the AND circuit 24c.

The AND circuit 24b is operable while the enable signal EB is raised to the logic H level, and the serial/parallel converter 24d uses the transfer clock signal SP applied at that time as the transfer clock signal SPb.
Output to.

Further, the AND circuit 24c is in an operable state while the enable signal EC is raised to the logic H level, and uses the transfer clock signal SP applied at that time as the transfer clock signal SPc to the parallel/serial converter 24e. Output to.

The serial/parallel converter 24d receives the transmission data SD in synchronization with the transfer clock signal SPb, and its output port is connected to the internal bus 26.

The parallel/serial converter 24e receives data output from the CPU 21 to the digital processing device 1 via the internal bus 26, and receives the shift clock signal S.
In synchronization with Pc, the stored data is sequentially output one bit at a time starting from the first bit. The data output from the parallel/serial converter 24e is applied to the interface device 14 of the digital processing device 1 as received data RD.

Now, the CPU II enters the timer interrupt execution state due to the retiming of the timer interrupt signal T applied to the interrupt signal input terminal INT, and at that time, CP T,,'
FIG. 3 shows an example of the processing executed by I1.

In the timer interrupt execution state, the CPU II first reads the data stored in the serial/parallel converter 14c and copies it to a predetermined storage area of the RAM 13 (processing 10).
1).

Next, 1 byte of data to be output to the digital processing device 2 stored in a predetermined storage area of the R, A M 13 is read out, and a synchronization signal 5 sync consisting of 1 bit of data "0" is placed at the beginning of the 1 byte data. is added to the parallel/serial converter +4b (processing 10
2).

Here, the CPU II executes a series of processes in synchronization with the cycle of the timer interrupt signal TI, and outputs the output to the digital processing device 2. 113 in a predetermined storage area.

In addition, received data R stored in a predetermined area of the RAM 13
The contents of D are referenced when executing the series of processes described above and are incorporated into the internal processing of the digital processing device 1.

FIG. 4 shows an example of interrupt processing executed by the CPU 21 at the falling timing of the enable signal EC.

When the enable signal EC applied to the interrupt signal input terminal INT falls, the CPU 2 reads the data stored in the serial/parallel converter 24d and stores it in the RAM 23.
(processing 201).

Here, like the CPU 11, the CPU 21 executes a series of processes at the cycle of the timer interrupt signal TI, and
The contents of the transmission data SD stored in the predetermined area of 23 are as follows:
It is referenced when executing this series of processes.

Further, the data to be output to the digital processing device 1 is formed by the series of processing, and is stored in the parallel/serial converter 24e with the synchronization signal 5ync added to the beginning.

With the above configuration, when the timer interrupt signal TI rises, as described above, the CPU II reads the data stored in the serial/parallel converter 14c, and then sets the transmission data SD in the parallel/serial converter 14b. do.

As a result, as shown in FIGS. 5(a) to 5(k), the parallel/serial converter 14b sends out the transmission data SD in synchronization with the transfer clock signal SP, and the interface device 24 detects the synchronization signal. Part 24a and serial/
It is added to parallel converter 24d.

When the synchronization signal 5sync at the beginning of this transmission data SD is detected by the synchronization signal detection section 24a, the synchronization signal detection section 24a
raises the enable signal EB.

As a result, the transfer clock signal SPb is applied to the serial/parallel converter 24d, and the transmission data SD is stored in the serial/parallel converter 24d.

Further, the synchronization signal detection unit 24a raises the enable signal EC after a predetermined time TA has elapsed since the enable signal EB has been brought down.

As a result, the transfer clock signal SPc is applied to the parallel/serial converter 24e, and the received data RD stored in the parallel/serial converter 24e is outputted in synchronization with the transfer clock signal SPc. It is added to the serial/parallel converter 14c and the synchronization signal detection section 14d.

When the synchronization signal 5ync at the beginning of this received data RD is detected by the synchronization signal detection section 14d, the synchronization signal detection section 14d
raises the enable signal EA.

As a result, the transfer clock signal SPa is applied to the serial/parallel converter 14c, and the received data RD is stored in the serial/parallel converter 14c.

In this way, the frequency divider circuit 14. When the timer interrupt signal TI is output from the interface device 14, the transmission data SD stored in the parallel/serial converter 14b of the interface device 14 is transmitted to the serial/serial converter 14b of the interface device 24 with the synchronization signal 5ync removed. parallel converter 24
The received data RD stored in the parallel/serial converter 24e of the interface device 24 is transferred to the serial/parallel converter 1 of the interface device 14 with the synchronization signal 5ync removed.
4c.

In addition, as described above, the CPU of the digital processing device l
I and the CPU 21 of the digital processing device 2 each execute their internal processing in units of one period of the timer interrupt signal TI, and the CPU Ull is configured to perform the data set for the parallel/serial converter 14b and the serial /
While reading data from the parallel converter 14c, the CPU 21 reads the data from the serial/parallel converter 24c.
Since data is read from d and set to the parallel/serial converter 24e, CPoll of digital processing device 1 and CPoll of digital processing device 2
The PUs 21 can appropriately exchange data.

In this way, bidirectional data transmission can be carried out using interface device 14 and interface device 24.

As described above, in this embodiment, two parallel/serial converters 14b, 24e and two serial/parallel converters 14c, 24d constitute the main part of the interface device @14.24. Therefore, the cost of the interface device 14.24 can be significantly reduced.

In addition, the CPL'l of each digital processing bag W1, 2
1, 21 is the period of the timer interrupt signal TI output from the frequency dividing circuit 14a, and since it is sufficient to exchange and receive data from the other device, the time limit is gentle, and other CP
The degree of freedom in processing Ull and 21 is also expanded.

By the way, in the embodiment described above, the transmission data when there is no signal is clamped to the data "1", and the 1-bit data "0" is added as a synchronization signal to the beginning of the transmission data.
", but the clamping mode when there is no signal and the bit pattern of the synchronization signal are not limited to this. Further, the synchronization signal can also be generated and added by a data generation circuit that generates a specific bit pattern.

[Effects of the Invention] As explained above, according to the present invention, a bidirectional serial interface can be realized with a simple device configuration, and data is input and output at fixed time intervals.
The processing burden is significantly reduced. Further, since a synchronization signal is added to the beginning of the transmission data and the synchronization signal is used as a trigger for data input operation, it is possible to easily synchronize data transmission.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a digital processing system according to an embodiment of the present invention, FIG. 2 is a schematic diagram illustrating the format of transmission data, and FIG. 3 is a flowchart showing an example of processing by the CPU of the primary side device. Figure 4 shows the CP of the secondary side device.
FIG. 5 is a flowchart showing an example of the processing of U. FIG. 5 is an operation waveform diagram for explaining the operation of the apparatus shown in FIG. 14.24...Interface device, 14a...
Branch circuit, 14b, 24e...Parallel/serial converter, 14c, 24d...Serial/parallel converter, 14d, 24a...Synchronization signal detection section, 14e,
24b, 24c...AND circuit.

Claims (2)

[Claims] (1) a data transfer clock generating means for generating a data transfer clock; a first parallel/serial converter for converting stored parallel data into serial data and outputting the serial data in synchronization with the data transfer clock; a first serial/parallel converter that inputs serial data output from a secondary device in synchronization with a data transfer clock; 1st serial/
A first control means for reading input data from the parallel converter is provided in the primary side device, and a second control means for inputting serial data output from the first parallel/serial converter in synchronization with the data transfer clock. a serial/parallel converter; a second parallel/serial converter that converts the stored parallel data into serial data in synchronization with the transfer clock and outputs the serial data; A second control means is provided in the secondary side device for setting output data in the converter and reading input data from the second serial/parallel converter, and the second control means sets the output data to the serial converter and reads the input data from the second serial/parallel converter. is input to the first serial/parallel converter. (2) A synchronization signal consisting of a predetermined bit pattern is added to the beginning of the data output from the first and second parallel/serial converters, while the primary side device and the secondary side device When the synchronization signal added to the beginning of the input data of the first and second serial/parallel converters is detected, the first and second serial/parallel converters
2. The serial interface system according to claim 1, further comprising the step of starting data input to a parallel converter.