JPH03295271A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To effectively prevent a semiconductor memory device from malfunctioning by a method wherein an N-type semiconductor substrate is provided, a well onto which a potential lower than an outer input potential is applied is provided inside the semiconductor substrate, and a first diffusion layer to which an outer input potential is applied and a second diffusion layer to which a voltage of Vref is applied are formed in the well. CONSTITUTION:A semiconductor memory device is composed of the following: a P well 16 which is formed on an N-type semiconductor substrate 11 and to which the substrate potential (VBB) of the semiconductor substrate 11 is applied through the intermediary of a third terminal 17 and a P<+> diffusion layer 18; a first N<+> diffusion layer 12 which is formed inside the P well 16 and to which a voltage of VIN is applied through the intermediary of a second terminal 15; and a second N<+> diffusion layer 13 to which a voltage of Vref is applied. A potential applied to a P well is changed from a conventional VSS to a VBB, whereby minority carriers are prevented from moving to the P well 16 even if VIN is given a negative potential as far as VIN is larger than VBB, so that a semiconductor memory device is effectively prevented from malfunctioning due to the reduction of Vref caused by the inflow of minority carriers.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) The present invention relates to a semiconductor memory device, and particularly to an element structure of an input circuit.

(Prior art) External input voltage (hereinafter referred to as VI
It is called N. ) with a reference potential (hereinafter referred to as V t e I) and determines whether it is “old GH”, “Low” or “1”.
In order to detect "0", amplify the detected signal, and convert it to a MOS level signal inside the device, an address sofa circuit is used in the case of an address pin, and a data inverter is used in the case of a data bin. There is an input circuit called the sofa circuit.

FIG. 4 is an equivalent circuit diagram of the address buffer circuit.

External input control signals (RAS, CA in DRAM)
internal control signals φ, φ2, φ generated by
3, the address is changed at the timing of this internal control signal. Then, "old gh" or "Low" is detected depending on whether the potential of VIN is higher than Vll.

Here■71. 7. refers to a predetermined potential that is generated inside a semiconductor memory device and serves as a reference for the circuit operation of the semiconductor memory device, and usually has a positive potential. ．．
Preventing fluctuations in is a problem that requires special attention in terms of circuit operation.

By the way, in a semiconductor memory device equipped with an input circuit, a negative potential is applied to VIN (for example, when VIN is lowered by -2
, up to about 0 [V]) is conducted to test the operating characteristics of semiconductor memory devices, and the following can be considered in this test. This will be explained below based on FIG.

FIG. 2 is a sectional view of a semiconductor memory device constructed from a conventional N-type semiconductor substrate.

The semiconductor memory device shown in FIG. 2 includes an N-type semiconductor substrate 21 and a ground potential (hereinafter referred to as VSS
It is called. ) is formed in the p-well 26 to which VI
It is formed in the first n+ diffusion layer 22 to which N is applied and in the p well 26, and is connected to the first n+ diffusion layer 22 to which N is applied, and the voltage is
, , is applied to the second n+ diffusion layer 23.

In this way, the first n+ diffusion layer 22 to which VAN is applied
A second n+ diffusion layer 23 to which V r e l is applied is surrounded in the same p well 26, which is connected to V55. In this case, the minority carriers generated when a negative potential is applied to vlN are shown in Figure 3(a).
As shown in the potential energy diagram, some of the carriers flow to the N-type semiconductor substrate 21, but the minority carriers that have no place to go flow to the second n+ diffusion layer 23 in the same p-well, increasing V r e l. There is a risk of deterioration. This v2. , is a reference potential for circuit operation, and if this potential fluctuates, the semiconductor memory device will malfunction.

(Problems to be Solved by the Invention) In semiconductor memory devices constructed from N-type semiconductor substrates as described above, malfunctions of the semiconductor memory devices caused by fluctuations in the reference potential due to the influx of minority carriers have become a major problem. The present invention eliminates the drawbacks of the prior art and provides a highly reliable semiconductor memory device.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention includes an N-type semiconductor substrate, a semiconductor substrate formed within the semiconductor substrate, and a voltage lower than an external input voltage applied to the semiconductor substrate. a first diffusion layer formed in this well to which an external input potential is applied, and Vl formed in the same well and generated inside the semiconductor memory device. The present invention provides a semiconductor memory device having a second diffusion layer to which a voltage is applied.

(Function) In this structure, the first diffusion layer and the second diffusion layer are surrounded by a well 1, and this well has a potential lower than VIN (that is, its absolute value is VIN).
It becomes larger than IN. ) is applied. For this reason V
Minority carriers generated when a negative potential is applied to IN do not move to the well with a high energy potential and therefore do not move to the second diffusion layer, so V
There is no variation in l, .

(Example) Examples of the present invention will be described below. FIG. 1 shows a semiconductor memory device in this embodiment.

That is, the N-type semiconductor substrate 11 and this semiconductor substrate 11
A third terminal 17, a p diffusion layer 18
The substrate potential (hereinafter referred to as VBB) of the semiconductor substrate is applied via the voltage.

), a first n'' diffusion layer 12 formed in this p well 16 and to which VIN is applied via the first terminal 14, and and a second n+ diffusion layer 13 to which 1.. is applied via the second terminal 15.

In such a configuration, as shown in the potential energy diagram of Fig. 3(b), by changing the potential applied to the p-well from the conventional VSS to VBB (for example, about -3.0[V]). , VBB even if a negative potential is applied to VIN.
Unless (i.e., l VINI > l
(unless VBBI), minority carriers are p-well 16
(Therefore, the second n゛ diffusion layer 13
Therefore, the potential of V v e L is not lowered.

Therefore, it is possible to effectively prevent malfunctions in the semiconductor memory device caused by a decrease in V +el due to the inflow of minority carriers.

[Effects of the Invention] As described above, according to the present invention, it is possible to effectively prevent malfunctions of a semiconductor memory device caused by fluctuations in the reference potential caused by minority carriers generated when a negative potential is applied to an external input potential, It becomes possible to improve the reliability of the semiconductor memory device.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a semiconductor memory device constructed from a conventional N-type semiconductor substrate, FIG. 3 is a potential energy diagram, and FIG. FIG. 3 is an equivalent circuit diagram of an address buffer circuit. 11.21...N-type semiconductor substrate, 12.22.
...First n+ diffusion layer, 13.23...
Second n+ diffusion layer, 14.24...First terminal, 15.25...Second terminal, 1B, 2f3...P well, 17.27・・・・・・Third terminal. 18.28...p"diffusion layer. ((1) (-4) 312 years old)

Claims (1)

[Scope of Claims] An N-type semiconductor substrate, a well formed within this semiconductor substrate to which a potential lower than an external input potential is applied, and a well formed within this well to which the external input potential is applied. A semiconductor memory device comprising: a first diffusion layer formed in the well; and a second diffusion layer formed in the well and to which a reference potential is applied.