JPH07120750B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor memory device, and more particularly to an element structure of an input circuit.

(Prior Art) An external input voltage (hereinafter, referred to as V _IN ) that is TTL level data is compared with a reference potential (hereinafter, referred to as Vref), and “High”, “Low” or “1”, In order to detect "0" and amplify the detected signal to convert it to the MOS level signal inside the device, the input is called the address buffer circuit for the address pin and the data-in buffer circuit for the data pin. There is a circuit.

FIG. 4 is an equivalent circuit diagram of the address buffer circuit.
Addresses of internal control signals φ ₁ , φ ₂ , φ ₃ generated by an external input control signal (RAS, CAS, etc. in DRAM) are latched at the timing of this internal control signal. Then, depending on whether or not V _IN is higher than Vref, “H
Detects "igh" or "Low".

Here, Vref is generated inside the semiconductor memory device,
It refers to a predetermined potential that serves as a reference for the circuit operation of the semiconductor memory device, and usually has a positive potential. However, preventing such fluctuations in Vref is a problem that must be paid special attention to in the circuit operation.

Meanwhile, in a semiconductor memory device having an input circuit applies a negative potential to V _IN (e.g., the V _IN ~-2.0
Inspect the operating characteristics of the semiconductor memory device (up to about [V])
The V _IL minus test has been conducted, and the following may be considered in this test. Hereinafter, description will be given with reference to FIG. FIG. 2 is a sectional view of a semiconductor memory device composed of a conventional N-type semiconductor substrate.

The semiconductor memory device shown in FIG. 2 includes an N-type semiconductor substrate 21,
The third terminal 27, which is formed in the semiconductor substrate 21,
Ground potential (hereinafter referred to as V _SS ) via the p ⁺ diffusion layer 28.
Is applied to the p-well 26 and the first n-well formed in the p-well 26 and to which V _IN is applied via the first terminal 24.
^{The +} diffusion layer 22 and the second n ⁺ diffusion layer 23 formed in the p well 26 and to which Vref is applied via the second terminal 25.

Thus, the first n ⁺ diffusion layer 22 to which V _IN is applied and V ref
The second n ⁺ diffusion layer 23 to which is applied is surrounded by the same p well 26, and the well is connected to V _SS . In this case, some minority carriers generated when a negative potential is applied to V _IN flow to the N-type semiconductor substrate 21 as shown in the potential energy diagram of FIG. 3 (a),
Minority carriers that have lost their place may flow into the second n ⁺ diffusion layer 23 in the same p-well and reduce Vref. Since this Vref is a reference potential for circuit operation, fluctuations in this potential result in malfunction of the semiconductor memory device.

(Problems to be Solved by the Invention) In the semiconductor memory device thus configured from the N-type semiconductor substrate, malfunction of the semiconductor memory device caused by fluctuation of the reference potential due to inflow of minority carriers has been a serious problem. The present invention eliminates the drawbacks of the prior art and provides a highly reliable semiconductor memory device.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, in the present invention, an external input potential is applied to the drain, and a gate is controlled by a first control signal. Type MOS transistor and this first
A first capacitive element connected to the source of the N-type MOS transistor, a second N-type MOS transistor in which a reference potential is applied to the drain, and a gate is controlled by a first control signal; The second capacitance element connected to the source of the N-type MOS transistor and the potential that is taken in by the first control signal and remains on the first and second capacitance elements are
Further, in a semiconductor memory device having an input protection circuit composed of comparison / latch means for latching the comparison result while making a comparison based on the second and third control signals, the semiconductor memory device has an N-type semiconductor region. And a lower limit of the potential of an input signal that is normally input from the outside as a logic signal through the P-type well potential setting diffusion layer when formed in the N-type semiconductor region of the semiconductor substrate. A P-type well to which a lower potential is applied,
It is formed in this well, the input signal is applied,
N used as the drain of the first MOS transistor
-Type first diffusion layer and a well structure formed in the well and having an N-type second diffusion layer formed in the well and applied with a reference potential and used as the drain of the second MOS transistor. A semiconductor memory device is provided.

(Operation) In the structure as described above, the first diffusion layer and the second diffusion layer are surrounded by the well, and this well has a potential lower than V _IN (that is, its absolute value is V Is greater than _IN ). Therefore, the minority carriers generated when a negative potential is applied to V _IN do not move to the well with high energy potential, and therefore do not move to the second diffusion layer, and thus do not change Vref. .

(Examples) Examples of the present invention will be described below. FIG. 1 shows a semiconductor memory device in this embodiment.

That is, the substrate potential of the semiconductor substrate (hereinafter referred to as V _BB ) is applied through the N-type semiconductor substrate 11 and the third terminal 17 formed in the semiconductor substrate 11 and the p ⁺ diffusion layer 18. And the p-well 16 formed in the p-well 16.
The first n ⁺ diffusion layer 1 to which V _IN is applied via the first terminal 14
2 and the second terminal 1 formed in the p-well 16
And a second n ⁺ diffusion layer 13 to which Vref is applied via 5. In such a configuration, as shown in the potential energy diagram of FIG. 3B, the potential applied to the p-well is changed from the conventional V _SS to V _BB (for example, −3.
By setting it to 0 [V]), even if a negative potential is applied to V _IN , V
Minority carriers do not move to the p-well 16 unless they are lower than _BB (that is, | V _IN |> | V _BB |), and hence to the second n ⁺ diffusion layer 13. Since it is not present, the potential of Vref is not reduced.

Therefore, it is possible to effectively prevent the malfunction of the semiconductor memory device due to the decrease of Vref due to the inflow of minority carriers.

[Effects of the Invention] As described above, according to the present invention, it is possible to effectively prevent the malfunction of the semiconductor memory device due to the fluctuation of the reference potential by the minority carriers generated when a negative potential is applied to the external input potential, The reliability of the semiconductor memory device can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a sectional view of a semiconductor memory device composed of a conventional N-type semiconductor substrate, FIG. 3 is a potential energy diagram, and FIG. It is an equivalent circuit diagram of an address buffer circuit. 11,21 …… N-type semiconductor substrate, 12,22 …… First n ⁺ diffusion layer,
13,23 …… Second n ⁺ diffusion layer, 14,24 …… First terminal, 15,2
5 …… second terminal, 16,26 …… p well, 17,27 …… third
Terminal, 18, 28 …… p ⁺ diffusion layer.

Claims (1)

[Claims] 1. A first N-type MOS having a drain to which an external input potential is applied and a gate controlled by a first control signal.
A transistor, a first capacitive element connected to the source of the first N-type MOS transistor, and a second N-type MOS whose reference potential is applied to the drain and whose gate is controlled by the first control signal. A transistor, a second capacitive element connected to the source of the second N-type MOS transistor, and the first and second transistors fetched by the first control signal.
In a semiconductor memory device having an input protection circuit configured by comparing / latching means for latching the comparison result while further comparing the potentials left on the capacitive element of the second control signal on the basis of the second and third control signals. The semiconductor memory device includes: a semiconductor substrate having an N-type semiconductor region; and a semiconductor substrate formed in the N-type semiconductor region of the semiconductor substrate, which receives a logic signal from the outside via a P-type well potential setting diffusion layer. A P-type well to which a potential lower than the lower limit of the potential of the input signal that is normally input during operation is applied, and the drain of the first MOS transistor formed in the well and to which the input signal is applied And a first N-type diffusion layer that is formed in the well, is applied with the reference potential, and is used as a drain of the second MOS transistor. The semiconductor memory device characterized by having a well structure composed of a second N-type diffusion layer.