JP3161378B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a threshold voltage variation detection and correction circuit composed of a CMOS transistor used for reading a signal stored and held in the semiconductor memory device.

[0002]

2. Description of the Related Art FIG. 11 is a block diagram showing an example of a configuration of a data read circuit of a conventional semiconductor memory device.
Referring to FIG. 11, an address buffer 801, an address transition detection circuit (hereinafter, referred to as an "ATD circuit") 802 for detecting a change in an address input, a latch pulse generator 803 for determining data latch timing, a data latch circuit 804, and a main cell It comprises a sense amplifier 806 for sensing data and an output buffer 805 for outputting data.

FIG. 12 is a timing chart for explaining the operation of the data read circuit shown in FIG.
FIG. 3 is a diagram showing signal waveforms of No. 1 to No. 1; Note that FIGS. 21 and 22 show enlarged waveform diagrams of the portion indicated by * 2 in FIG. As shown in FIG. 12, when an address is input, an address change is detected to generate an ATD pulse, and a latch pulse for determining a data fetch timing is generated from the signal.

On the other hand, from the input of an address, data of a main cell corresponding to the address is sensed by a sense amplifier 806. When this data is latched by Lo
, and the data is latched in the output buffer 805.
To output as data output.

FIG. 13 is a diagram showing a schematic configuration of a conventional sense amplifier 806. M101 and M102 are memory cells, and have a source connected to the ground, a drain connected to the bit line BL101, and a gate connected to the word lines WL101 and 102, respectively, during a read operation. R10
A reference cell 1 has a source connected to the ground and a drain connected to the bit line BL102, like the main cell, but has a constant voltage V102 applied to the gate so that a constant current flows. The bit lines are respectively connected to feedback NOR circuits F101 and F102, which are composed of Nch transistors N101 and N102 and inverters INV101 and INV102,
Control is performed so that the voltage applied to the drains of the memory cell and the reference cell becomes constant.

P101 and P102 are load transistors, which are Pch transistors, and whose gate and source are Nch transistors N10 of F101 and F102, respectively.
1, connected to the drain of N102 and the drain is connected to Vcc.

[0007] A101 is a sense amplifier, and F1
01, 102 Nch transistors N101, N102
Of the drain of the memory cell, and ON / OFF of the memory cell
Has been detected.

The operation of the sense amplifier shown in FIG. 13 will be described. The constant voltage V1 is applied to the gate of the reference cell.
02, since the feedback NOR circuit F102 is connected to the drain, a substantially constant current flows depending on the threshold voltage, the power supply voltage Vcc, and the temperature. The main cell has the same configuration, but a Vcc power supply voltage or a constant voltage V101 obtained by boosting the same is applied to the gate. The OFF cell has a high threshold voltage so that no current flows, and the ON cell has a low threshold voltage and a current flows.

The sense amplifier S. The input voltage to A101 depends on the current flowing through the cell. A low voltage is applied when a current flows, and a high voltage is applied when no current flows. By comparing this input voltage with the input voltage on the reference cell side, the sense amplifier S.D. At A101, ON / OFF determination is performed.

Although the operation of the sense amplifier is as described above, the bit line is actually very long, so that parasitic resistance and capacitance exist. A parasitic capacitance due to the PN junction also exists at the drain of the cell.

Therefore, when the power supply voltage Vcc decreases,
Also, at high temperatures, the determination speed of each node of the sense amplifier itself becomes slower. The speed also depends on the threshold voltage. When the threshold voltage of the Nch transistor increases, the speed of the feedback NOR circuit decreases, and the speed decreases. Similarly, Pc
Feedback threshold voltage of h transistor is also NOR
This is a factor that affects the performance of the circuit and the load transistor and slows down the speed.

FIG. 14 is a diagram showing an example of a circuit configuration of the ATD pulse generator circuit 802. The ATD pulse generator circuit 802 detects a change in the address and generates a one-shot pulse. The ATD pulse generator circuit 802 converts the address input signal and a signal obtained by delaying the address input signal by a delay circuit 111 connected to a plurality of inverters into two.
Input NOR circuit NOR111 and NAND circuit NAND
Input to 111. The output of the NOR circuit NOR111 passed through the inverter INV111 and the NAND circuit NA
The output of ND111 is connected to a two-input NAND circuit NAND11.
2 and the output thereof is passed through a delay circuit 112.

The pulse is generated by the second NAND circuit NAN.
The process is performed up to D112, and the delay circuits 111 and 112 adjust the pulse width. FIG. 15 shows the ATD shown in FIG.
FIG. 15 is a timing waveform diagram for explaining the operation of the pulse generator circuit, showing signal waveforms at each node in FIG. 14, where the address input waveform is ATDIN111;
The output of the delay circuit 111 is 111, the NOR circuit NOR11
1, the output of the NAND circuit NAND111 is 11
2, 113, ATD pulse waveform is ATDOUT111
It is.

FIG. 16, FIG. 17, and FIG. 18 show the data determination speed and AT by the sense amplifier circuit 806 described above.
FIG. 9 is a diagram illustrating a threshold voltage, a power supply voltage Vcc, and a temperature dependency of a data latch time depending on a D pulse generator circuit 802;

The dependence of the analog circuit such as the determination of the sense amplifier data on the analog circuit and the dependence on the digital circuit such as the data latch circuit are different as shown in FIG. 16, FIG. 17, and FIG. For this reason, there is a possibility that the data determination timing of the sense amplifier and the timing of latching the data are shifted from each other, causing a malfunction.

In order to eliminate the above problem, a threshold voltage detection correction circuit as shown in FIG. 19 has been proposed, for example, in Japanese Patent Application Laid-Open No. 58-100294. FIG. 16 shows a configuration of a differential type sense circuit in a dynamic memory proposed in the above publication.
N162 is an Nch transistor for sensing, and its drain is connected to complementary bit lines BL161 and BL162. A plurality of memory cells and one dummy cell are provided along the bit lines BL161 and BL162, respectively.

The memory cells and the dummy cells are MOS transistors M161 and D161 and a capacitor CS161.
CS162, the stored information is held in the form of electric charge stored in the capacitor. MOS capacitor CC16
1. CC162 is a transistor having only a gate and a drain, and serves as a capacitor. The Nch transistors N163, N164, N165 and N166 each serve as a switching.

FIG. 20 is a time chart for explaining the operation of the threshold voltage detection and correction circuit shown in FIG. VDD is applied to φ161 and φ163 until time t1.
Since voltages are applied to + V1 and VDD, the Nch transistors N161, N162, N163, and N164 are turned on, the bit lines BL161 and BL162 are precharged, and charges are stored in the capacitors CC161 and CC162. However, VDD is High level voltage, V
1 is a voltage higher than the threshold voltage of N163, N164, N165, N166, and VSS is a low level voltage.

Next, after t1, when φ161 is lowered to VSS, charges of the capacitors CC161 and CC162 are injected into the bit lines BL161 and BL162. Thereafter, when the signal φ162 is set to the VDD level, the word line WL16
1. The dummy word line WLD 161 is pulled up to the pull-up level and reaches an equilibrium state.

Thereafter, the ON / OFF state of the memory cell is determined by differential amplification comparing the output voltage of the main cell and the output voltage of the dummy cell.

In this circuit, by pulling up the word line, the Nch transistor N before differential amplification is performed.
161 and N162 are equalized, and sensing independent of the difference in threshold voltage becomes possible.

In this method, variation in threshold value is detected and corrected in two NMOS transistors for sensing in a sense amplifier, and sensing is performed without depending on variation in threshold voltage. However, it does not compensate for fluctuations in threshold voltage due to diffusion lots, seasonal fluctuations and the like.

[0023]

The above-described prior art has the following problems.

The first problem is that if the values of the threshold voltage, temperature, and power supply voltage Vcc fluctuate, a malfunction may occur.

The reason is that in the operation of the digital system (for example, a data latch circuit) and the operation of the analog system (for example, a sense amplifier circuit), as shown in FIGS.
This is because they have different compatibility with respect to the threshold voltage, temperature, Vcc, and the like. For this reason, when the threshold voltage or the like fluctuates, the rate of change of the operation speed differs between the data output determination time of the sense amplifier and the data fetch time, so that the operation margin is lost and a malfunction may occur. .

FIG. 21 is a diagram showing the waveform of the latch timing in the data read circuit of FIG. 11 during normal operation and FIG. 22 is a diagram showing the latch timing waveform in the case of malfunction (enlarged portion of * 2 in FIG. 12). In FIG. 21, the output data of the sense amplifier 806 is determined before the end edge of the latch pulse, and the latch has been performed normally. On the other hand, at the time of malfunction,
As shown in FIG. 22, the data determination of the sense amplifier 806 is after the end edge of the latch pulse, and it can be seen that the indeterminate sensing of the intermediate level is performed.

The second problem is that if an operation margin is provided to avoid the above-described malfunction, the speed cannot be satisfied.

The reason is that the operation speed depends on the sense amplifier data fetch by the latch. In order to secure an operation margin, the operation is reliably performed by delaying the end edge of the latch pulse. However, the speed may be reduced correspondingly, and the characteristics may not be satisfied.

Accordingly, the present invention has been made in view of the above-described problems, and has as its object to know the state of the threshold voltage, the power supply voltage Vcc, the operating state under worst conditions such as temperature, and the like. It is an object of the present invention to provide a semiconductor memory device having a threshold voltage detection / correction circuit which enables data to be taken in at a data taking timing corresponding to a state and operates at high speed and accurately.

[0030]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a transistor (hereinafter referred to as a transistor) having a substrate portion in a channel portion which is less dependent on threshold voltage due to diffusion than a normal transistor. The state of the threshold voltage is known by comparing the current flowing through a "non-doped transistor" and a normal Nch transistor, and the result is fed back to the ATD circuit to optimize the operation margin.

[Operation] To explain the operation of the present invention, the read operation timing is optimized by detecting the threshold voltage of the transistor in the peripheral circuit. Thereby, the operation margin can be optimized without unnecessarily reducing the speed.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating a configuration of a threshold voltage detection circuit according to an embodiment of the present invention. FIG.
Referring to FIG. 1, in the embodiment of the present invention, the non-doped transistor N
D11, a constant voltage V11 is input to the gate, the source is connected to the drain of the Nch transistor N12, and the drain is connected to the drain and gate of the Pch transistor P13. The Nch transistor N11 used for measuring the threshold voltage inputs a constant voltage V12 to the gate, connects the source to the drain of the Nch transistor N12, and connects the source to the drain of the Pch transistor P14, like the non-doped transistor ND11. are doing. The gate of the Nch transistor N12 is Vcc,
The source is connected to ground.

The Pch transistors P13 and P14 have the same size, the source is connected to the power supply voltage Vcc, the gate is commonly connected, and the drain of the transistor P13 and the source of the non-doped transistor are connected. Pch
The drain of the transistor P14 is an Nch transistor N
11 and the output O11.

As shown in FIG. 1, the threshold voltage detecting circuit includes a differential pair transistors ND11 and N11 whose sources are commonly connected and connected to a constant current source N12, and a current mirror constituting an active load of the differential pair. It is configured as a differential amplifier circuit composed of circuits P13 and P14. That is, the operation of this circuit is basically a differential amplifier circuit, the load transistors P13 and P14 are of the same size, the source is a common power supply voltage Vcc, and the gates are common. Transistors ND11 and N
An equivalent voltage is applied to the source of the channel transistor N11.

Since a constant voltage is applied to the gates of the transistors ND11 and N11, the currents are basically different from the threshold voltages and the voltages applied to the gates of the respective transistors.

However, since the sources of the transistors ND11 and N11 are connected in common and connected to the Nch transistor N12 functioning as a constant current, the total current flowing through the respective transistors ND11 and N11 is limited by the capability of the transistor N12. Will be done. For this reason, the current flowing through the transistors ND11 and N11 flows more when the current flows more, and the current stops flowing when the current does not flow, so that the difference between the currents flowing through the two transistors is amplified. Actually, in order to know the threshold voltage, the size of the reference transistor ND11 and the voltage applied to the gate are adjusted to determine the reference current.
Then, in order to know the level of the threshold voltage, it is compared whether the current of the transistor N11 is larger or smaller than the reference current.

When the threshold voltage is low, the transistor N
11, a large amount of current flows, and no current flows through the transistor ND11. Therefore, the transistor ND1
1 and the voltage applied to the load transistors P13 and P14 become High level,
14 turns off. As a result, the output goes to a low level.

Conversely, when the threshold voltage of the transistor N11 is high, no current flows through the transistor N11 and a large amount of current flows through the transistor ND11, so that the load transistor P14 is turned on and the output goes to a high level.

FIGS. 3 and 4 show an example of a circuit using the threshold voltage detecting circuit. FIG. 3 shows an AT according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of a D pulse generator. FIG.
FIG. 4 is a diagram illustrating an example of a configuration of delay circuits 31 and 32 in FIG. 3. The threshold voltage detection circuit shown in FIG. 1 determines whether the threshold voltage of the Nch transistor is high or low, and adjusts the width of the ATD pulse based on the output signal. The data determination speed of the sense amplifier output has a greater dependence on the threshold voltage than the end of the latch pulse for taking in data. For this reason, if the threshold voltage is set high, data is fetched before data is determined, resulting in an erroneous latch.

Therefore, when it is determined that the threshold voltage is high (the output of the threshold voltage detection circuit is high).
h) By increasing the number of inverter stages in the delay circuit of the ATD pulse generator, the width of the latch pulse is increased and the data fetching time is delayed, so that the reading operation can be performed accurately. On the other hand, when the threshold voltage is low, a delay circuit of the ATD pulse generator having a smaller number of inverter stages is used. If the data reading margin can be secured, the reading operation is performed without lowering the speed.

FIG. 2 is a diagram showing the threshold voltage dependence of the sense amplifier data determination speed and the data latch speed after the delay circuit is changed. By switching the latch circuit, a circuit with a small delay is selected in a region where the threshold voltage is low. In a region where the threshold voltage is high, a delay is added to reduce the speed, and the operation is changed so as to operate reliably. As a result, reliable operation can be guaranteed, and operation can be performed at an appropriate speed.

The threshold voltage detection and correction circuit according to the embodiment of the present invention is performed in a test mode in a wafer test or a sorting process. For this reason, it is possible to ship a sample whose speed and operation margin have been optimized. The selection of the delay circuit for optimizing the speed and the operation margin is performed by switching with a fuse cell as in the related art.

Since the read margin also depends on the temperature and the power supply voltage Vcc, the detection of this threshold voltage is performed on the power supply voltage VC in a direction in which there is no read margin.
It is preferable to carry out under conditions of high C and high temperature.

However, the dependence of the temperature, the power supply voltage Vcc, and the threshold voltage on the read operation differs depending on the circuit configuration, so that the worst condition must be evaluated by the circuit.

Next, another embodiment of the present invention will be described. FIG. 5 is a diagram illustrating a circuit configuration according to the second embodiment of this invention. The configuration shown in FIG. 5 is a threshold voltage detection correction circuit of a Pch transistor. Referring to FIG.
The configuration is almost the same as the configuration shown in FIG. 1 except for the polarity of the transistor.

Nch transistor N forming an active load
Since the gates of the transistors 51 and N52 are connected to the same potential and the source is also connected to the ground, the current flowing to the ground depends on the capability of the non-doped transistor ND51 and the Pch transistor P.
It is proportional to 52 capabilities. Non-doped transistor ND5
A constant voltage V51 is applied to the gate of No. 1 and the drain is
Connected to the source of transistor P51, and set the source to Nch
Connected to the gate and drain of transistor N51. On the other hand, a constant voltage 52 is applied to the gate of the Pch transistor P52 for detecting the threshold voltage, and the drain is connected to the source of the Pch transistor P51 as in the non-doped transistor, and the source is connected to the drain of the Nch transistor N52. are doing. Output O51 is Pc
Connected to the source of h transistor P52.

The operation of the embodiment of the present invention will be described. Since the gates and sources of the Nch transistors N51 and N52 have the same potential, the current flowing through each of them is ND5
1, proportional to the current flowing through P52. When the threshold voltage of the Pch transistor is low, a large amount of current flows through the Pch transistor P52, so that a current flows through the Nch transistor N52 and no current flows through the Nch transistor N51, so that the gate voltages of the transistors N51 and N52 increase. As a result, the output O11 is pulled low.

Conversely, when the threshold voltage of the Pch transistor P52 is high, more current flows through the Nch transistor N51, the gate voltages of the Nch transistors N51 and N52 decrease, and the output O11 outputs High.
As described above, the level of the threshold voltage of the Pch transistor is detected.

The correction method uses the circuits shown in FIGS. 3 and 4 as in the case of the Nch transistor. When the threshold value of the Pch transistor P52 is low, the speed is reduced and the operation margin is widened by using the delay circuit of FIG. On the other hand, when the threshold value of the Pch transistor P52 is high,
Since the operation margin is secured, the delay is not passed.
As a result, the speed and the operation margin can be optimized.

In the first and second embodiments, as a method of expanding the operation margin, as shown in FIG.
We are expanding the D pulse width. In order to extend the operation margin and perform accurate reading, the end edge of the latch pulse only needs to be delayed in time. Therefore, as a speed adjustment method, a delay circuit can be provided at a place where the end edge of the latch pulse is delayed without delaying the data output of the sense amplifier.

As an example of an application example of the present invention, there is a circuit configuration as shown in FIG. This is shown in FIG. 1 or FIG.
Of the constant voltage V11 applied to the non-doped transistor ND1 as a reference for the threshold voltage measurement in the circuit shown in FIG.
By preparing a plurality of threshold voltage detection circuits having different (V51), the state of the threshold voltage is finely detected, and the speed is finely adjusted. This output 20
By selecting a plurality of delay circuits from FIG. 6 as shown in FIG. 6, a more optimal latch speed can be adjusted as shown in FIG.

As a method for obtaining the same effect, there is a method as shown in FIGS. This corresponds to the threshold voltage detection circuit shown in FIG. 1 or FIG.
As shown in FIG. 10, the gate of the non-doped transistor ND1 serving as a reference for the threshold voltage measurement in 1) is
In this method, a plurality of voltages having different magnitudes are applied with a time difference. By selecting a plurality of delay circuits as shown in FIG. 6 from this output, a more appropriate latch speed can be adjusted as shown in FIG.

[0053]

As described above, according to the present invention, the following effects can be obtained.

A first effect of the present invention is that it is possible to detect a manufacturing variation such as a threshold voltage.

The reason for this is that in the present invention, the threshold voltage is detected based on the current flowing through the Nch and Pch transistors used in the peripheral circuit, based on the current flowing through the non-doped transistor with little manufacturing variation. It is.

A second effect of the present invention is that it is possible to operate with an appropriate operation margin.

The reason is that, in the present invention, the operation margin and speed are adjusted using the threshold voltage value detected by the above effect.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a graph showing a threshold voltage dependency of a read speed in one embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration of an ATD circuit according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a circuit configuration of a delay circuit of an ATD circuit according to an embodiment of the present invention.

FIG. 5 is a diagram showing a circuit configuration of a second embodiment of the present invention.

FIG. 6 is a diagram showing a circuit configuration of a delay circuit according to another embodiment of the present invention.

FIG. 7 is a graph showing the threshold voltage dependence of the read speed in the semiconductor memory device according to the example of the present invention.

FIG. 8 is a diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 9 is a diagram showing a configuration of a fourth exemplary embodiment of the present invention.

FIG. 10 is a diagram showing an example of a time chart of an input voltage in a fourth embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a read circuit of a conventional semiconductor memory device.

FIG. 12 is a time chart of main signals during a read operation of the conventional circuit shown in FIG. 11;

FIG. 13 is a diagram showing a configuration of a conventional sense amplifier circuit.

FIG. 14 is a diagram showing a configuration of a conventional ATD pulse generator circuit.

FIG. 15 is a time chart showing an operation of a conventional ATD pulse generator circuit.

FIG. 16 is a graph of threshold voltage dependence of read speed.

FIG. 17 is a graph showing the dependence of the read speed on the power supply voltage Vcc.

FIG. 18 is a graph of temperature dependence of read speed.

FIG. 19 is a diagram showing a configuration of a conventional semiconductor memory device.

20 is a time chart of main signals of the conventional semiconductor memory device shown in FIG.

FIG. 21 is a time chart of main signals during a read operation of the circuit shown in FIG. 11;

FIG. 22 is a time chart of main signals during a read operation of the circuit shown in FIG. 11;

[Explanation of symbols]

N11, N12 NMOS transistor ND11 Non-doped transistor P13, P14 PMOS transistor Vcc Power supply voltage V11, V12 Constant voltage O11 Output of threshold voltage detection circuit NOR31 NOR circuit NAND31, 32 NAND circuit DELAY circuit 31, 32 Circuit having a plurality of inverters connected ATDIN31 Input signal of ATD pulse generation circuit ATDOUT32 Output signal of ATD pulse generation circuit DELAYIN41 Delay circuit input DELAYOUT41 Delay circuit output N51, N52 NMOS transistor P51, P52 PMOS transistor ND51 Non-doped transistor Vcc Power supply voltage V51, V52 Constant voltage O51 Threshold voltage detection Circuit output M101, M102 Memory cell transistor R101 Reference Scan cell transistors V101 gate application voltage of the memory cell WL101,102 word line BL101,102 bit lines F101, F102 gate voltage applied feedback NOR circuit V102 reference cell P101, P102 PMOS transistor Vcc supply voltage S. A101 Conventional sense amplifier A output Sense amplifier output NOR111 NOR circuit NAND111, 112 NAND circuit DELAY circuit 111, 112 A circuit in which a plurality of inverters are connected ATDIN111 Input signal of ATD pulse generation circuit 111 Output signal of DELAY circuit 41 112 Output signal of NOR41 113 Output of NAND41 circuit Signal ATDOUT111 Output signal of ATD pulse generation circuit ATDIN111 Input signal of ATD pulse generation circuit 111 Output waveform of DELAY circuit 41 112 Output waveform of NOR41 113 Output waveform of NAND41 circuit ATDOUT111 Output waveform of ATD pulse generation circuit N161, N162 NMOS transistor N163 N164 NMOS transistor N165, N166 NMOS transistor M161, D161 Recell CS161, CS162 Capacitor CC161, CC162 Capacitor BL161, BL162 Bit line WL161, WLD161 Word line LATCH PULSE Latch pulse waveform SENSE AMP OUTPUT Sense amplifier output waveform LATCH PULSE Latch pulse waveform SENSE AMP output AMP 202 AMP AMP output , 203 threshold voltage detection circuit 201, 202, 203 threshold voltage detection circuit 211 threshold voltage detection circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/41-11/419 G11C 29/00 G01R 31/26 H01L 21/64-21/66

Claims (7)

(57) [Claims] 1. A semiconductor memory device comprising an internal circuit using a second transistor having a threshold voltage which is a parameter fluctuating by diffusion, wherein a threshold voltage for detecting and correcting the parameter fluctuating by diffusion is provided. Detecting and correcting means, wherein the threshold voltage detecting and correcting means has a substrate density in a channel portion.
Lower than normal transistors, diffusion threshold
The first voltage variation is smaller than the second transistor
Transistor threshold voltage and said second transistor
The level of the threshold voltage is determined, and the threshold voltage is compensated.
Positively, the semiconductor memory device, characterized in that. 2. A semiconductor memory device comprising an internal circuit using a second transistor having a threshold voltage which is a parameter fluctuating by diffusion, wherein a threshold voltage for detecting and correcting the parameter fluctuating by diffusion is provided. A detection and correction means, wherein the threshold voltage detection and correction means uses a first transistor whose substrate concentration in the channel portion is lower than that of a normal transistor and whose threshold voltage fluctuation due to diffusion is smaller than the second transistor. A constant voltage is applied to each of the gates of the first and second transistors, a current flowing through the first transistor is used as a reference current, and a current value flowing through the second transistor is smaller than the reference current. Determining whether the threshold voltage of the second transistor is high or low based on whether the threshold voltage is large or small, and correcting the threshold voltage. A semiconductor memory device characterized by the above-mentioned. 3. The threshold voltage detection and correction means compares the threshold voltage with the current flowing through the first transistor and the current flowing through a second Nch transistor or Pch transistor forming a normal peripheral circuit. 3. The semiconductor memory device according to claim 2 , wherein the operation is performed by performing the following. 4. A method according to claim 1, wherein a plurality of said first transistors are prepared as said reference current in said threshold voltage detection and correction means, and different constant voltages are applied to gates of said plurality of first transistors, respectively. one of the by applying a plurality of times with different constant voltage of the voltage with a time difference to the gate of the first transistor, the semiconductor memory device according to claim 2, or 3, wherein the obtaining the reference current. 5. An address transition detection circuit (ATD) after detecting a threshold voltage by said threshold voltage detection and correction means.
Of performing correction by adjusting the pulse width, the semiconductor memory device according to any one of claims 1 to 4, characterized in that. 6. The threshold voltage detecting and correcting means detects a threshold voltage in a test mode, and stores a read margin optimization in a fuse cell based on a result of the detection. Item 6. The semiconductor memory device according to any one of Items 1 to 5 . 7. A comparison is made between a current flowing through a non-doped first transistor, which is less dependent on threshold voltage due to diffusion, and a current flowing through a normal second transistor used in a peripheral circuit or the like. Threshold voltage detecting means for judging the level of the threshold voltage is provided, and when the threshold voltage is judged to be high, an operation margin is expanded by expanding a latch pulse of a data latch circuit for latching the output of the sense amplifier. A semiconductor memory device characterized in that: