JPS62188090A - Voltage detection circuit - Google Patents

Abstract

PURPOSE:To detect a power source voltage drop with a constitution in which no transistor of high threshold voltage is required, by utilizing a voltage drop caused by plural stages of transistors. CONSTITUTION:Three, for example, transistors 1-3, the drain and the gate of which are connected in common, are connected to a power source 10 with a voltage of VCC in series with a threshold value VH, and the voltage at a node (a) goes to VCC-3VH by the voltage drop through the transistors 1-3. And when the voltage VCC drops more than a prescribed level, an N-type of transistor 5 in an inverter 6 is turned off, and a node (b) goes to H, then the power source voltage drop is detected. By the use of the plural transistors, the power source voltage drop can be detected using an usual transistor, without using the transistor with high threshold voltage, and a switching to a data retention mode can be performed automatically.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a circuit for automatically entering a data retention mode in a semiconductor memory device in the event of a power supply voltage drop, particularly for detecting a power supply voltage drop. This relates to a voltage detection circuit.

[Conventional technology]

Among semiconductor memory devices, CMOS static RAM has a data retention function. This is the chip select (
When C8) is turned off by MOS level input, the DCWL flow path in the internal circuit disappears, and the current decreases from several tens of nA to several μA.
This function allows the memory contents to be retained even if the power supply voltage is lowered to a certain degree (ft2ν). This function is commercial
This is a unique advantage of OS static RAM, and is a function suitable for battery backup. - In the data retention mode, the memory can be retained even if the power supply voltage drops, but if the power supply voltage drops for some reason in the normal active state, the memory cannot be retained. Therefore, there is a need for a function (all-data retention) that detects a drop in the power supply voltage and automatically enters the data retention mode, and a circuit for detecting this voltage drop is shown in FIG. 2. In Figure 2, 11
has a threshold voltage (hereinafter abbreviated as VTR) of 3.0.
(V), and this MO8 transistor 11 has an input, that is, a power supply 10
turns on when the voltage Vcc of 3.0 (V) or more,
) or below to turn it off. 12 is a high resistance, and the MO8
This is to suppress the through current flowing from VCC to ground (GND) when the transistor 11 is in the on state. Also, 4 and 5 are normal VTRs (0, 86/
), and both of them constitute a 6ft inverter. Therefore, the node bftCS buffer of this inverter 6 (
(not shown), it is active when the power supply voltage VCC is 3.07 or higher, and VCC is 3.07 or higher. It becomes data retention mode when it is below Ov, and the chip can have an automatic data retention function.

Note that in FIG. 2, a represents a node connecting the drain side of the MO8 transistor 11 and the input end of the inverter 6.

[Problem that the invention seeks to solve]

However, in the conventional voltage detection circuit shown in FIG. 2, in order to detect a drop in the power supply voltage VCC, the VTR is
, 0v), a special manufacturing process is required for that element. As a result, the manufacturing process of a semiconductor memory device having a data retention function has become complicated, which has been a factor causing a decrease in yield and an increase in cost.

This invention was made to solve all of the above-mentioned problems, and by using an MO8 transistor element, which is equivalent to the peripheral circuit, as a circuit element for detecting a drop in power supply voltage, it can be realized without using any special manufacturing process. It is an object of the present invention to provide a voltage detection circuit that can easily realize a semiconductor memory device that also has an automatic data retention function.

[Means for solving problems]

A voltage detection circuit according to the present invention includes a first MO8 transistor whose drain and gate are commonly connected to a power supply to be detected in a semiconductor voltage detection circuit that detects a drop in power supply voltage; A second MO whose drain and gate are commonly connected to the source.
8 transistor, and a third MOB transistor whose drain and gate are commonly connected to the source of the second MOB transistor, the source of the third MOB transistor is connected to the input terminal of the inverter, and the high It is connected to ground potential via a resistor.

[For production]

In this invention, the V of multiple stages of MO8 transistors is
By utilizing the voltage drop due to TH, a drop in the power supply voltage can be detected using a normal MO8 transistor without using a special MOS transistor with a VTR of about 3.0 (V) as in the past. .

[Embodiments of the invention]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. In the same figure, 1, 2.3 are N-channel MOS transistors, 4 is an inverter 60P channel MO8 transistor,
5 is an N-channel MO8 transistor of the inverter 6, and 6 is a high resistance.

That is, the drain and gate of the first MO8 transistor 1 are commonly connected to the power supply 10, and this MOS
The drain and gate of a second MO8 transistor 2 are commonly connected to the source of the transistor 1 .

Similarly, the drain and gate of a third MO8 transistor 3 are commonly connected to the source of the second MO8 transistor 2, and the source of this MO8 transistor 3 is connected to the input terminal s2i! - It is connected to the common input terminal of the MO8 transistors 4 and 5 that constitute it, and is also connected to the ground (GND) via a high resistance 6. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Next, the operation of the circuit of the above embodiment will be explained.

Here, each of the N-channel MO8 transistors 1, 2 and 3 are equivalent to the normal N-channel MOS transistor 5 that constitutes the inverter 6;
[7th direct voltage toTHN of 8 transistors 1, 2, 3
Assuming this, a voltage lower by IVTHN than the voltage VCC of the power supply 10 is obtained at the source of each MO8 transistor 1, 2, and 3 by one transistor. Therefore, the potential of node a becomes V((3VTHN). Therefore, each channel MOS transistor 1.

N channel M of inverter 6 with normal VTHN of 2.3
Similar to the O8 transistor, when the voltage is around 0.8M), the potential of node a is Vcc = 3 (VCC3V at Vl).
THN = 0.6 (M). Therefore, when such a voltage is input to the inverter 6, the MO8 transistor 5 is turned off and rHJ is output to the node b. On the other hand, from the MO8 transistor 4ftMO8 transistor 5 If the transistor has a sufficiently large channel width W, MO
Even if a voltage slightly higher than ■Tit of the 8-transistor 5 is input, "L" is output to the node b. That is, in the circuit of the above embodiment, the output is "L" when Vcc is 3 V or more, and the output is rHJ when Vcc is 3 V or less, and the chip can be provided with an auto data retention function as in the conventional case. Note that the potential of the node a of the high resistance 6 is VC
This element is used to release the charge at node a so as to follow the change in C, and this element is often used in static RAM that uses high resistance load type memory cells. There is no problem with the power supply current.

Note that the present invention is not limited to the embodiments described above, and it goes without saying that the three-stage N-channel MO8 transistor for detecting a drop in the power supply voltage can be changed as appropriate depending on the power supply voltage. be.

〔Effect of the invention〕

As described above, according to the present invention, by utilizing the voltage drop due to VTH of MO8 transistors in multiple stages, ordinary MO8 transistors can be used without using MO8 transistors with high vTH as in the past. This has the advantage that a semiconductor memory device having an automatic data retention function can be easily obtained without any special process.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a voltage detection circuit diagram according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional voltage detection circuit. 1.2,3...N-channel MO8 transistor, 6
11...Inverter, 7...High resistance, 10...
·power supply. Agent Masuo Oiwa Figure 1 Figure 2

Claims (2)

[Claims] (1) A semiconductor voltage detection circuit that detects a drop in power supply voltage includes a first MOS transistor whose drain and gate are commonly connected to the power supply to be detected, and whose drain and gate are connected to the source of the first MOS transistor. It has a second MOS transistor connected in common, and a third MOS transistor whose drain and gate are connected in common to the source of the second MOS transistor, and the source of the third MOS transistor is connected to the source of the inverter. 1. A voltage detection circuit, characterized in that it is connected to an input end and also connected to a ground potential via a high resistance to detect a drop in voltage of the power supply. (2) The voltage detection circuit according to claim 1, wherein the first, second, and third MOS transistors are of N-channel type.