JPH03295099A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To easily and surely conduct the fuse electric characteristic test by providing a fuse check pad to a fuse type storage IC. CONSTITUTION:Check pads 25, 28, 26 or the like for a fuse 29 are provided to a memory cell provided with the fuse 29 and whose ROM information is written by fuse blown. With a positive level of a stationary power supply 38 of a test equipment 35A connected to the pad 25 through a probe 50, with a negative level of a variable power supply 37 connected to the pad 28 through a probe 52, and with an ammeter connected to the pad 26 through a probe 51, when a voltage of the power supply 27 is changed, a current I1 corresponding to the non-blown, half-blown and blown state of the fuse 29 is detected respectively by the ammeter 36 and the electric characteristic test of the fuse is easily and surely conducted.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor integrated circuits and fuse-type memory circuits included therein, and is applicable to, for example, redundant selection of semiconductor integrated circuits and analog/digital mixed type semiconductor integrated circuits. This article describes techniques that are effective when applied to gain adjustment of the included amplifier circuits.

[Conventional technology]

One unit circuit of a conventional fuse-type memory circuit used in a semiconductor integrated circuit has one unit, for example, a pair of power supply terminals Vdd and Vss.
In between, a P-channel type MO5FET to form a relatively large resistance, a fuse, and a resistance element are connected in series, and information is stored depending on whether the fuse is fused or not fused. It had become. To store low-level information in this fuse-type memory circuit, it is sufficient to keep the fuse connected, and to store high-level information, apply voltage to this fuse or irradiate it with laser light. Then, the fuse can be blown out.

Conventionally, the blown and unfused states of such fuses have been visually inspected, and the electrical characteristics of the fuse itself have not been tested until the operation of the semiconductor private product circuit including the fuse has been tested. That was considered sufficient.

An example of a document describing a fuse type memory circuit is Japanese Patent Laid-Open No. 144100/1983.

[Problem to be solved by the invention]

However, according to the inventor's study of the above-mentioned prior art, it has been revealed that there are the following problems.

If the fuse to be blown is not completely blown and is in a so-called partially fused state, the stored information will not be at a low level or high level with sufficient margin, and the information will not be at a low or high level with a sufficient margin, and the fuse will not be completely blown. Even if a desired logic result is obtained in an operation test, the logic state of the arranged level determination circuit may later be reversed due to a temperature change in the logic threshold level. However, with the above-mentioned conventional technology, such an abnormality cannot be detected in advance. In addition, the conventional visual inspection described above can also detect abnormalities in characteristics due to defects in the so-called vertical structure or cross-sectional structure, such as cases where the surface is not melted but is actually melted, or vice versa. Difficult to detect.

An object of the present invention is to provide a technique that allows easy testing of the electrical characteristics of the fuse itself.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a semiconductor integrated circuit is constructed by providing a fuse testing pad that enables energization to test the electrical characteristics of the fuse itself, which constitutes a part of the memory circuit.

In order to be able to conduct a good electrical characteristic test of the fuse by shortening the wiring length from the fuse testing pad to the fuse, it is preferable to arrange the fuse testing pad close to the fuse. Also,
In order to smoothly test the electrical characteristics of the fuse itself, it is preferable to expose the pad from the surface protective film of the wafer.

[For production]

According to the above-mentioned means, it is possible to supply electricity for testing the electrical characteristics of the fuse via the test pad, which facilitates the testing of the electrical characteristics of the fuse itself.

〔Example〕

FIG. 10 shows a semiconductor memory device which is an embodiment of the semiconductor integrated circuit according to the present invention. The semiconductor memory device shown in the figure is formed on one semiconductor substrate made of, but not limited to, single crystal silicon.

The memory cell array 4 is made up of a plurality of memory cells arranged in an array, and the row address of the memory cell array 4 is an address signal A from the outside.

It is indicated by the output of the row address decoder 2 which decodes ~An. In this embodiment, when a part of the memory cell array 4 includes a defective bit that cannot be repaired, in order to improve the yield of the semiconductor memory device by replacing it with a spare element, a redundant memory cell array is used. 3 and redundant row address decoder 1
is provided. The redundant row address decoder 1 receives the address signal A from the outside. -An is taken in, and the output of this decoder 1 causes the redundant memory cell array 3
The row address of is specified. As a result, defective bits included in memory cell array 4 are replaced with spare elements of redundant memory cell array 3.

Note that the column address system is omitted in No. 10.

FIG. 11 shows a detailed configuration of the redundant address decoder 1. As shown in the figure, the redundant address decoder 1 includes address signals A0 to A, although not particularly limited.
Fuse type storage units 7□ to 7n arranged corresponding to n, outputs of these storage units 7□ to 7n, and address signals A, to A
It includes comparison units 8□ to 8n that perform a comparison to determine whether or not they match, and a selection circuit 9 that selects a word line of the redundant memory cell array 3 based on the comparison result.

FIG. 1 shows a detailed configuration example of the fuse type storage section 7□.

This fuse type storage section 7□ is located between the first power source Vdd and the second power source Vss, although it is not particularly limited.

P-channel type MO8FET (MO3 field effect transistor) Ql, fuse 29, N-channel type MO3F
A series circuit of ETQ2 is provided. MO8FETQI,
The gate of Q2 is commonly connected to the output terminal of an inverter 24, and the relief determination signal φRE is transmitted through the inverter 24.
D is now transmitted. This relief judgment signal φ
RED is generated inside the semiconductor integrated circuit.

Furthermore, in this embodiment, fuse test pads (hereinafter also simply referred to as pads) 25 to 28 are provided to enable energization for testing the electrical characteristics of the fuse 29. These pads 25 to 28' are exposed through partial openings in the surface protection film on the wafer in order to enable electrical contact with inspection probes in electrical property tests to be described later, although this is not particularly limited. . That is, pad 2
5° 26 is exposed in opening 20, pad 27 is exposed in opening 21, and pad 28 is exposed in opening 23.
exposed in Note that the fuse 29 is exposed at the opening 22 and can be fused by laser beam irradiation.

If the fuse is not blown, MO5FTQ1
．． Q2 is operated as an inverter and MO8FETQI
The level of the connection point (output node) 30 between the fuse 29 and the fuse 29 becomes equal to the relief determination signal φRED. However, when fuse 29 is blown, the level of output node 30 is fixed at a high level regardless of the state of relief determination signal φRED.

FIG. 2 shows an example of the layout of the main parts of the fuse-type storage section 7□.

The pads 26 and 27 are connected to aluminum wiring layers 31 and 32, respectively, and a fuse 29 before being fused is provided to bridge the aluminum wiring layers 31 and 32. The fuse 29 is made of, but not limited to, polysilicon or the like.

In particular, the pads 26 and 27 shown in FIG. 2, together with the aluminum wiring layers 31 and 32, form the current conduction path of the fuse 29, and in order to increase the accuracy of the electrical characteristic test of the fuse 29, this current conduction path must be The layout of the pads 26, 27, etc. is determined so as to be as short as possible. In this embodiment, pads 27 and 28 are connected to fuse 2.
9 as close as possible. Also, pad 26.27
etc. are used only for testing the electrical characteristics of the fuse 29, so the increase in aluminum wiring area can be suppressed by making them as small as possible under conditions that allow electrical contact with the test probe. Do it like this.

Note that the other storage units 7□ to 7n are also configured in the same manner as described above.

Next, an electrical characteristic test (electrical characteristic test) of the fuse 27 will be explained.

FIG. 3 shows the voltage-current characteristics of the fuse 29.

As shown in the figure, the voltage-current characteristics vary depending on the state of the fuse 29, that is, unfused, partially fused, and fully fused, and it is possible to test the electrical characteristics of the fuse 29 by utilizing such characteristics.

4 to 8 show preferred electrical characteristic tests of the fuse 29 based on the above principle.

In the test example shown in FIG. 4, an ammeter 36, a variable power supply 3
7. A testing machine 35A including a fixed power source 38 is used. The positive side of the fixed power source is coupled to the pad 25 via the probe 50, one end of the ammeter 36 is coupled to the pad 26 via the probe 51, and the negative side of the variable g37 and the fixed power source 38 are connected via the probe 52. It is coupled to pad 28.

The potential of the fixed power supply 38 is made equal to the first power supply Vdd, and therefore the MO3FET Q2 is turned on. In this state, the ammeter 36, pad 26, fuse 29, MO
A current □ flows through the 3FET Q2 and the pad 28, and the value of this current □ varies depending on the blown state of the fuse 29 (see FIG. 3). Therefore, the blown state of the fuse 29 can be detected by appropriately changing the voltage of the variable power supply 37 and reading the value of the ammeter 36 at that time.

That is, when a large current flows at a low potential, fuse 2
9 is in a non-melting state, and when almost no current flows regardless of potential changes, the fuse 29 is in a completely melting state. Further, when the current is between the current when the fuse is completely blown and the current when the fuse is not blown, the fuse is half blown.

In the test example shown in FIG.
Testing machine 35B containing 7 is used. One end of the ammeter 36 is coupled to the pad 26 via a probe 51, and the negative electrode side of the variable power supply 37 is coupled to the pad 27 via a probe 52. In this test example, MO
Since 5FETQ2 is not included, this MO8FETQ2
The power supply 38 (see FIG. 4) for turning on the power supply is not required. Note that, as in FIG. 4, the blown state of the fuse 29 can be detected based on the value of the current I2.

In the test example shown in FIG. 6, a tester 35C including a voltmeter 41, a variable resistor 40, and a fixed power source 38, 39 is used. The positive side of the fixed power supply 39 is coupled to the pad 26 via a variable resistor 40 and a probe 53. Voltmeter 41
is connected between pads 28 and 26 via probes 52 and 53.

That is, the blown state of the fuse 29 can be detected by measuring the potential drop across the fuse 29 with the voltmeter 41. At this time, the variable resistor 40 acts as a range switch. Therefore, in the test example shown in FIG. 6, by changing the range using the variable resistor 40, the indication on the voltmeter 41 can be adjusted to be appropriate.
Measurement accuracy can be increased.

In the test example shown in FIG. 7, a tester 35D including a variable resistor 4o, a voltmeter 41, and a fixed power source 39 is used.

Voltmeter 41 is connected to pad 26. through probes 53.52.
27. In this circuit, the potential drop at the fuse 29 can be measured regardless of whether MO8FETQ2 is on or off, so as shown in FIG.
The fixed power supply 38 for turning on the FET Q2 is not required (see FIG. 6).

In the testing machine shown in FIG. 8, a testing machine 38 including an inverter 43 and a fixed power supply 38 is used.

The logic threshold of the inverter 43 is set higher than the potential appearing on the pad 26 when the fuse 29 is partially blown. If the output state of the inverter 43 is at a high level before the fuse is blown, the fuse is determined to be normal, and conversely, if it is at a low level, the fuse is determined to be abnormal. If the exclusive OR of the outputs of the inverters 43 in the storage units 71-7n is taken, a plurality of fuses 29 in the storage units 7□-7n can be checked at the same time.

According to the above embodiment, there are the following effects.

(1) Fuse 2 via pad 26, 27 or 28, etc.
Since it is possible to conduct electricity for the electrical characteristic test in 9.
The electrical characteristics of the fuse itself can be easily tested.

(2) In particular, the pad layout was made so that the wiring length from pads 26, 27, etc. to fuse 29 was shortened, so the electrical resistance of the wiring was reduced, and the electrical characteristics test of fuse 29 was performed well. It can be carried out.

(3) Since the fuse inspection pads 25 to 28 are exposed from the wafer surface protective film, the testers 35A to 35
E's probe can easily come into contact with the butt.

(4) According to the electrical characteristics test of the fuse described above, the fuse may be in a partially fused state, or even in cases where it is ostensibly unfused but actually fused, or vice versa.
Characteristic abnormalities caused by so-called vertical structural defects can be easily detected, contributing to improved reliability of semiconductor memory devices.

Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, as shown in FIG.
A two-man Canand gate 60 may be provided at the front stage of the Nand gate 2, one input terminal of the Nand gate 60 may be coupled to the pad 25, and the relief determination signal φRED may be input to the other input terminal. In this configuration, since the Nant gate 60 functions as an inverter only when the pad 25 is fixed at a high level, the relief determination signals φR, E
As far as D is concerned, it is equivalent to the above embodiment (see FIG. 1). When a low level signal is input to the pad 25, the MO5FET Q2 is turned on, thereby making it possible to test the fuse 29 using the test example shown in FIG. 4 or FIG. 6. In this case, the fixed power supply 38 is not required, and instead, the probe 50 is connected to the low level.

Further, although the above embodiments have been described as having pads 25 to 28, according to the test examples shown in FIGS. 4, 6, and 8, the pad 27 is unnecessary, and According to the illustrated test example, the pads 25 and 28 are unnecessary, so the pads 27 and 25 and 28 may be omitted by limiting the test method.

In the above explanation, the invention made by the present inventor has been applied to a semiconductor integrated circuit, which is the background field of application, but the present invention is not limited thereto. It can also be used as a circuit for adjusting the gain of amplifiers included in semiconductor integrated circuits, and can also be applied to semiconductor integrated circuits such as bipolar and BI-CMO5 types in addition to MO8 type semiconductor integrated circuits. be able to. The present invention can be applied at least to those in which the circuit function is changed using a fuse circuit.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, by providing a pad for fuse inspection, it is possible to easily test the electrical characteristics of the fuse itself, and it is possible to detect abnormalities in characteristics due to half-blown fuses or defects in the vertical structure using conventional visual inspection. various drawbacks of the above can be eliminated.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the main parts of a semiconductor memory device which is an embodiment of the semiconductor integrated circuit according to the present invention, FIG. 2 is a layout pattern diagram of the main parts of the circuit shown in FIG. 1, and FIG. 3 is the above-mentioned Electrical characteristic diagrams of fuses applied to semiconductor storage devices; FIGS. 4 to 8 are circuit diagrams showing electrical characteristic test examples of the fuses described above; FIG. 9 is a modified example circuit of the circuit shown in FIG. 1. Figure, 10th
The figure is a block diagram of m semiconductor memory devices including the circuits shown in FIG. 1 or 9, and FIG. 11 is a block diagram of the main parts of the device shown in FIG. 10. DESCRIPTION OF SYMBOLS 1... Redundant decoder, 2... Row address decoder, 3... Redundant row address decoder, 4... Memory cell array, 7□~7n... Fuse type storage section, 8□~
8n... Comparison section, 9... Selection circuit, 20-23...
Opening, 25-28 ・Fuse inspection pad, 29・
...Fuse, 30...Output node, 31.32.Aluminum wiring, 35A~35E...Testing machine, Vc
ld...first power supply, Vss...second power supply. Figure 1 Figure V pressure (V) Figure

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit including a fuse-type memory component that enables information to be written by blowing the fuse, a fuse testing pad is provided that enables electricity to be applied to test the electrical characteristics of the fuse itself. A semiconductor integrated circuit characterized by: 2. The semiconductor integrated circuit according to claim 1, wherein the fuse testing pad is located close to a fuse that can be energized through the pad. 3. The semiconductor integrated circuit according to claim 1 or 2, wherein the fuse testing pad is exposed through a partial opening in a surface protection film of the wafer.