JP3025476B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a circuit for enabling its own inspection and repairing itself when a defect occurs.

[0002]

2. Description of the Related Art When a CMOS circuit is used, only one of a PMOS circuit and an NMOS circuit constituting the circuit is turned on, so that current consumption is small. Therefore, when an abnormality such as a bridge between wirings occurs in the CMOS circuit, the order of current consumption increases by two to three digits. Utilizing this, when inspecting an LSI constituted by a CMOS circuit, a method of detecting a failure by observing an increase in a current value, specifically, a standby current test, an IDDQ test, or the like is used.

On the other hand, in recent years, as the power supply voltage of the LSI has been reduced for the purpose of reducing power consumption, a threshold voltage (hereinafter referred to as Vt) has been set for a MOS transistor included in a CMOS circuit in order to secure an operation speed. It is strongly demanded to reduce the above. However, when the Vt is low, the leakage current of the MOS transistor during standby increases, so two methods have been developed for the purpose of reducing power consumption during standby. The first method is to control the CMOS circuit by controlling the substrate voltage so that the Vt at the time of standby of each MOS transistor is set.
So-called variable thres
hold-voltage-CMOS (hereinafter VT-C)
MOS)). A second method is a configuration in which a CMOS circuit is turned off during standby by using a high Vt MOS transistor and a circuit formed of a low Vt MOS transistor, that is, a so-called multi-threso.
This is a method of configuring an ld-CMOS (hereinafter, referred to as MT-CMOS). MT-CMOS has the advantage that the switching time from the operation mode to the standby mode is shorter than that of VT-CMOS.

[0004]

However, according to the above-described MT-CMOS structure, the leakage current in the standby mode is increased by each of the low Vt MOS transistors constituting the CMOS circuit. The ratio of the increase in the abnormal current becomes small, so that it becomes difficult to detect the abnormality, and the IDDQ test or the like becomes difficult.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a semiconductor integrated circuit including a MOS circuit composed of low Vt transistors, which enables an increase in current due to an abnormality in the MOS circuit to be inspected.

[0006]

In order to achieve the above object, the present invention divides a circuit to be inspected comprising a low Vt MOS transistor into a plurality of circuit blocks, and sets the plurality of circuit blocks in a normal standby mode. A high-Vt MOS transistor for turning off the power supply of the circuit block is also used at the time of leakage current inspection. That is,
For each small circuit block, the circuit current of the small circuit block is guided to the inspection circuit via a high Vt MOS transistor.

Further, according to the present invention, in a semiconductor integrated circuit, a circuit block determined to be defective based on a result of inspection of a leak current is replaced with another circuit block prepared in advance. .

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor integrated circuit according to the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration example of a semiconductor integrated circuit according to the present invention. In FIG. 1, a scan register 210 is a circuit block selecting means for sequentially transferring received block selection data BS by a clock CP and supplying block selection signals S11 to S61. Circuit block switching unit 220
A and 220B apply the circuit voltage VCIR to the circuit under test 230 composed of the circuit blocks AB,..., TG, and receive the test enable signal TE, the block selection signals S11 to S61, and the operation selection signal / OP. , I61,..., I61 or a path to the ground GND. Here, "/" indicates that the signal is of negative logic. The circuit under test 230 is a circuit composed of, for example, an SRAM, a ROM, a logic circuit, and the like formed on the same chip and divided into a plurality of circuit blocks AB,..., TG. The inspection circuit 240 interrupts the path of the detection current to be received in the normal state, generates a reference current based on the received reference voltage VREF during the inspection, and sets the received detection current and the generated reference This is an inspection means for comparing the current with the current, and supplying a block inspection result T in a predetermined case. The register circuit 250 sequentially shifts the received block inspection result T to generate block inspection data D11 to D61 as parallel data,
Further, it is a storage means for supplying as necessary when a defective circuit block is to be specified.

The operation of the semiconductor integrated circuit shown in FIG. 1 will be described. The scan register 210 sequentially transfers the block selection data BS composed of “HLLLL...” In which only the first bit is “H” by the clock CP, and sequentially shifts one of the block selection signals S11 to S61 to “H”.
Supply. Circuit block switching units 220A and 22
0B indicates that the received test enable signal TE is “H”
, The path of the circuit current of the circuit blocks AB,..., TG is switched, and the current corresponding to the circuit block whose received block selection signals S11 to S61 are “H” among the detection currents I11,. , To the inspection circuit 240. When the received test enable signal TE is "L" and the operation selection signal / OP is "H", all the circuit currents I11,.
1 to the inspection circuit 240, and if the operation selection signal / OP is "L", all the circuit currents I11,..., I61 flow out to the ground GND. At the time of inspection, the inspection circuit 240 generates a reference current that is a reference value in advance based on the received reference voltage VREF,
If the received detection current exceeds the value of the reference current, a block test result T indicating that the circuit block is defective is supplied. At the time of normal operation, the current path of the circuit current to be received is cut off. The register circuit 250 sequentially generates the block inspection data D11 to D61 indicating which circuit block is defective by sequentially shifting the received block inspection result T, and supplies the data as needed. With the above operation, the circuit current of one or a plurality of circuit blocks selected from all the circuit blocks AB,..., TG can be inspected.

FIG. 2 is a configuration diagram of the circuit under test 230 and the circuit block switching units 220A and 220B in FIG.
In FIG. 2, address buffers 231,..., First memory blocks 232,.
The timing generators 234 are circuit blocks that constitute the circuit under test 230, respectively. Each circuit block to which the circuit voltage VCIR is applied has a normal current path through which each circuit current flows to the ground GND and a current path during inspection through which each of the detection currents I11 to I61 formed by each circuit current flows. Have. In addition, each circuit block includes a low Vt NMOS transistor TL.
CM composed of N and PMOS transistors TLP
An OS circuit. High Vt PMOS transistor THP
Reference numerals 11 to THP61 are power line switching means which constitute the circuit block switching unit 220A and include elements for interrupting a current path to the ground GND for each circuit block, that is, a normal current path. High Vt NMO
The S transistors THN11 to THN61 are power line switching means including elements for cutting off a current path to a test circuit for each circuit block, that is, a current path at the time of test. Low Vt NMOS transistors QN11-QN
61 and low Vt PMOS transistors QP11-Q
P61 is a drive element for switching each of the high Vt MOS transistors.
A circuit block switching unit 220B is configured together with the S transistors THN11 to THN61.

[0011] Circuit block switching units 220A and 220B
Will be described. As a first case, consider a case where the test enable signal TE is “H”. In this case, the low Vt NMOS transistors QN11 to QN61
Are turned on at the same time, all the low Vt PMOS transistors QP11 to QP61 are turned off. Thus, the block selection signals S11 to S6 of each circuit block are obtained.
1 is supplied to the gate of each high Vt MOS transistor. In the selected circuit block in which the block selection signals S11 to S61 are “H”, the high V
At the same time, the corresponding one of the t NMOS transistors THN11 to THN61 turns on, and the corresponding one of the high Vt PMOS transistors THP11 to THP61 turns off. As a result, the current path at the time of inspection is connected to the selected circuit block,
In addition, the normal current path is cut off. Therefore, the circuit current of the circuit block becomes a corresponding current among the detection currents I11 to I61 and is supplied via the current path at the time of inspection. At this time, the block selection signals S11 to S11
The circuit block in which 61 is “L” is not related to the inspection because the circuit current flows to the ground GND.

On the other hand, when the test enable signal TE is "L"
, The low Vt NMOS transistor QN1
1 to QN61 are all turned off, and at the same time
All the OS transistors QP11 to QP61 are turned on. As a result, the operation selection signal / OP is supplied to the gates of the respective MOS transistors having the high Vt.
As a second case, consider a case where the test enable signal TE is "L" and the operation selection signal / OP is "H". In this case, all the high Vt NMOS transistors THN11 to THN61 are turned on, and at the same time, all the high Vt PMOS transistors THP11 to THP61 are turned off. As a result, the current paths at the time of inspection are connected to all the circuit blocks, and all the current paths at the time of normal operation are cut off. Therefore, the detection currents I11 to I61, which are the circuit currents of all the circuit blocks, are supplied via the current path at the time of inspection. In this case, the current path is separately cut off at the supply destination as described later, and the entire circuit current of the circuit under test 230, that is, the current consumption becomes zero. As a third case, consider a case where the test enable signal TE is “L” and the operation selection signal / OP is “L”. In this case, all of the high Vt NMOS transistors THN11 to THN61 are turned off, and at the same time, all of the high Vt PMOS transistors THP11 to THP61 are turned on. As a result, the normal current paths are connected to all the circuit blocks, and all the current paths during the inspection are cut off. Therefore, the circuit currents of all the circuit blocks flow out to the ground GND via the normal current path, and the normal operation becomes possible. At the time of inspection, the combination of signals in the first case, the second case in the normal standby mode, and the third case in the normal operation mode are used.

FIG. 3 is a circuit diagram of the inspection circuit 240 in FIG. In FIG. 3, the reference current determination circuit 24
1 is a current designation signal L1 based on parallel data in which only one bit is “1” in order to determine a current reference value.
To L4, and is composed of a reference current determining memory 242 for storing the parallel data. The reference current generation circuit 243 determines and supplies a reference current from the received reference voltage VREF based on the supplied current designation signals L1 to L4 . Reference current determination note
From the reference 242 and the reference current generation circuit 243
Value generating means is configured. The comparison circuit 244 interrupts the current path of the detection current to be received in the normal state, and compares the received detection current of the detection currents I11 to I61 with the received reference current during the inspection, and When the detected current exceeds the reference current, it is a comparing means for setting the block inspection result T to "H" and outputting the result. Reference current generation circuit 2
43 is a reference current determining resistor RR1 to RR5;
The comparison circuit 244 includes MOS transistors Q1 to Q5, and the voltage dividing resistors R1A, R2A, R1B, R2
B, MOS transistors Q6, Q7 and a comparator 245. The voltage dividing resistors R1A and R1B, and R2A and R2B have the same resistance value, respectively. The bias voltage VA adjusts the value of the current flowing through the MOS transistors Q6 and Q7, and normally the MOS transistor Q6
6 and Q7. The bias voltage VB is a voltage for adjusting the value of the constant current flowing through the comparator 245 and for turning off the comparator 245 at normal times.

The operation of the inspection circuit 240 will be described. The inspection circuit 240 supplies a reference voltage V which is a power supply only at the time of inspection.
REF is supplied to operate. Normally, the reference voltage V
Since REF is not supplied to the test circuit 240 and the MOS transistors Q6 and Q7 and the comparator 245 are all off, the current paths of the detection currents I11 to I61 to be received from the circuit under test 230 are cut off. As a result, in the normal standby mode, the entire circuit current of the circuit under test 230, that is, the current consumption becomes zero. At the time of inspection, the inspection circuit 240 is supplied with the reference voltage VREF.
The standard power supply voltage Vdd of the circuit under test 230 is supplied to the circuit under test 230 as the circuit voltage VCIR.
The reference current determination circuit 241 supplies current designation signals L1 to L4 based on 4-bit parallel data included in the reference current determination memory 242. Of the supplied signals by turning on the current indicating signal L3 is a MOS transistor Q3 is "H", dividing the reference voltage VREF using a combination of reference current determination resistor RR1～RR5, MOS transistors
The voltage obtained from the voltage dividing point is supplied to the gate of the MOS transistor Q5 through the resistor Q3 . MOS transistor Q
5 is a reference voltage VRE according to the received gate voltage.
Li the comparison circuit 244 amplifies a current supplied by F
Supply as reference current . The comparison circuit 244 calculates the supplied reference current and the voltage dividing resistors R1A and R2.
A, and the set voltage generated by A is supplied to one input terminal of the comparator 245, and the received detection current and the detection voltage generated by the voltage dividing resistors R1B and R2B are supplied to the other input terminal of the comparator 245. Supply. Comparator 245
Compares the voltages received at the respective input terminals, and if the detected voltage is higher than the set voltage, outputs the block inspection result T as “H”. By comparing the voltages, the received detection current and the reference current can be compared. Further, by supplying the standard power supply voltage Vdd as the reference voltage VREF and appropriately determining the circuit voltage VCIR to be supplied to the circuit under test 230,
For example, an acceleration test can be easily performed by applying an overvoltage as the circuit voltage VCIR. In this case, at the time of inspection, the circuit voltage VCIR and the reference voltage VR are supplied from outside the semiconductor integrated circuit.
In order to supply EFs, terminals corresponding to respective voltages may be provided on the semiconductor integrated circuit.

In the above description, the reference current generation circuit 243 generates the reference current having four values based on the voltage obtained by dividing the reference voltage VREF into four types. However, the present invention is not limited to this, and by using the following configuration, the level of the voltage generated by dividing the reference voltage VREF can be increased, and the value that the reference current can take can be further finely divided.

That is, for example, a total of three reference current determining memories 242 are provided, and the data to be stored is one.
Increase to two. Then, the same combination as the combination of the resistors RR1 to RR4 and the MOS transistors Q1 to Q4 is added to make a total of 12 combinations, and the combination of the resistor and the MOS transistor corresponding to each data of the reference current determination memory 242 is obtained. Is provided. here,
In order to determine the reference current with coarse accuracy, the resistor R
The resistance value of each resistor is set so that R1 to RR4 divide the voltage in a large voltage range. Then, each of the added resistors divides a voltage in a medium voltage range in a large voltage range, and divides a voltage in a small voltage range in a medium voltage range. Set. That is, each of the twelve resistors functions as a low-precision resistor, a medium-precision resistor, and a high-precision resistor, four each . Since the voltage reference voltage VREF this manner is generated by dividing is supplied to the gate of the MOS transistors Q5, the reference current may take more finely divided value. Judging from the characteristics of the circuit to be inspected and the required accuracy, if the inspection can be performed with coarse accuracy, it is desirable to use only four low-precision resistors out of the 12 resistors and to perform the inspection with high accuracy In such a case, the inspection is performed based on the reference currents obtained using the high-precision resistors. The detected current I11 is compared with the value of the reference current by the comparing circuit 244.
To I61 are determined.

According to the above configuration, when the inspection can be performed with a coarse accuracy, only the four low-precision resistors are used, so that the inspection is performed in a short time, and the inspection is performed with higher accuracy as necessary. A semiconductor integrated circuit that can also be realized.

It should be noted that three reference current determination memories each storing 4 bits are provided so that the reference current is 1
Although the configuration has two possible values, it goes without saying that the number of reference current determination memories and the number of bits stored in the memories are not limited to these.

As described above, the reference current is determined by the value input to the reference current determination memory 242. Here, as a modified example of the determination of the reference current, a configuration in a case where the reference current is determined based on the actually measured leak current value, that is, the actually measured value, will be described with reference to FIGS. .

FIG. 4 is a circuit diagram showing a circuit for determining a reference current value based on an actual measurement value. The same components as those in FIG. 3 are denoted by the same reference numerals as those in FIG. 3, and description thereof will be omitted.

In FIG. 4, the inspection circuit 340 is obtained by adding a configuration for sequentially increasing the value of the reference current to the inspection circuit 240 of FIG. The reference current determination circuit 341 is a signal supply unit for supplying current designation signals L1 to L4 based on parallel data in which only one bit is “1” in order to determine a current reference value. The reference current determination circuit 341 includes an inverting circuit NOT including a three-stage inverter and an inverter INV.
And NAND circuits NA1 to NA3, an NMOS transistor Q8, and a reference current determination memory 342. Reference current determination memory 34
2 stores “0” when the operation of the reference current determination circuit 341 starts, and functions as a shift register in accordance with the operation of the reference current determination circuit 341.
Further, it is a storage unit for generating and storing parallel data. The current determination clock ICLK is supplied to the reference current determination memory 342 via the NMOS transistor Q8, and the reference current determination memory 34
2 is a clock for sequentially performing a shift operation. The reference current determining signal IDET is supplied to the reference current determining memory 342, and is a signal composed of only the first one bit “H” and the rest “L”. When the reset signal RESET becomes “L” in a state where the current determination clock ICLK is not supplied to the reference current determination memory 342, the reset signal RESET starts the operation of supplying the current determination clock ICLK to the reference current determination memory 342. It is a signal for making it.

Hereinafter, the operation of the reference current determination circuit 341 will be described. First, a leakage current of a reference block selected in advance among the circuit blocks is measured. As a reference block, a circuit block in which a leak current is expected to be most likely to occur is selected in advance in terms of a circuit configuration. Then, the circuit block switching units 220A, 220 in FIG.
20B, the circuit current of the reference block, which is the circuit under test 230, is passed through the current path at the time of inspection to the comparison circuit 24.
4. The comparison circuit 244 compares the supplied circuit current, that is, the received detection current among the detection currents I11 to I61, with the reference current, and if the received detection current exceeds the reference current, the block inspection result T Is set to “H” and output.

Here, the reference current determination signal IDET of FIG. 4 is based on current determination data "1000... 0" consisting of only the first one bit "1" and the rest "0". The serial signals “HLLL... L” are sequentially supplied according to the clock ICLK. Then, “L” is supplied as the reset signal RESET only when the operation of the reference current determination circuit 341 starts, and “H” is supplied in other cases. That is, when the operation of the reference current determination circuit 341 starts, the reset signal R
Since ESET is “L”, the output of NAND circuit NA3,
That is, one input of the NAND circuit NA2 is fixed to “H”.

First, consider the case where the block test result T is "L", that is, the case where the detected current from the reference block does not exceed the reference current. Since the block test result T and its inverted signal are supplied to each input of the NAND circuit NA1, its output, that is, the other input of the NAND circuit NA2 becomes “H” regardless of the block test result T. I have. As a result, the NAND circuit NA2 receiving “H” as each input supplies “L” and the inverter INV supplies “H”.
The S transistor Q8 turns on, and the current determining clock I
CLK is supplied to the reference current determination memory 342. Therefore, the reference current determination memory 34
2, the reference current determination signal IDET is
The shift is performed sequentially according to the current determining clock ICLK.

Next, a reference current determining signal IDE based on the first bit of the current determining data consisting of "1".
"H" of T is sequentially shifted in accordance with the current determination clock ICLK, and the case where the block inspection result T becomes "H", that is, the case where the detected current from the reference block exceeds the reference current will be considered. In this case,
The block test result T that has become “H” indicates that the NAND circuit NA
After being supplied to one input, the block test result T, which has been delayed and inverted by the inverting circuit NOT, is supplied to the other input from "H" to "L". That is,
Block inspection result T is applied to one input of NAND circuit NA1.
Is supplied to both inputs for a short period of time until the delayed and inverted block test result T is supplied to the other input. Therefore, the NAND circuit NA1 supplies “L” to one input of the NAND circuit NA2 for a short time. In this case, the NAND circuit NA2 supplies "H" regardless of the level of the signal received from the NAND circuit NA3. As a result, the inverter INV supplies “L”, the NMOS transistor Q8 is turned off, and the supply of the current determining clock ICLK to the reference current determining memory 342 is stopped. Therefore, in the reference current determination memory 342, the current determination clock ICL
The reference current determination signal IDET sequentially shifted according to K is fixed. That is, the data representing the detected current from the reference block in this case is stored in the reference current determining memory 342. If the value of the detected current in this case is smaller than a value indicating a fatal defect such as a short circuit due to a bridge between wirings, the held parallel data is converted to the current designation signal L1.
L4 to the reference current generation circuit 243. As a result, the value of the detected current from the reference block, that is, the actually measured value, can be used as the reference value of the leak current.

When comparing the detected current with the reference current again, "L" may be supplied as the reset signal RESET. As a result, the reference current determination memory 342 can be returned to the state at the start of the operation, and the supply of the current determination clock ICLK can be started.

As described above, according to this modification,
A leak current value of a circuit block in which a leak current is expected to be most likely to occur in terms of a circuit configuration is measured, and a leak current of another circuit block is determined based on the measured value. Therefore, by using the actual measurement values as described above, even when the leakage current value changes due to a process variation or the like, the inspection is performed without applying an excessively strict reference value, so that the device is manufactured with a stable yield. A semiconductor integrated circuit is obtained.

Note that the present modified example may be applied to a circuit block which is expected to be most susceptible to a leak current from the viewpoint of a circuit configuration. In this case, since the circuit block most susceptible to the leak current is determined not to be defective, it can be estimated that other circuit blocks are not defective, so that a semiconductor integrated circuit to be inspected with a small number of steps can be realized. You.

As a measurement object for obtaining an actually measured value, that is, a reference block, a circuit block in the same chip or a circuit block in another chip may be used. For example, if it is expected that a leak current is likely to occur in a chip formed in a portion near the outer periphery in a wafer, a circuit block included in such a chip can be used.

In addition, when a circuit block having the same configuration as the block to be inspected is used as a reference block among circuit blocks of another chip, almost the same leak current value can be obtained. Is performed.

Further, an adjacent circuit block adjacent to the block to be inspected may be used as the reference block. As a result, an adjacent circuit block which is considered to be formed under the most similar manufacturing conditions is used as the reference block. Therefore, a semiconductor integrated circuit including a circuit block having a more uniform leakage current distribution is realized, and this configuration is effective, for example, when obtaining a ranked semiconductor integrated circuit. In addition, since the leakage currents of the block to be inspected and the adjacent circuit blocks are always compared, the configuration of the inspection can be simplified.

When a circuit block having a different configuration from the block to be inspected is used as the reference block, a difference in leakage current value may occur due to the difference in the configuration. In such a case, in order to prevent the difference between the non-abnormal leak current values from being determined to be defective,
The inspection may be performed by shifting the threshold value in the comparison circuit 244 of FIG.

In this modification, when the reference current is determined, the supply of the current determining clock ICLK to the reference current determining memory 342 is stopped when the block test result T becomes "H". Is applied to the IDDQ test and the like. That is, the circuit configuration of FIG. 4 can be used even when an abnormality is found during a test such as an IDDQ test on the semiconductor integrated circuit of FIG. In this case, when the block test result T becomes “H”, that is, when the detected current from the reference block exceeds the reference current, the shift operation of the scan register 210 in FIG. 1 is stopped to end the test. Therefore, the inspection time after the abnormality is detected is not required, and the entire inspection time is shortened.

Another modification of the semiconductor integrated circuit according to the present invention will be described with reference to FIG. Even if the circuit block is determined to be defective by the inspection described above, the semiconductor integrated circuit is not discarded,
It is preferable to use the product as a product after repairing it so that the entire circuit operates normally. Therefore, in this modification, a configuration as shown in FIG. 5 is used to obtain a semiconductor integrated circuit that is repaired even if it is determined to be defective. FIG.
3 is a circuit diagram partially showing a circuit obtained by adding a spare block switching circuit to the circuit of FIG. 2; The same components as those in FIG. 2 are denoted by the same reference numerals as those in FIG. 2, and description thereof will be omitted.

The spare block switching circuit 400 in FIG. 5 is switching means for switching a circuit block determined to be defective to a spare block. The spare block switching circuit 400 connects the spare memory block 235 with the high Vt P
MOS transistor THP3Y, high Vt NMOS transistor THN3Y, low Vt NMOS transistor QN3Y, and low Vt PMOS transistor QP3Y
, A switching NMOS transistor SW3Y, fuse means F1 to Fn, and a NAND circuit NA4.

The spare memory block 235 includes a first memory block 232 to an n-th memory block 233 (M1
To Mn) are replacement memory blocks having the same configuration as that of the replacement memory block. High Vt PMOS transistor THP3
Y secures a current path when the spare memory block 235 is used by turning on, and a high Vt NMOS transistor THN3Y secures a current path when the spare memory block 235 is tested by turning on. Power line switching means. The low Vt NMOS transistor QN3Y and the low Vt PMOS transistor QP3Y are driving elements for switching the high Vt MOS transistors THP3Y and THN3Y, respectively, according to the level of the received test enable signal TE.

The fuse means F1 to Fn are composed of fuse resistors R31 to R3n and NMOS transistors N31 to N3n.
And circuit interruption means. Here, as the NMOS transistors N31 to N3n, transistors having a small gate W / L, that is, transistors having high resistance with little current flow are used. NAND circuit NA4
Is a logic gate for supplying a spare block switching signal SCB composed of a NAND logic signal based on the received outputs of the fuse means F1 to Fn. The switching NMOS transistor SW3Y is connected to the NAND circuit NA.
4 is a switch means for connecting or disconnecting a current path when the spare memory block 235 is used, according to the level of the spare block switching signal SCB received from 4.

Each of the first memory block 232 to the n-th memory block 233 (M1 to Mn) has the same configuration as the spare memory block 235, and is electrically connected by the spare memory block 235 when it is determined to be defective. The memory block to be replaced. First memory block 232 and high Vt NMOS transistor THN31
And a high Vt PMOS transistor THP3
1, a switching NMOS transistor SW31 whose gate is connected to the output of the fuse means F1 is arranged. Similarly, the nth memory block 233 and the high Vt
Between the NMOS transistor THN3n and the high V
t between the PMOS transistor THP3n and the switch N whose gate is connected to the output of the fuse means Fn.
MOS transistor SW3n is arranged. Other memory blocks have the same circuit configuration. The gates of the switching NMOS transistors SW31 to SW3n are connected to the respective inputs of the NAND circuit NA4.

The replacement operation of the memory block by the spare block switching circuit will be described with reference to FIG.

First, the first memory block 232 to the n-th memory block
Of the memory block 233 (M1 to Mn) is normal. In this case, each fuse resistor R3
No processing is performed on 1 to R3n. Therefore, the output from each of the fuse means F1 to Fn is equal to the resistance of the NMOS transistor N which is regarded as a resistor having a large resistance value.
The circuit voltage VCIR is a value obtained by dividing the circuit voltage VCIR by the fuse resistors R31 to R3n and the fuse resistors R31 to R3n. Thereby, the first memory block 232 to the n-th memory block 23
3 (M1 to Mn) NMOS transistors S for switching
Since all of W31 to SW3n are turned on and the output of the NAND circuit NA4, that is, the spare block switching signal SCB becomes "L", the switching NMOS transistor SW3Y of the spare memory block 235 is turned off. Therefore, a current path when the first memory block 232 to the n-th memory block 233 (M1 to Mn) are used is secured, and a current path when the spare memory block 235 is used is cut off. Therefore, each memory block operates.

Next, for example, the first memory block 232
Is determined to be defective. In this case, the circuit block in which the failure has occurred can be specified from the data of the reference current determination memory when the block test result T becomes “H”, and the fuse of the specified first memory block 232 is determined. The resistor R31 is disconnected. The cutting of the fuse resistor R31 is performed by using a means that does not affect the other, such as application of a high voltage, a laser, or the like. As a result, the output from the fuse unit F1 is pulled down to the ground GND by the NMOS transistor N31 regarded as a resistor having a large resistance value and is fixed at “L”, so that the switching NMOS transistor of the first memory block 232 is used. SW31 turns off. On the other hand, the NAND circuit NA4 supplies "H" as the spare block switching signal SCB because the output of the fuse means F1, which is one of the inputs, becomes "L". Thereby, the NMO for switching of the spare memory block 235 is
The S transistor SW3Y turns on. Therefore, the first memory block 2 which is a circuit block in which a defect has occurred
Since the current path when the second memory block 32 is used is interrupted and the current path when the spare memory block 235 is used is secured, the spare memory block 235 operates instead of the first memory block 232. become.

As described above, according to this modification,
Since the memory block determined to be defective by the inspection is replaced with the spare memory block, a semiconductor integrated circuit in which the generated defect is repaired by replacing the memory block is realized.

The switching NMOS transistor SW3 of the spare memory block 235 is output based on the outputs from the plurality of fuse means F1 to Fn using a NAND circuit.
Control Y. Therefore, one spare memory block can be made to correspond to a plurality of memory blocks, and a memory block in which a failure has occurred among the plurality of memory blocks can be replaced with a spare memory block.

Although the memory block has been described, it goes without saying that a corresponding spare circuit block can be provided for other circuit blocks, for example, a logic circuit.

Also, the case where one spare circuit block is provided for n circuit blocks has been described. Alternatively, one spare circuit block may be provided for each circuit block. A plurality of spare circuit blocks may be provided corresponding to the above circuit block. In the latter case, the same circuit block may be provided as a plurality of spare circuit blocks, or a plurality of types of spare circuit blocks composed of the same type of circuit blocks, for example, memory blocks may be provided.

The circuit block may be replaced each time "H" (failure) is output as the block inspection result T in the test of each circuit block, or after all the circuit blocks have been tested. , Register circuit 25
Circuit blocks for which "H" (defective) has been output to 0 may be collectively replaced with spare circuit blocks.

Further, only one or a plurality of circuit blocks which are particularly susceptible to a failure may have a corresponding spare circuit block.

According to the present invention, a low Vt MOS
Using a high Vt MOS transistor provided to turn off the power of a circuit block including transistors,
An inspection target is selected from the circuit blocks. Further, a circuit current flowing through the selected circuit block is detected, and when the detected current exceeds a reference value, the selected circuit block is determined to be defective. As a result, the number of circuit blocks to be inspected at one time is limited without providing new switching means, so that an IDDQ test or the like of a circuit composed of low-Vt MOS transistors can be realized.

Further, since a defective circuit block is replaced with a spare circuit block, a semiconductor integrated circuit which can be repaired and has an improved yield can be obtained without being immediately discarded even if a defect occurs.

Further, since the leak current is determined for each circuit block, a circuit block in which the leak current exceeds a reference value among the circuit blocks is easily specified. Therefore, a semiconductor integrated circuit that can easily perform evaluation, failure analysis, and the like of each circuit block is realized.

The circuit block switching unit 22 is provided on the chip.
Only the circuit boards 0A and 220B and the circuit under test 230 are provided, and the circuit block selection signals S11 to S61 can be supplied from outside the substrate on which the chip is formed using predetermined pads. Further, the detection currents I11 to I11
I61 can also be tested. As a result, an IDDQ test or the like of a circuit composed of low-Vt MOS transistors can be realized without increasing the chip area.

If necessary, block selection data BS in which desired bits are set to “H” is used.
In addition, by setting the reference value to an appropriate value, a plurality of circuit blocks can be inspected simultaneously. Thus, it is only necessary to inspect individual circuit blocks only when it is determined to be defective when the plurality of circuit blocks are inspected simultaneously, so that the number of inspections can be reduced. In addition, inspection can be performed in the same connection state between circuit blocks as in the case of actual use.

It is also possible to provide a test circuit 240 and a block test result T corresponding to each circuit block, and use the register circuit 250 as a parallel input. This makes it possible to increase the number of circuit blocks that can be tested simultaneously.

In the configuration of FIG. 3, the reference current determination memory 242 has only one type of parallel data. However, a memory having a plurality of different parallel data may be provided and selected from the data. . Further, it is also possible to supply parallel data to the reference current generation circuit 243 from outside the substrate on which the chip is formed without providing a memory on the chip.

In the above description, the high V
t PMOS transistors THP11 to THP61 are turned on to secure a normal power supply path, the high Vt NMOS transistors THN11 to THN61 are turned on to secure a power supply path during inspection, and a test enable signal TE and a block selection signal Although S11 to S61 are positive logic, it is needless to say that the present invention is not limited to these. For example, a high Vt PMOS transistor THP11 to THP11 is provided in a current path for supplying the circuit voltage VCIR in each circuit block.
By providing a high Vt PMOS transistor in place of the HP 61 and a high Vt NMOS transistor in place of the high Vt NMOS transistors THN11 to THN61, the current path between the normal time and the test time can be switched.

The configuration of the present invention can be applied not only to disconnection and connection to a power supply circuit but also to access to a circuit block during actual use.
When the semiconductor integrated circuit receives an address of a defective circuit block during actual use, it is necessary to select a spare circuit block instead of the defective circuit block. Here, if there is a defect, the data indicating the defective circuit block is held in the register circuit 250, and the decoded data of the address of the circuit block to be accessed and the holding data indicating the defective circuit block are stored. And compare the data. If the two data match, it indicates that the circuit block to be accessed is defective. Therefore, the circuit is configured in advance so that the spare circuit block is to be accessed instead of the defective circuit block. It is good.

[0057]

As described above, according to the present invention,
High Vt MO provided to turn off the power during standby
A circuit block to be inspected is selected using the S transistor, and a low V is set for each of the selected circuit blocks.
The power supply current of the circuit composed of the t MOS transistors is detected and compared with a reference value to determine pass / fail. As a result, at the time of inspection, the number of circuit blocks to be inspected at one time is limited, and an increase in power supply current due to an abnormality such as leakage of a low Vt MOS transistor can be detected to realize an IDDQ test or the like.

Further, by replacing a circuit block in which a defect has occurred with a spare circuit block, it is possible to repair the defect even if it occurs, so that a semiconductor integrated circuit with an improved yield can be obtained.

Since the leak current is determined for each circuit block, a circuit block in which the leak current exceeds a reference value can be easily specified. Therefore, a semiconductor integrated circuit that can easily perform evaluation, failure analysis, and the like of each circuit block is realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration of a circuit under test and a circuit block switching unit in FIG. 1;

FIG. 3 is a circuit diagram showing a detailed configuration of a test circuit in FIG. 1;

FIG. 4 is a circuit diagram showing a circuit when a reference current value is determined based on an actually measured value.

FIG. 5 is a circuit diagram partially showing a circuit obtained by adding a spare block switching circuit to the circuit of FIG. 2;

[Explanation of symbols]

210 scan register 220A, 220B circuit block switching section 230 circuit under test 231 address buffer 232 first memory block 233 nth memory block 234 timing generator 235 spare memory block (spare circuit block) 240, 340 inspection circuit (inspection means) 241, 341 Reference current determination circuit 242 Reference current determination memory 342 Reference current determination memory (storage means) 250 Register circuit 400 Spare block switching circuit (switching means) F1 to Fn Fuse means ICLK Current determination clock IDET Current determination signal I11 to I61, I3Y detection current / OP operation selection signal QN11 to QN61, TLN, QN3Y Low Vt NM
OS transistor QP11 to QP61, TLP, QP3Y PM with low Vt
OS transistor SCB Spare block switching signal SW31 to SW3n, SW3Y Switching NMOS transistor S11 to S61, S3Y Block selection signal T Block inspection result TE Test enable signal THN11 to THN61 High Vt NMOS transistor (power supply line switching means) THN3Y High Vt NMOS transistors THP11 to THP61 High Vt PMOS transistors (power supply line switching means) THP3Y High Vt PMOS transistors

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-334010 (JP, A) JP-A-8-23277 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01R 31/28-31/3193 H01L 21/822 H01L 27/04 H01L 21/66

Claims (11)

(57) [Claims] MOS transistors each having a first threshold voltage
A circuit under test composed of a plurality of circuit blocks each including a transistor; and a power supply line for each of the plurality of circuit blocks, a current path flowing through the circuit block being a normal current path or
Is a MOS having a second threshold voltage higher than the first threshold voltage for switching to a current path at the time of inspection.
And the power supply line switch means comprising the transistors, the current from the plurality of circuit blocks at the time of inspection
Path to be switched to the current path during inspection
Circuit block selecting means for selecting a circuit block
And at the time of the switched inspection in the desired circuit block
The current flowing through the current path exceeds the predetermined reference value.
If this is the case, it indicates that the circuit block is defective.
A semiconductor integrated circuit comprising: a test unit for generating a constant signal . 2. The semiconductor integrated circuit according to claim 1 , wherein said circuit to be inspected comprises a CMOS circuit. 3. The semiconductor integrated circuit according to claim 1 , wherein said circuit block selecting means generates a block selecting signal for selecting said desired circuit block by sequentially shifting received signals. A semiconductor integrated circuit provided with a scan register for performing the operation. 4. The semiconductor integrated circuit according to claim 1 , wherein said inspection means includes a reference value generation means for previously generating a reference value corresponding to each of said plurality of circuit blocks. Semiconductor integrated circuit. 5. The semiconductor integrated circuit according to claim 4 , wherein said reference value generating means comprises: a voltage dividing means for dividing the received reference voltage into a plurality of voltages; and a voltage divided by said voltage dividing means. One of the
Storage means for holding data for the purpose of selecting the pressure, the reference value according to the voltage selected according to the data
And a means for generating the same . 6. The semiconductor integrated circuit according to claim 4, wherein said reference value generating means is provided for each of said plurality of circuit blocks .
A means for generating a reference value having an accuracy corresponding to ( c). 7. The semiconductor integrated circuit according to claim 4 , wherein said reference value generation means is different from a power supply line for supplying a voltage to said plurality of circuit blocks and is for generating said reference value. A semiconductor integrated circuit comprising: 8. The semiconductor integrated circuit according to claim 7 , wherein: a terminal for supplying a voltage from outside the semiconductor integrated circuit to a power supply line for supplying a voltage to the plurality of circuit blocks; And a terminal for supplying a voltage from outside the semiconductor integrated circuit to a power supply line for generating power. 9. The semiconductor integrated circuit according to claim 1 , wherein said inspection means includes means for simultaneously inspecting a plurality of circuit blocks selected by said circuit block selection means from among said plurality of circuit blocks. And a semiconductor integrated circuit. 10. The semiconductor integrated circuit according to claim 1 , wherein a spare circuit block having the same circuit configuration as at least one of the plurality of circuit blocks, and a circuit block having the same circuit configuration as the spare circuit block. A switching unit for replacing the circuit block with the spare circuit block when a predetermined signal indicating that the signal is defective is generated. 11. The semiconductor integrated circuit according to claim 1 , wherein said inspection means includes a stop means for stopping said inspection when a predetermined signal indicating that said circuit block is defective is generated. A semiconductor integrated circuit further provided.