JPH03293734A - Field effect transistor - Google Patents

Abstract

PURPOSE:To improve performance of an element by forming electrodes on a semiconductor chip and wirings between headers of a thick plating layer reaching from the electrodes on the chip to the rear surface of the chip. CONSTITUTION:A source electrode 2 is connected to the rear surface of a semiconductor substrate 1 via a through hole 5 formed in the substrate 1 by a first plating layer 6. On the other hand, a gate electrode 3, a drain electrode 4 are connected to the side of the substrate 1 reaching the rear surface of the substrate 1 by a second thick plated layer 7 formed on the side of the substrate 1. Accordingly, L (inductance) component of the wirings is reduced, an irregularity therein is simultaneously reduced, and a circuit design is facilitated. Thus, the performance of the element is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor that can reduce inductance components added to input and output electrodes of a peer-hole type semiconductor chip and suppress variations.

"Conventional technology" A field effect transistor (hereinafter referred to as FE'I') is a Schottky barrier gate structure GAAs field effect transistor (hereinafter referred to as GAA8 MES FET) using gallium arsenide (hereinafter referred to as GAAII) as a single crystal semiconductor substrate. An explanation will be given below, taking as an example the case of

Peer hole type GAAI! It is well known that the IMES FET is effective in maintaining high gain in the high frequency region of the X band or higher. This is due to the effect of reducing parasitic inductance (LS) due to the source electrode of the T chip being grounded through the peer hole (through hole), and the effect of reducing thermal resistance due to the thinning of the substrate of the FET chip. This largely depends on the situation. In case 5, even in the case of this type of FET,
Au wire is generally used for wiring between the gate and drain electrodes on the FF and T chips and each electrode terminal on the header or the metallized pattern on the dielectric substrate added on the header. Figure 4 shows the conventional GAA8 MES F of this type.
A cross-sectional view of the IET, Fig. 3 shows the chip structure, Fig. 4 shows the third
In Figure 3, the source electrode is formed in the semiconductor substrate (211, passes through the 9 through holes (c), and is connected to the back surface of the semiconductor substrate Q1) and thickly. It is connected to the carcass. On the other hand, the gate electrode and the drain electrode are placed on the back side of the semiconductor substrate (21).

FIG. 4 shows the assembled state of this flexible FIT chip. The source electrode is grounded to the source electrode terminal of the microwave header (2) through the thick layer (□□□) and solder material formed across the back surface of the chip from the inner part of the through hole. on the other hand,
The gate electrode and drain electrode (2) are connected to the gate electrode terminal (33) through the metallized pattern (32) on the dielectric substrate (31) added to the header (2) using Au@ω.
) or connected to the drain electrode terminal (34).

[Problem to be solved by the invention]

Since conventional FETs were constructed as described above, it was necessary to use core wires (30) for wiring from the gate electrode and drain electrode to each electrode terminal of the header. In this case, variations in the round wire's inductance component or the Au wire length (inductance variations) were factors that inhibited performance.

Furthermore, in cases where the dielectric substrate and metallized pattern added to the header form an impedance matching circuit, such as in a large signal element, this variation in L (inductance) of 5 to 2 becomes a major factor that impedes matching. There was a problem.

This invention was made to solve the above-mentioned problems.
The object of the present invention is to obtain an FET that can reduce components and their variations.

[Means to solve the problem]

The FET according to the present invention has a thick layer filled in a peer hole passing through the semiconductor substrate for a ground electrode (source), and a thick layer on the side of the chip for an input electrode (gate) and an output electrode (drain). A thick wall layer is formed respectively, and the thick layer corresponding to each electrode is directly bonded to each electrode end of the microwave header or to the metallized pattern on the dielectric substrate added to the header. This is what I did.

[Effect]

In the present invention, the thick layer has a Fi5. This is achieved by the thick plating layer.
At the same time, the inductance component due to wiring is reduced, and its variation is also reduced, making circuit design easier.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

Figures 1 and 2 show G^As which is an embodiment of this invention.
A cross-sectional view of a MES FET. Figure 1 shows the chip structure, Figure 2 shows the chip structure.
The figure is an assembly diagram showing the assembled state of the chip in Figure 1. In the figure, the source electrode (2) passes through the through hole (6) formed in the semiconductor substrate (1) and connects to the back surface of the semiconductor substrate (1). They are connected by a first plating layer (6). On the other hand, the gate electrode (8) and the drain (4) electrode are each electrode (8) (4).
The conductor substrate (1) is connected by a second thick layer (7) formed on the side surface of the substrate (1) reaching the back surface. 2 thick layer (7) is required, which can be easily obtained by applying well-known pier hole formation techniques, chip separation techniques, etc.

From a thermal standpoint, the width of the thick layer (6) formed on the back surface of the semiconductor substrate (1) is seen as a problem, but in reality the semiconductor substrate (1) is thinned to several tens of micrometers, so the thickness of the chip Even taking into account the spread of heat flow from the heat generating area on the surface,
FIG. 2 shows a schematic configuration when the chip shown in FIG. 1 is mounted on a microwave header (9), which is not a major problem. In this figure, a dielectric substrate Gυ is added to the electrode σ31 (141) corresponding to the input and output of the header (9), and a metallized pattern (1z) is formed on the surface of the dielectric substrate Gυ, which acts as an impedance matching circuit.

As can be seen from the figure, not only the source electrode (2) but also the gate electrode (8) and drain electrode (4) are formed on the side surface of the semiconductor substrate, and the header (
9) Coupled to each electrode terminal (1311141).

Therefore, the parasitic inductance (inductance) α in the wiring is extremely small, and its variation can also be reduced. In the figure, (8
) is a solder material and αIFi source electrode terminal.

Needless to say, the structure of the microwave header (9) needs to be designed in accordance with the chip shape.

Note that although the above embodiments have been explained using a GAAa MES FET as an example, it goes without saying that the present invention is not limited thereto and can be similarly applied to other device structures.

〔Effect of the invention〕

As described above, according to the present invention, the wiring between each electrode on the semiconductor chip and the header is formed of a thick layer extending from each electrode on the semiconductor chip to the back surface of the chip, so that parasitic inductance (inductance) is generated in the wiring. The components can be made smaller, their variations can be suppressed, and the collector performance can be improved.

[Brief explanation of drawings]

FIGS. 1 and 2 are cross-sectional views showing one embodiment of the FgT of the present invention, and FIGS. 3 and 4 are cross-sectional views of conventional FETs. In the figure, (1) is the semiconductor substrate, (2) is the source electrode, (8) is the gate electrode, (4) is the drain electrode, +6)
is the through hole, (6) is the first thick layer, (γ) is the second thick layer, (8) is the solder material, (9) is the microwave header, and is the source electrode terminal. dielectric substrate, α
2 is a metallized pattern, (13 is a gate electrode terminal, [
I4 indicates a drain electrode terminal. In the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A coupling medium between a semiconductor chip having a plurality of electrodes having different properties and an electrode terminal formed on a microwave header or a dielectric substrate having a desired electrode pattern on the surface added to the header is used in the source electrode section. A via hole and a metal layer filled in the via hole,
A field effect transistor characterized in that the gate and drain electrode portions are sidewall metal layers formed on the side surfaces of the chip.