JPH0329235B2 - - Google Patents

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention generates an electron beam for each division when a screen is vertically divided into a plurality of divisions, and generates an electron beam for each division. This invention relates to a device that displays a television image as a whole by vertically deflecting an electron beam to display a plurality of lines.

(Conventional structure and its problems) Conventionally, cathode ray tubes have been mainly used as display elements for displaying color television images, but conventional cathode ray tubes have a very long depth compared to the screen size. However, it was impossible to create a thin television receiver. In addition, EL display elements, plasma display elements, crystal display elements, etc. have recently been developed as flat display elements.
All of them are insufficient in terms of performance such as brightness, contrast, and color display, and have not yet been put into practical use.

Therefore, in order to achieve a flat display device using electron beams, the present applicant filed a patent application in 1983-
No. 20618 (Japanese Unexamined Patent Publication No. 135590/1983) proposed a new display device.

This method generates an electron beam for each section when the screen is vertically divided into multiple sections, and displays multiple lines by deflecting each electron beam vertically for each section. However, it displays the television image as a whole.

First, a basic configuration example of the image display element used here will be explained with reference to FIG.

This display element is arranged in order from the back to the front.
A rear electrode 1, a line cathode 2 as a beam source, vertical focusing electrodes 3, 3', a vertical deflection electrode 4, a beam flow control electrode 5, a horizontal focusing electrode 6, a horizontal deflection electrode 7, a beam accelerating electrode 8, and a screen 9 are arranged. These are housed in the evacuated interior of a flat glass bulb (not shown). A line cathode 2 serving as a beam source is stretched horizontally so as to generate an electron beam distributed linearly in the horizontal direction, and a plurality of line cathodes 2 (here, Only four (2A to 2D are shown) are provided. In this example, it is assumed that 15 are provided. Let's call them 2i~2yo. These line cathodes 2 are, for example, 10~
It consists of an oxide cathode material for thermionic emission coated on the surface of a 20 μφ tungsten wire. These line cathodes 2I to 2Y are heated so as to generate a thermionic beam when a current is passed through them, and as will be described later, the line cathodes 2
The electron beams are controlled to be emitted sequentially from A to A for a fixed period of time. The back electrode 1 suppresses the generation of electron beams from line cathodes 2 other than the line cathode 2 that is controlled to emit the electron beam for a certain period of time,
It also functions to push out the generated electron beam only in the forward direction. The back electrode 1 may be formed by a coating of a conductive material applied to the inner surface of the rear wall of the glass bulb. Further, instead of the back electrode 1 and the linear cathode 2, a planar electron beam emitting cathode may be used.

The vertical focusing electrode 3 is a conductive plate 11 having a horizontally long slit 10 facing each of the line cathodes 2I to 2Y, and extracts the electron beam emitted from the line cathode 2 through the slit 10, and focus in a direction. An electron beam for one horizontal line (360 pixels) is extracted at the same time. In the figure, only one section in the horizontal direction is shown. The slit 10 may be provided with crosspieces at appropriate intervals in the middle, or may actually be configured as a slit with a row of through holes arranged horizontally at small intervals (nearly touching). may have been done. The vertical focusing electrode 3' is also similar.

A plurality of vertical deflection electrodes 4 are arranged horizontally in the middle of each of the slits 10, and are each composed of conductors 13 and 13' provided on the upper and lower surfaces of an insulating substrate 12. has been done. And the opposing conductors 13, 13'
A vertical deflection voltage is applied between them to deflect the electron beam in the vertical direction. In this example, the electron beam from one line cathode 2 is vertically deflected to positions corresponding to 16 lines by a pair of conductors 13, 13'. The 16 vertical deflection electrodes 4 constitute 15 pairs of conductors corresponding to each of the 15 line cathodes 2, and in the end, the electron beams are drawn so as to draw 240 horizontal lines on the screen 9. to deflect.

Next, the control electrodes 5 each consist of a conductive plate 15 having a long slit 14 in the vertical direction, and a plurality of control electrodes 5 are arranged in parallel in the horizontal direction at predetermined intervals. In this embodiment, 180 conductive plates 15a to 15n for control electrodes are provided (only nine are shown in the figure). Each of the control electrodes 5 separates and extracts the electron beam into two picture elements in the horizontal direction, and controls the amount of electron beam passing therethrough in accordance with a video signal for displaying each picture element. Therefore, the conductive plates 15a to 15n for the control electrode 5 are
With this arrangement, 360 pixels can be displayed per horizontal line. In addition, in order to display images in color, each picture element is displayed using phosphors of three colors, R, G, and B, and each control electrode 5 has two picture elements of R, G, and B. Each video signal is applied sequentially. In addition, 180 conductive plates 15a to 15n for control electrodes 5
180 sets of video signals for one line (two picture elements per set) are simultaneously applied to each of the lines, and one line of video is displayed at one time.

The horizontal focusing electrode 6 is composed of a conductive plate 17 having a plurality of vertically long slits 16 (180 slits 16) facing the slits 14 of the control electrode 5, and collects electrons for each picture element divided in the horizontal direction. Each beam is focused horizontally into a narrow electron beam.

The horizontal deflection electrode 7 is made up of a plurality of conductive plates 18, 18' arranged vertically on both sides of the slit 16, and each electrode 18, 18' has six levels of horizontal deflection. A voltage is applied to horizontally deflect the electron beam for each pixel, and on the screen 9 two sets of R,
The G and B phosphors are sequentially irradiated to emit light. In this example, the deflection range is two picture elements wide for each electron beam.

The accelerating electrode 8 is composed of a plurality of conductive plates 19 provided horizontally at the same position as the vertical deflection electrode 4, and accelerates the electron beam so that it collides with the screen 9 with sufficient energy.

The screen 9 is constructed by coating the back surface of a glass plate 21 with a phosphor 20 that emits light when irradiated with an electron beam, and adding a metal back layer (not shown). The phosphor 20 is arranged for each slit 14 of the control electrode 5, that is, for each horizontally divided electron beam.
Two pairs of phosphors in each of the three colors R, G, and B are provided and are applied in stripes in the vertical direction. In FIG. 1, the broken lines drawn on the screen 9 indicate divisions in the vertical direction that are displayed corresponding to each of the plurality of line cathodes 2, and the two-dot chain lines correspond to each of the plurality of control electrodes 5. Indicates the horizontal division displayed. As shown in the enlarged view in Figure 2, one section partitioned by these two has R, G, and B phosphors 20 for two pixels in the horizontal direction, and 16 lines in the vertical direction. It has a width of
For example, the size of one section is 1 in the horizontal direction.
mm, and the vertical direction is 9 mm.

Note that in FIG. 1, the length in the horizontal direction is greatly enlarged relative to the length in the vertical direction for clarity.

Further, in this example, one control electrode 5, that is, one
R, G, B phosphors 20 for the electron beam of the book
Although only one pair for two picture elements is provided, of course, one picture element or three or more picture elements may be provided, in which case the control electrode 5 has one picture element or three or more pictures R, G, and B video signals are sequentially applied, and horizontal deflection is performed in synchronization with the R, G, and B video signals.

Next, the basic configuration of a drive circuit for displaying television images on this display element will be explained with reference to FIG. First, a driving portion for irradiating the screen 9 with an electron beam to emit raster light will be described.

The power supply circuit 22 is a circuit for applying a predetermined bias voltage (operating voltage) to each electrode of the display element,
-V ₁ to the back electrode 1, and -V 1 to the vertical focusing electrodes 3 and 3'.
DC voltages of V ₃ , V ₃ ', V ₆ to the horizontal focusing electrode 6, V ₈ to the accelerating electrode 8, and V ₉ to the screen 9 are applied.

Next, a composite video signal of a television signal is applied to the input terminal 23, and a synchronization separation circuit 24 separates and extracts a vertical synchronization signal V and a horizontal synchronization signal H.

The vertical deflection drive circuit 40 includes a vertical deflection counter 25, a memory 27 for storing vertical deflection signals, and a digital-to-analog converter 39 (hereinafter referred to as a DA converter). As input pulses to the vertical deflection drive circuit 40, a vertical synchronizing signal V and a horizontal synchronizing signal H shown in FIG. 4 are used. The vertical deflection counter 25 (8 bits) receives the vertical synchronization signal V.
The horizontal synchronizing signal H is counted. This vertical deflection counter 25 counts the effective scanning period (here, a period of 240 hours) excluding the vertical retrace period of the vertical period,
This count output is supplied to an address in memory 27. The memory 27 outputs vertical deflection signal data (here, 10 bits) corresponding to each address, and is converted by the DA converter 39 into vertical deflection signals v and v' shown in FIG. In this circuit 240H
There is a memory address for storing the vertical deflection signal corresponding to each line of minutes, and by storing regular data in the memory every 16H minutes, it is possible to obtain a 16-step vertical deflection signal.

On the other hand, the line cathode drive circuit 26 receives the vertical synchronization signal V
and the output of the vertical deflection counter 25 to create line cathode drive pulses I to Y. FIG. 5a shows the relationship between the vertical synchronizing signal V, the horizontal synchronizing signal H, and the lower five bits of the vertical deflection counter 25. Fifth
FIG. b shows a method of creating line cathode driving pulses 1' to 16' every 16H using these signals. In Figure 5, LSB indicates the lowest bit, and (LSB+1) is
It means the bit one higher than the LSB.

The first line cathode drive pulse I' consists of the vertical synchronizing signal V and the output of the vertical deflection counter 25 (LSB+
4) can be created using an R-S flip-flop, etc., and the line cathode drive pulses LO' to YO' can be created using a shift register, and the line cathode drive pulses LO' to YO' are output from the vertical deflection counter 25 (LSB+3).
It can be obtained by using the inverted version of the clock as a clock and transmitting it. These drive pulses I'~Yo' are inverted and made low potential only during each pulse period, and converted into line cathode drive pulses I~Yo that are at a high potential of about 20 volts during other periods, and each line cathode 2 I~
Added to 2yo.

Each line cathode 2i to 2yo is heated by a current flowing through it during the high potential period of the drive pulses I to YO, and the heated state is maintained so that electrons can be emitted during the low potential period of the drive pulses I to YO. Ru. As a result, electrons are emitted from the 15 line cathodes 2I to 2Y only during the 16H period when low potential drive pulses I to 2Y are applied to each of them. During the period when a high potential is applied, the potential at the line cathode 2 is lower than the potential at the position of the line cathode 2 determined by the bias voltage applied to the back electrode 1 and the vertical focusing electrode 3. Since the applied high potential becomes positive, no electrons are emitted from the line cathodes 2I to 2Y. Thus, in the line cathode 2, electrons are sequentially emitted from the upper line cathode 2a toward the lower line cathode 2y every 16H period during the effective vertical scanning period.

The emitted electrons are pushed forward by the back electrode 1, pass through the opposing slits 10 of the vertical focusing electrode 3, and are focused in the vertical direction to form a flat electron beam.

Next, the relationship between the line cathode drive pulses y to y and the vertical deflection signals v and v' will be explained using FIG. 6. FIG. 6a is a waveform diagram of a line cathode pulse, b is a waveform diagram of a vertical deflection signal, and FIG. 6c is a waveform diagram of a horizontal deflection signal. The vertical deflection signals v and v' in FIG. 6b change in steps of 1H during the 16H period of each line cathode pulse E to Y in FIG. 6A, and change in 16 steps. Vertical deflection signal v and
Both v' and V' have a center voltage of _V4 , and are configured to change in opposite directions so that v increases sequentially and v' decreases sequentially. These vertical deflection signals v and v' are applied to electrodes 13 and 13' of the vertical deflection electrode 4, respectively, and as a result, the electron beams generated from the respective line cathodes 2a to 2o are deflected in 16 steps in the vertical direction. As mentioned above, on the screen 9, one electron beam is deflected so as to sequentially draw a raster line of 16 lines one line at a time from the top.

As a result of the above, an electron beam is emitted for a period of 16 hours from the top of the 15 line cathodes 2A to 2Y, and each electron beam is sequentially emitted for one line from the top to the bottom within 15 sections in the vertical direction. As a result, the electron beam is vertically deflected one line at a time on the screen 9 from the first line at the top end to the 240th line at the bottom end, thereby drawing a raster of 240 lines in total.

The electron beam thus vertically deflected is horizontally deflected by 180 degrees by the control electrode 5 and the horizontal focusing electrode 6.
It is divided into sections and taken out. Figure 1 shows one of these categories. The amount of electron beam passing through each section is controlled by a control electrode 5, and horizontally focused by a horizontal focusing electrode 6 into a single narrow electron beam, which is then controlled by horizontal deflection means described below. The light is then deflected in six steps in the horizontal direction, and is sequentially irradiated onto each of the R, G, and B phosphors 20 for two picture elements on the screen 9. FIG. 2 shows the vertical and horizontal divisions. The phosphors corresponding to each of 15a to 15n of the control electrode 5 are R, G, and B for two picture elements, but for convenience of explanation, one picture element is
Let R ₁ G ₁ , B ₁ be R ₂ , G ₂ , B ₂ .

The horizontal deflection drive circuit 41 includes a horizontal deflection counter (11 bits), a memory 29 storing horizontal deflection signals, and a DA converter 38. As shown in FIG. 7, the input pulses of the horizontal deflection drive circuit 41 are synchronized with the vertical synchronizing signal V and the horizontal synchronizing signal H, and a pulse 6H having a repetition frequency six times that of the horizontal synchronizing signal H is used.

The horizontal deflection counter 28 is reset by the vertical synchronizing signal V and counts the horizontal six times pulse 6H. This horizontal deflection counter 28 is
6 times during 1H, 240H x 6/H = 1440 during 1V
The count output is supplied to an address in the memory 29. Horizontal deflection signal data (here, 8 bits) corresponding to the address is output from the memory 29, and converted by the D-A converter 38 into horizontal deflection signals such as h and h' shown in FIG. . This circuit has memory addresses for storing horizontal deflection signals corresponding to each of 6 x 240 lines, and by storing 6 pieces of regular data for each line in the memory, 6 step waves are generated in 1H period. horizontal deflection signals can be obtained.

This horizontal deflection signal is a pair of horizontal deflection signals h and h' that change in 6 steps as shown in FIG. 7, both have a center voltage of V ₇ , and h gradually decreases.
h' increases in sequence and changes in opposite directions. These horizontal deflection signals h, h' are applied to electrodes 18 and 18' of the horizontal deflection electrode 7, respectively.
As a result, each horizontally divided electron beam is transmitted to the R, G, B,
It is horizontally deflected so that R, G, and B (R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , B ₂ ) phosphors are sequentially irradiated with H/6. Thus, in each line raster, the electron beam is R ₁ ,
Each phosphor 20 of G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ is sequentially irradiated with light.

Therefore, an electron beam is applied to each horizontal section of each line.
A color television image can be displayed on the screen 9 by modulating the video signals R ₁ , G ₁ , B ₁ , R _{2 ,} G ₂ , and B 2 .

Next, the modulation control portion of the electron beam will be explained.

First, the composite video signal applied to the television signal input terminal 23 is applied to the color demodulation circuit 30,
Here, the color difference signals of R-Y and B-Y are demodulated,
The G-Y color difference signals are matrix-synthesized, and further, they are combined with the luminance signal Y to generate R, G,
B primary color signals (hereinafter referred to as R, G, and B video signals) are output. Each of these R, G, and B video signals are processed by 180 sample and hold circuit sets 31a to 3.
Added to 1n. Each sample hold circuit group 3
1a to 31n are for R ₁ , G ₁ , B ₁ , R ₂ respectively
It has six sample-and-hold circuits for G, _G2 , and _B2 . These sample and hold outputs are respectively applied to holding memory sets 32a-32n.

On the other hand, the reference clock oscillator 33 is constituted by a PLL (phase locked loop) circuit, etc., and in this example generates a reference clock 6f _SC that is six times as large as the color subcarrier f _SC and a reference clock 2f _SC that is twice the color subcarrier f SC.
The reference clock is controlled to always have a constant phase with respect to the horizontal synchronizing signal H. The reference clock 2f _SC is added to the deflection pulse generation circuit 42, and a signal 6H which is six times the horizontal synchronizing signal H and signal switching pulses r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , b every H/6 are added. I'm getting ₂ pulses. On the other hand, the reference clock 6f _SC is applied to the sampling pulse generation circuit 34, where it is delayed by one clock period by a shift register, so that the effective horizontal scanning period (approximately 50 μsec) of the horizontal period (63.5 μsec) is delayed. In the meantime, 1080 sampling pulses Ra ₁ to Bn ₂ are sequentially generated, and then one transfer pulse t is generated. These sampling pulses Ra ₁ to Bn ₂ correspond to each picture element when one line of the video to be displayed is divided into 360 picture elements in the horizontal direction, and their positions are always constant with respect to the horizontal synchronization signal H. controlled so that

Six of these 1080 sampling pulses Ra ₁ to Bn ₂ are added to each of the 180 sample and hold circuit sets 31a to 31n, and thereby one line is applied to each sample and hold circuit set 31a to 31n. 2 of each when divided into individuals
Each picture element's R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ video signals are individually sampled and held. The sample-held 180 pairs of R ₁ , G ₁ , B ₁ ,
The video signals of R ₂ , G ₂ , and B ₂ are stored in 180 sets of memories 32a to 32n after completing the sample hold for one line.
are transferred all at once by a transfer pulse t, and are held here for the next one horizontal period. This held
The signals R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ are applied to switching circuits 35a to 35n. The switching circuits 35a to 35n each have R ₁ , G ₁ , B ₁ ,
It is composed of a tri-state or analog gate having individual input terminals for R ₂ , G ₂ , and B ₂ and a common output terminal that sequentially switches and outputs them.

The output of each switching circuit 35a to 35n is
180 sets of pulse width modulation (PWM) circuits 37a to 3
7n, and here, the reference pulse signal is pulse width modulated according to the magnitude of the sampled and held R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , B ₂ video signal and is output. It is desirable that the repetition period of the reference pulse signal is sufficiently smaller than the pulse width of the signal switching pulses r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , b ₂ , for example, 1:10 to 1:10. A ratio of about 1:100 is used.

The output of the pulse width modulation circuits 37a to 37n is used as a control signal for modulating the electron beam to the 180 conductive plates 15a to 15 of the control electrode 5 of the display element.
n separately. Each of the switching circuits 35a to 35n receives a switching pulse r ₁ , which is applied from the switching pulse generation circuit 36.
Switching is controlled simultaneously by g ₁ , b ₁ , r ₂ , g ₂ , and b ₂ . The switching pulse generation circuit 36 generates a signal switching pulse from the deflection pulse generation circuit 42 mentioned above.
It is controlled by r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , b ₂ ,
Each horizontal period is divided into 6 and the switching circuits 35a to 35n are switched by H/6, and R ₁ , G ₁ , B ₁ ,
The switching signals r _{1 ,} g _{1 ,} b ₁ , r ₂ , b _{2 ,} Generate g ₂ .

What should be noted here is that the switching circuit 3
R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , B ₂ in 5a to 35n
video signal supply switching and horizontal deflection drive circuit 4
The irradiation switching horizontal deflection of the electron beams R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , B ₂ to the phosphor according to No. 1 is synchronously controlled so that they completely match both in timing and order. It is that you are. As a result, when the electron beam _R1 is irradiated with the phosphor, the amount of the electron beam is controlled by the _R1 video signal, and the same applies to _G1 , _B1 , _R2 , _G2 , and _B2 . R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , B ₂ of each picture element
The luminescence of each phosphor in R ₁ , G ₁ , B ₁ ,
Each picture element is controlled by the R ₂ , G ₂ , and B ₂ video signals, and each picture element is displayed by emitting light according to the input video signal. Such control is performed simultaneously for 180 sets of one line (2 picture elements each) to display an image of 360 picture elements for one line, and then sequentially for 240 minutes of lines starting from the upper line. One image will be displayed.

The above operations are repeated for each field of the input television signal, and as a result,
The screen 9 is similar to a normal television receiver.
The television footage of the video is shown above.

Note that the terms "horizontal direction" and "vertical direction" in the above explanation refer to the horizontal direction, which is the direction in which line units are displayed when an image is projected, and the vertical direction, which is the direction in which the lines are stacked. It is used in this sense, and is not directly related to the vertical and horizontal directions on the actual screen.

However, in the example device explained above,
The following inconveniences occurred. The first is variation in output level due to variation in capacitance of a capacitor used as an analog memory of a sample-and-hold circuit. The second is the stability of the sampling clock. As long as stability is achieved using a PLL circuit, etc., the cause of clock instability appears in the horizontal expansion and contraction of the image. But PLL
The circuit configuration requires a highly stable reference oscillator such as a crystal oscillator, resulting in an extremely expensive configuration. Therefore, the idea was to use digital memory as a storage device for one horizontal period without causing variations, and furthermore, even if there were some variations in the output level, only the on and off states of the display elements were used to change the brightness at time intervals. It uses a pulse width modulation method that can be controlled and has extremely good uniformity. Furthermore, both the A/D converter clock for digitization and the clock used for pulse width modulation are based on the color subcarrier (f _SC =
By using a signal of an even multiple of 3.58MHz),
It was possible to realize an extremely inexpensive and high-performance receiver without using a new, expensive reference oscillator.

This digitization method consists of a clock generating means that synchronizes with the color subcarrier extracted from the received color television signal and generates a clock signal having a frequency that is an even multiple of the color subcarrier; An A/D converter converts the clock signal from the clock generation means into a digital color signal, a storage means for storing the digital color signal until the next horizontal period, and a memory using the clock signal from the clock generation means. The apparatus includes a pulse width modulation circuit that converts a digital color signal output from the means into a pulse width modulated color signal, and an image display element that displays a color television image using this pulse width converted color signal.

Next, the configuration and operation of an example using this digital memory will be explained with reference to the drawings.

The horizontal deflection, vertical deflection, and line cathode drive are essentially the same as in the case of FIG. 3, but the signal modulation control portion is completely different. A block diagram of this modulation control section is shown in FIG.

The composite video signal is input from the input terminal 50, demodulated by the color demodulation circuit 51, and the color demodulated R,
The three primary color signals of G and B are output lines 53R, 53G, 5
A/D converters 54R, 54 respectively via 3B
G, 54B. This A/D converter 54
R, 54G, 54B may be general-purpose ones, and 6~
Use 8 bits.

A clock for the A/D conversion operation is supplied from a voltage controlled oscillator (VCO) 56 via a frequency divider 55. The frequency of this operating clock is set to 2m times the frequency f _SC of the color subcarrier supplied from the color subcarrier oscillator 57 of the color demodulation circuit 51 (m is a natural number). On the other hand, the transmission output of VCO56 is set to 1/2n (n
is a natural number, n≧m) The output of the frequency divider 58 and the color subcarrier are compared by the phase detector 59, and the control output is supplied to the VCO 56 to oscillate at a frequency of 2nf _SC in synchronization with the color subcarrier. It constitutes a phase-locked loop circuit (PLL circuit).
Here, if m=n=1, 2mf _SC =71.6MHz, and the number of possible data samples for effective video information during one horizontal scanning period is approximately 360.

Therefore, during the effective horizontal scanning period (50 μsec) of one horizontal period, the clock is A/
In addition to the D converters 54R, 54G, 54B, the three primary color signals are each converted into digital three primary color signals of 6 bits each.

The digital three primary color signals output from the A/D converters 54R, 54G, 54B are input in parallel to 180 sets of memories 60a, 60b, . . . 60n for each of R, G, and B. The memories 60a to 60n each consist of a simple data latch circuit that stores 6 bits in parallel for each of R, G, and B, and the latch pulses are sent to the lines 61a to 61 by a shift register 62.
n. This shift register 62
If m=n=1 as mentioned above, it is a 360-stage parallel output shift register, and the clock of mf _SC is supplied from the frequency divider 55 as its clock.
The horizontal synchronization signal, which is a pulse with a width of one clock of the start pulse mf _SC and is output from the synchronization separation circuit 52 to the line 64, is differentiated by the differentiation circuit 65, and the D flip-flop 63 is used to differentiate the horizontal synchronization signal from the synchronization separation circuit 52 to the line 64. An AND gate 66 generates and uses a logical AND output of a suitably delayed signal and the mf _SC clock. In this case, there is generally no need for a particularly large delay, and it is sufficient to pass the signal through one stage of the D flip-flop 63 as shown in FIG.

The differential output of the differential circuit 65 is stored in the memories 60a...6
The data contents of 0n are stored in 180 sets of memories 67a...67
It is also used as a pulse for transferring to n.
These memories 67a...67n are memory 3 in FIG.
Corresponds to 2a to 32n. That is, the memory 60a~
The contents of 60n are stored in memory 6 all at once during the horizontal retrace period.
7a to 67n.

Next, the three primary color digital signals of R, G, and B in the memories 67a to 67b are applied via the line 69 as switching pulses r ₁ ′, g ₁ ′, b ₁ ′, r ₂ ′, g ₂ ′,
It is switched and taken out by b ₂ ′. This switching pulse r ₁ ′, g ₁ ′, b ₁ ′, r ₂ ′, g ₂ ′,
b ₂ ′ is the switching pulse generation circuit 3 in Fig. 3.
Output pulses r ₁ , g ₁ , b ₁ , r ₂ , g ₂ ,
b ₂ (described later).

The switched and selected digital three primary color signals are supplied to 180 sets of pulse width modulation (PWM) circuits 70a, 70b...70n. this
A clock for operating the PWM circuits 70a-70n is supplied from a frequency divider 55 via a line 72. Since this PWM clock 2mf _SC has the same frequency as the A/D conversion clock (nf _SC ) mentioned above, the circuit can be simplified.

Furthermore, if a 2nf _SC clock is used as the PWM clock, the output of the VCO 56 can be used by simply converting the impedance appropriately.

In the example shown in FIG.
Although A/D conversion is performed in the above, the same effect can be obtained by using a configuration in which the composite video signal is directly A/D converted using a clock and then digitally demodulated.

Since the outputs of the PWM circuits 70a-70n are generally at logic level, the control electrodes 15a-15
The signals are amplified by pulse amplifiers 73a to 73n to match the saturation level and cutoff level of n and are output to output terminals 74a to 74n, and these output signals are applied to control electrodes 15a to 15n of the display elements.

Next, the specific circuit configuration and timing of each part are shown in FIGS. 9 to 13. Here, the description will be made assuming that the outputs of the A/D converters 54R, 54G, and 54B are 6 bits. First, Figure 9 shows the memory 60
a ₁ , 60a _{2 .} . . , memories 67a ₁ , 67a _{2 .} . . and switching circuits 68a ₁ , 68a ₂ . Memory 60a ₁ , 60a ₂ ..., 67a ₁ , 67a ₂
are data latch circuits 60aR ₁ , 60aG ₁ , 60aB ₁ . . . , 67aR ₁ , 67 for each bit, respectively.
aG ₁ , 67aB _{1 .} . . and an example thereof is shown in FIG. 10. Here, this circuit is composed of AND gates 75, 76, an inverter 77, and an OR gate 78, and the input signal to the data input terminal D is input only when a high-level data latch pulse is applied to the gate terminal G. It is transmitted to the output terminal Q, and the input state at the negative edge of the data latch pulse to the gate terminal G is latched and outputted to the output terminal Q as a storage output signal.

Latch pulse 61 of memory 60a ₁ , 60a ₂ ...
a, 61b, . . . are the output pulses of the shift register 62 as described above, and are the output pulses of the 180 sets of memories 60a to 60.
0n, two pulses are sequentially input during one horizontal scanning period. As a result, 360 sets of A/D converted digital primary color signals for one horizontal scanning period are stored in the memories 60a, 60b, . . . . memory 60
A corresponds to the leftmost picture element on the screen, and the memory 60n is the rightmost picture element.

The stored contents are output to the data latch output terminal Q in _FIG .
Connected to input terminal D of a ₂ .... Memory 67a ₁ ,
The memory circuit for each bit of 67a ₂ ... is also the 10th
This is a data latch circuit with the same configuration as the figure. The latch pulses of the memories 67a ₁ , 67a _{2 .} . . are data transfer pulses, which are commonly supplied to all terminals. That is, the stored contents of the memories 60a ₁ , 60a ₂ . . . are transferred to the memory 67 all at once by the data transfer pulse.
It will be transferred to a ₁ , 67a ₂ .

The switching circuits 68a ₁ , 68a _{2 .} . . are shown for 6 bits together in FIG. 9, but in reality, one switching circuit is connected in series to the output terminal Q of each bit of the memory 67a ₁ , 67a ₂ . It is connected. A tri-state buffer circuit can be used as the switches 68a ₁ , 68a ₂ . . . . Its control inputs, namely switching pulses r ₁ ′, g ₁ ′,
b ₁ ′, r ₂ ′, g ₂ ′, b ₂ ′ are generated as shown in FIG. That is, the pulses r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , b ₂ are generated by the switching pulse generation circuit 36 in FIG.
This is the output of Switching pulse r ₁ ′, g ₁ ′,
b ₁ ′, r ₂ ′, g ₂ ′, b ₂ ′ are switching pulses r ₁ , g ₁ ,
Positive edges of b ₁ , r ₂ , g ₂ , b ₂ (rising edges)
It is generated by a mono-multi vibrator etc. which is triggered by . As a result, the switching circuits 68a ₁ , 6
_The data selected by 8a _{2 . .} . are supplied to _the PWM _{circuits 70a} .

As shown in FIG. 12, each PWM circuit 70a, 70b, .
It is constituted by an S flip-flop 84. The digital primary color signals for each picture element selected by the switching circuits _{68a 1 ,} 68a ₂ .
Data is preset by applying b ₁ ', r ₂ ', g ₂ ', b ₂ ' to the load terminal of counter 79 via OR gate 85'. Then, the f _SC clock from the frequency divider 55 is counted by the counter 79,
By its carry output, the flip-flop 84
Set. Therefore, the larger the digital primary color signal, the earlier the set point becomes. On the other hand, as shown in FIG. 13, the D-flip-flop 86 is driven by switching pulses r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , b ₂ and a 2mf _SC clock.
r ₁ , 86g ₁ , 86b ₁ , 86r ₂ , 86g ₂ , 86b ₂ and
NOR gate 87r ₁ , 87g ₁ , 87b ₁ , 87r ₂ , 8
7g ₂ , 87b ₂ and AND gates 88r ₁ , 88g ₁ ,
A reset pulse generation circuit composed of 88b ₁ , 88r ₂ , 88g ₂ , 88b ₂ and an OR gate 89 generates switching pulses r ₁ , g ₁ , b ₁ , r ₂ , g ₂ ,
A reset pulse Re is generated at each negative edge of _b2 to reset the flip-flop 84.

As a result, in the PWM circuit shown in FIG. 12, the trailing edges of the output pulses from the output terminals Q and Q are the negative edges of each of the switching pulses r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , and b _{2 .} The output pulses, which are fixed and whose leading edges are pulse width-converted so that they vary according to the magnitude of each of the three digital primary color signals, are output as digital red signals, digital green signals, and digital signals during approximately 50 μsec during one horizontal period. A green signal, a digital red signal, a digital green signal, and a digital green signal are output in this order. The maximum pulse width of each output signal is approximately 8 μsec (=1/f _SC ×64 bits).

In this way, the PWM circuits 70a to 70n output PWM output signals that have been converted to a pulse width corresponding to the magnitude of the digital three primary color signals, and are amplified to a predetermined level by the pulse amplifiers 73a to 73n. By adding the electron beams to the control electrodes 15a to 15n of the display element as shown in FIG. 1, it is possible to control the amount of electron beams irradiated to the phosphors of each color on the screen 9, thereby displaying a color television image. be able to.

FIG. 14 shows the relationship between the horizontal deflection signals h, h' and the PWM output signal. FIG. 14a shows the dynamic operating state. b is PWM when the input signal is black
Indicates an output signal, and the level is low (L).

c is PWM when the input signal is slightly brighter than black
The output signal is shown, and d is when the input signal is white.
Shows PWM output signal. In such devices, white balance adjustment is done using A/D, similar to the conventional CRT white balance adjustment method.
The color temperature of highlights and lowlights is adjusted by changing the amplitude and DC level of the R, G, and B primary color signals applied to the inputs of the converters 54R, 54G, and 54B. FIG. 15 shows the A/D converter 54
The input/output characteristics of the A/D converter are shown when 100% of the operating ranges of R, 54G, and 54B are used. In practice, the color temperature of highlights and lowlights is adjusted by changing the amplitude and DC level of the R, G, and B three primary color signals applied to the inputs of the A/D converters 54R, 54G, and 54B. The result will be as shown in the figure. In order to adjust the color temperature of the highlight to a predetermined color temperature (for example, 9300〓), assume that the white level for red lights is adjusted to V1, the white level for green lights is adjusted to V2, and the white level for blue lights is adjusted to V3. . When adjusting the white balance using this adjustment method, the three primary color signals have different resolutions, so there are problems such as noticeable quantization noise depending on the signal and color temperature changing depending on the signal level. . On the other hand, the above problem can be solved by using an A/D converter with extremely high resolution, but it has the disadvantage of being expensive.

(Objective of the Invention) The present invention solves the above problems, and provides an image display device that can arbitrarily select the color temperature for highlights and lowlights, and also prevents increase in quantization noise caused by signals. The purpose is to

(Structure of the Invention) In the image display device of the present invention, a sawtooth voltage is generated in synchronization with the red, green, and blue outputs of the PWM output signal, and is applied to the vertical focusing electrode to display each of the low lights and highlights. The color temperature of lowlights and highlights can be adjusted to any value by controlling the amount of electron beam passing through.

(Description of Embodiment) Hereinafter, the structure and operation of an embodiment of the present invention will be described with reference to FIGS. 17 to 21. This image display device is essentially the same as those shown in FIGS. 3 and 8 in terms of horizontal deflection, vertical deflection, line cathode drive, and signal modulation control, but the color of highlights and low lights is There are completely different ways to adjust the temperature. FIG. 17 shows an overall circuit diagram of the present invention. Input terminal 10
0 to 102 are the switching pulses r ₁ , g ₁ , of the switching pulse generation circuit 36 shown in FIG.
b ₁ , r ₂ , g ₂ , b ₂ as r ₁ and r ₂ , g ₁ and g ₂ , b ₁ and b ₂ as shown in FIG. 18 created through OR gates
r ₁ , r ₂ , g ₁ , g ₂ and b ₁ , b ₂ are applied, respectively.
Pulses (r ₁ , r ₂ ), (g ₁ , g ₂ ), and (b ₁ , b ₂ ) are applied to sawtooth wave generation circuits 103R, 103G, and 103B. Volume 104R, 104G, 104
B is for adjusting the color temperature of highlights, and volumes 105R, 105G, and 105B are for adjusting the color temperature of lowlights.
The details will be described later. Sawtooth wave generation circuit 103
The outputs of R, 103G, and 103B are impedance-converted by emitter followers 106, 107, and 108, and then sent to analog switches 109, 110, and 103B.
11 input terminal in. On the other hand, pulses (r ₁ , r ₂ ), (g ₁ , g ₂ ), and (b ₁ , b ₂ ) are applied to the control terminal C of the analog switch, and at each timing, the analog switch 1
09, 110, and 111 are turned on, and the outputs of the sawtooth wave generating circuits 103R, 103G, and 103B are supplied to the output terminals OUT of the analog switches 109, 110, and 111, and are made into the desired amplitude DC level by the amplifier circuit 112. , are supplied to the vertical focusing electrode 3. Block 140 adjusts the level of red highlights and lowlights. Block 141 adjusts the green highlight and block 142 blue highlight and low light levels. Next, the adjustment of highlights and lowlights will be explained in detail using FIG. 19. In FIG. 19a, periods r ₁ and r ₂ are red signal periods, r ₁ is from t ₁ to _{t 2} and r ₂ is from t ₄ to _{t 5} . In the period from _t1 to _t2 , the _t1 side means white and the _t2 side means black. In Figure 19a, by controlling the voltage applied to the vertical focusing electrode 3 at time _t1 , the red light emission output of the highlight can be controlled. On the other hand, t ₂
By controlling the voltage applied to the vertical focusing electrode 3 at the point in time, the red light emission output of the low lights can be controlled. The same can be said for the period t ₄ to _{t 5} of r ₂ . Also, the green signal periods g ₁ (t ₂ to _{t 3} ), g ₂ (t ₅
~ _t6 ), the same can be said for the blue signal periods _b1 ( _t3 ~ _t4 ), _b2 ( _t6 ~ _t7 ), and the highlights and lowlights of red, green, and blue, respectively. The light output can be controlled and can be adjusted to any color temperature. Figure 20 shows the sawtooth wave generation circuit 1 of Figure 17.
10 in the specific circuit diagram of 03R, 103G, 103B
3R, 103G, and 103B are completely the same circuits and have the same functions. In FIG. 20, (r ₁ , r ₂ ), (g ₁ , g ₂ ), and (b ₁ , b ₂ ) are input to the input terminal 120, respectively. For example, the red sawtooth wave generation circuit 103R will be explained using FIG. 21. resistance 12
1,122,126,129,130,132,
Volume 124, transistors 123, 125,
127, 131, diode 128, t ₁ and t ₄
In the circuit that determines the voltage to be applied to the vertical focusing electrode 3 at the time of , the transistors 123 and 127 are turned off while the level of r ₁ and r ₂ is L,
A voltage E ₁₃₃ divided by the resistor 122 and the potentiometer 124 is supplied through the transistor 125 . When the volume 124 is increased, E ₁₃₃ ′ is obtained, and when the volume 124 is decreased, the voltage obtained is E ₁₃₃ ″, and the voltage at time t ₁ and t ₄ can be controlled _. , r ₂ operates as a current source only when the level is L. The transistor 125
is an emitter follower whose load is the current source 131. Further, while the level of r ₁ r ₂ is L, the transistor 135 is turned off and the transistors 140,
141 and 143 are turned off. Next, the H period at the r ₁ and r ₂ levels will be explained. During the H period, transistors 123 and 127 are on, transistors 125 and 131 are off, and they have no effect. On the other hand, transistor 135 is turned on, transistors 140, 141, and 143 operate, and capacitor 133 is charged or discharged. By setting the volume 139, the base voltage of the transistor 140 is lowered by the transistor 141.
As the base voltage of increases, the current I ₁₄₃ becomes the current I ₁₄₀
becomes larger, and as shown by the solid line b, the capacitor 133 is charged, and a positive sawtooth wave is generated. If the voltage of volume 139 is further increased,
The current I ₁₄₃ becomes even larger than the current I ₁₄₀ , and b
as shown by the dotted line. On the other hand, if the base voltage of the transistor 141 is lower than the base voltage of the transistor 140 due to the setting of the volume 139,
The current I ₁₄₀ becomes larger than the current I ₁₄₃ , and as shown by the solid line c, the capacitor 133 is discharged and a negative sawtooth wave is generated. transistor 1
When the base voltage of 41 is further lowered, the discharge current increases, as shown by the dotted line c. In this way, by changing the volume 139 and controlling the base voltage of the transistor 141, the polarity and amplitude of the sawtooth wave can be changed without changing the voltage E ₁₃₃ at times t ₁ and t ₄ , and the polarity and amplitude of the sawtooth wave can be changed at times t ₂ and t 4 . The voltage at t ₅ can be adjusted arbitrarily. In this way, the same function can be used for green and blue, and by controlling the red, green, and blue light emission outputs during highlight and lowlight respectively, the color temperature during highlight and lowlight can be set arbitrarily. can be adjusted to

In the above embodiment, the method of controlling the vertical focusing electrode 3 has been described, but the same effect can be achieved by controlling the emission potential of the back electrode 1 or the line cathode 2 as an electron beam generation source using the same means. Obtainable.

The effects of the present invention are great in a system that uses digital memory for signal memory as shown in Figure 8, and can be similarly obtained in a system that uses sample and hold for signal memory as shown in Figure 3. Can be done.

(Effects of the Invention) As described above, according to the present invention, the color temperature in highlights and lowlights can be adjusted to any value, and when digital memory is used as a signal memory, quantization An image display device that can prevent an increase in noise and deterioration of color temperature tracking due to brightness can be obtained.

[Brief explanation of the drawing]

Fig. 1 is an exploded perspective view showing an example of an image display element used in the image display device of the present invention, Fig. 2 is an enlarged view of the fluorescent surface of the image display element, and Fig. 3 is a drive of the image display element. 4 and 5 are block diagrams of drive rotation devised prior to the present invention in order to
Figures 6 and 7 are waveform diagrams of various parts to explain the operation of the drive circuit, Figure 8 is a conventional example in which digital memory is used for the signal modulation control part, and Figure 9 is the memory. 10 is a detailed circuit diagram of the memory section and switch section.
The circuit diagram for bits, Figure 11 is its timing diagram, Figure 12 is the circuit diagram of the PWM circuit, Figure 13 is the circuit diagram of the PWM circuit.
The figure shows the circuit diagram of the PWM reset pulse generation circuit, Figure 14 shows the relationship between the horizontal deflection signal and the PWM output signal, Figure 15 shows the input/output characteristics of the A/D converter, and Figure 16 shows the conventional device. Fig. 17 is a circuit diagram of an embodiment of the present invention, Fig. 18 is a switching pulse used in the embodiment, and Fig. 19 is an operation of the embodiment. An explanatory diagram, FIG. 20 is a sawtooth wave generation circuit used in the same embodiment, and FIG. 21 is an operation explanatory diagram of the sawtooth wave generation circuit used in the same embodiment. 2, 2 I to 2 Y... Line cathode, 4... Vertical deflection electrode, 5... Beam flow control electrode, 7... Horizontal deflection electrode, 9... Screen, 10... Slit, 20
... Fluorescent body, 23 ... Input terminal, 24 ... Synchronization separation circuit, 25 ... Vertical deflection counter, 26 ...
...Line cathode drive circuit, 27...Memory, 28...Horizontal deflection counter, 29...Memory, 30,5
1...Color demodulation circuit, 31a-31n...Sample hold circuit, 32a-32n, 60a-60
n, 67a to 67n...Memory, 33...Reference clock oscillator, 34...Sampling pulse generation circuit, 35s to 35n, 68a to 68n...Switching circuit, 36...Switching pulse generation circuit, 37a to 37n, 70a ~70n...
PWM circuit, 38...D/A converter, 39...
D/A converter, 40... Vertical deflection drive circuit, 41
... Horizontal deflection drive circuit, 42 ... Deflection pulse generation circuit, 44 I to 44 Y ... Switching circuit,
54R, 54G, 54B...A/D converter, 10
3R, 103G, 103B... Sawtooth wave generation circuit, 106, 107, 108... Emitter follower transistor, 109, 110, 111... Analog switch, 112... Amplification circuit.

Claims (1)

[Scope of Claims] 1. A line cathode as an electron beam generation source, which is stretched horizontally and arranged vertically at predetermined intervals; a vertical focusing electrode that vertically focuses the electron beam emitted in the forward direction; a vertical deflection electrode that vertically deflects the electron beam that has passed through the vertical focusing electrode; control electrodes for extracting the electron beam by dividing it horizontally into each pixel and controlling the amount of the electron beam passing in accordance with a video signal for displaying each pixel; a horizontal focusing electrode that focuses electron beams for each picture element in the horizontal direction; a horizontal deflection electrode that sequentially irradiates multiple color phosphors on a screen in a time-sharing manner; an accelerating electrode that accelerates the electron beam that has passed through the horizontal deflection electrode so as to increase its energy; and an accelerated electron beam. a display element consisting of a screen coated with phosphors of a plurality of colors that emit light when irradiated with the phosphor; a memory means for holding video signals of a plurality of colors sampled for each picture element; switching means for extracting a video signal from the memory means in synchronization with the irradiation of the plurality of color phosphors with an electron beam; and pulsing a reference signal in accordance with the magnitude of the video signal output from the switching means. a sawtooth wave generation circuit that applies the output of the pulse width modulation means to the control electrode and generates a sawtooth wave in synchronization with the pulse width modulation period for each color; and an amplifier for amplifying the wave and applying it to the vertical focusing electrode, and controlling the color temperature during highlights and lowlights of the image by changing the amplitude and DC level of the sawtooth wave. Device.