JPH03291058A - High efficiency encoding device - Google Patents

Abstract

PURPOSE:To keep picture quality in an excellent way by applying block processing and orthogonal transformation to a picture signal for each picture element, quantizing the result and deciding a quantization step depending on a difference of a picture signals between adjacent picture elements among plural sub blocks resulting from each block. CONSTITUTION:Each block of a picture signal outputted from a block processing circuit 1 is divided further into plural sub blocks and a discrimination reference arithmetic section 13 obtains a discrimination reference value from sum of absolute values of difference of picture signals between adjacent picture elements in each sub block. A discriminator 14 decides a quantization step of an adaptive quantization device 12 quantizing a transformation coefficients obtained from an orthogonal transformation circuit 11 in response to the discrimination reference value. Moreover, an adaptive weighting device is provided in place of the quantizer 12 to decide a waiting coefficients for the transformation coefficients as an alternate embodiment. Thus, a decoder keeps excellent picture quality even to a picture of a flat part in which deterioration in the picture quality is often eminent.

Description

[Detailed description of the invention]

[0001]

[Industrial application field]

[000
2]

[Conventional technology]

FIG. 34 shows, for example, IEEE Transactions
on Consumer Electronics,
Vol, 34. No. 3 (AUGUSUT, 1
988) (7) ”AN EXPERIMENTAL
DIGITAL VCRWITH40MM DRUM
, 5INGLE ACTUATORAND DCT-B
ASED BIT-RATE REDLJCTION
1 is a block diagram showing the configuration of a conventional high-efficiency encoding device shown in 1. In the figure, 1 is a blocking circuit that divides an input digital image into a plurality of blocks; , the image signal of each block is DC
Output to T circuit 2. The DCT circuit 2 performs Dis for each block of the image signal output from the blocking circuit 1.
CRETE Co51ne Transform (hereinafter abbreviated as DCT) is applied, and the transform coefficients are output to the quantizer 3. The quantizer 3 holds a plurality of quantization tables with different quantization steps, selects and quantizes the optimal quantization table according to the transform coefficients within a block, and sends the quantized transform coefficients to a variable length encoder. Output to 4. The variable length encoder 4 performs variable length encoding on the quantized transform coefficients and outputs the variable length encoded transform coefficients to the buffer memory 5 . The buffer memory 5 converts the variable length encoded image signal at a fixed rate and stores the converted image signal. The controller 6 selects the quantization parameters of the quantizer 3 and the transform coefficients to be encoded by the variable length encoder 4 so that the buffer memory 5 does not overflow. [0003] Next, specific operations will be described. The input digital image signal consists of, for example, a luminance signal and two color difference signals, and these signals are time-division multiplexed in a blocking circuit 1, divided into blocks of, for example, 8 pixels x 8 lines, and output to a DCT circuit 2. be done. The DCT circuit 2 converts the image signal of each block into X(i, j)
When expressed as (i, j=o, 1...7), horizontal 8-point DCT is performed using the following equation. [0004]

[0005] The converted image signals f (0, j), f (m, j) are subjected to vertical 8-point DCT according to the following equation, and the image signals are converted into transform coefficients F (m , n) (m, n=0.1°・
. . , 7) and output to the quantizer 3. [0006]

[0007] The obtained transform coefficient is quantized in the quantizer 3 according to a quantization step selected based on the content of the transform coefficient and the quantization parameter from the controller 6. A coarse quantization step is selected when the contents of the transform coefficients represent an image with a high contrast rising edge, and a fine quantization step is selected when the contents represent an image with a detail portion of /JN amplitude. Ru. [0008] The quantized transform coefficients are variable-length encoded in the variable-length encoder 4 and then stored in the buffer memory 5. The amount of data stored in the buffer memory 5 is detected by a controller 6 to prevent the buffer memory 5 from overflowing. The controller 6 selects a quantization parameter according to the amount of data stored in the buffer memory 5 and outputs it to the quantizer 3, and also encodes it in the variable length encoder 4 according to the amount of data. The selected transform coefficients are output to the variable length encoder 4. The data stored in the buffer memory 5 is then read out at a fixed rate. [0009] FIG. 35 is a block diagram showing the configuration of another conventional high-efficiency encoding device disclosed, for example, in the above-mentioned literature. In the figure, parts given the same numbers as those in FIG. 34 indicate the same parts, so a description thereof will be omitted. In this example, a weighting device 7 that weights the transform coefficients obtained by the DCT circuit 2 is provided between the blocking circuit 1 and the quantizer 3. The quantizer 3 quantizes each weighted transform coefficient. [0010] Next, the operation will be explained. Similarly to the above example, the image signal of each block divided by the blocking circuit 1 is subjected to 8-point DCT in the horizontal and vertical directions in the DCT circuit 2, and transform coefficients F (m, n) is output to the weighting device 7. Each transform coefficient from the DCT circuit 2 is weighted by a weighting device 7. Specifically, when the result of DCT calculation for each block of 8 pixels x 8 lines is divided into four regions as shown in FIG. A weighting coefficient W (
m, n) (see FIG. 37).

[0012] The weighted transform coefficients are output to the quantizer 3. Quantizer 3 from now on. The operations in the buffer memory 5 and controller 6 are the same as those shown in FIG. 34, so their explanation will be omitted. [0013]

[Problem to be solved by the invention]

Although the conventional high-efficiency encoding device is configured as described above, there are problems with the selection of quantization steps and the configuration of the weighting device as described below. [0014] A quantization step is selected in the quantizer 3 according to the AC power E obtained from the conversion coefficient F (m, n) by the following equation. [0015]

[0016] When the value of this AC power E is small, it is quantized in fine steps, and when E is large, it is quantized in coarse steps. In other words, for an image with high contrast lines in a flat area, which is a flat background with small amplitude changes and small changes in the data image signal, the image block will be coarsely quantized, but the decoder side When inverse DCT is applied to the block, the quantization error spreads over the entire block, and noise is superimposed even on the flat part. Since noise in such flat areas is visually very noticeable, there is a problem in that it greatly deteriorates image quality. [0017] Furthermore, in order to weight transform coefficients of a block size of 8×8, for example, 82=64 types of multipliers are required, and there is a problem that the size of the weighting device is large. [0018] The present invention was made to solve such problems, and it is possible to quantize image signals so that good image quality can be maintained on the decoder side even in flat areas where image quality deterioration is easily noticeable. Another object of the present invention is to provide a highly efficient encoding device that can perform image signal compression with less noticeable deterioration in image quality using a small number of multipliers. [0019]

[Means to solve the problem]

A high-efficiency encoding device according to a first aspect of the present application includes blocking means for dividing a digital image signal into blocks for each of a plurality of pixels;
orthogonal transformation means for performing orthogonal transformation on the blocked image signal; quantization means for quantizing the transform coefficients obtained by the orthogonal transformation; A means for dividing into sub-blocks and calculating a judgment reference value from the sum of the absolute values of image signal differences between adjacent pixels in each sub-block, and a quantization step when the quantization means quantizes the judgment reference value. and means for determining based on. [0020] The high-efficiency encoding device of the second invention of the present application includes blocking means for dividing a digital image signal into blocks for each of a plurality of pixels;
A plurality of orthogonal transform means perform orthogonal transform on the blocked image signal, a weighting means perform weighting on the transform coefficients obtained by the orthogonal transform, and a plurality of blocks of the image signal output from the blocking means. means for dividing into sub-blocks and determining a determination reference value from the sum of absolute values of image signal differences between adjacent pixels in each sub-block; and means for determining a weighting coefficient in the weighting means based on the determination reference value. It is characterized by comprising: [0021] A high-efficiency encoding device according to a third aspect of the present application includes blocking means for dividing a digital image signal into blocks for each of a plurality of pixels;
orthogonal transformation means for performing orthogonal transformation on the blocked image signal; quantization means for quantizing the transform coefficients obtained by the orthogonal transformation; Means for dividing the image signal into sub-blocks and determining the maximum and minimum values of the image signal of the pixels in each sub-block, and the quantization step when the quantization means performs quantization based on the maximum value and the maximum tJ) value. and means for determining. [0022] A high-efficiency encoding device according to a fourth aspect of the present application includes blocking means for dividing a digital image signal into blocks for each of a plurality of pixels;
A plurality of orthogonal transform means perform orthogonal transform on the blocked image signal, a weighting means perform weighting on the transform coefficients obtained by the orthogonal transform, and a plurality of blocks of the image signal output from the blocking means. and means for determining the maximum and minimum values of the image signal of the pixels in each sub-block, and means for determining the weighting coefficient in the weighting means based on the maximum and minimum values. Features. [0023] A high-efficiency encoding device according to a fifth aspect of the present application includes blocking means for dividing a digital image signal into blocks for each of a plurality of pixels;
orthogonal transform means that performs orthogonal transform on each divided block; and weighting means that has fewer function units than the number of pixels in each block and that performs weighting on transform coefficients obtained by the orthogonal transform. The method is characterized by comprising means for variable length encoding the weighted transform coefficients. [0024] Blocking means for dimensional blocking, orthogonal transformation means for performing orthogonal transformation in units of three-dimensional blocks on the blocked image signal, and quantization means for quantizing transform coefficients obtained by the orthogonal transformation. and means for further dividing each block of the image signal output from the blocking means into a plurality of sub-blocks and determining a determination reference value from the sum of absolute values of differences in image signals between adjacent pixels in each sub-block. ,
The method is characterized by comprising means for determining a quantization step when the quantization means performs quantization based on the determination reference value. [0025] The high-efficiency encoding device according to the seventh invention of the present application includes a blocking means for three-dimensionally blocking a digital image signal for each of a plurality of pixels; orthogonal transform means for performing orthogonal transform; weighting means for weighting transform coefficients obtained by orthogonal transform; and blocking means for further dividing each block of the image signal output into a plurality of sub-blocks and It is characterized by comprising means for determining a determination reference value from the sum of absolute values of image signal differences between adjacent pixels in a block, and means for determining a weighting coefficient in the weighting means based on this determination reference value. [0026] The high-efficiency encoding device of the eighth invention of the present application includes a blocking means for three-dimensionally blocking a digital image signal for each of a plurality of pixels, and a blocking means for three-dimensionally blocking a digital image signal for each of a plurality of pixels; orthogonal transformation means for performing orthogonal transformation, quantization means for quantizing transform coefficients obtained by orthogonal transformation, and blocking means for further dividing each block of the image signal outputted into a plurality of subblocks, and dividing each block into a plurality of subblocks. means for determining the maximum value and minimum value of the image signal of the pixel within;
The method is characterized by comprising means for determining a quantization step when the quantization means performs quantization based on the maximum value and the minimum value. [0027] The high-efficiency encoding device of the ninth invention of the present application includes a blocking means for three-dimensionally blocking a digital image signal for each of a plurality of pixels; orthogonal transform means for performing orthogonal transform; weighting means for weighting transform coefficients obtained by orthogonal transform; and blocking means for further dividing each block of the image signal output into a plurality of sub-blocks and It is characterized by comprising means for determining the maximum and minimum values of image signals of pixels within a block, and means for determining weighting coefficients in the weighting means based on the maximum and minimum values. [0028] The high-efficiency encoding device of the tenth invention of the present application includes blocking means for three-dimensionally blocking a digital image signal for each of a plurality of pixels, and a three-dimensional block unit for each blocked block. orthogonal transformation means that performs orthogonal transformation; weighting means that has fewer multipliers than the number of pixels included in a two-dimensional plane in each block; and weighting means that performs weighting on transform coefficients obtained by orthogonal transformation; and means for variable length encoding the transformed transform coefficients. [0029]

[Effect]

In the high-efficiency encoding device of the L3, 6.8 invention, the blocked digital image signal is further divided into sub-blocks, and the reference judgment value is determined according to the image signal of the pixel in each sub-block. is calculated, the image state is determined based on this determination value, and an appropriate quantization step is selected. For each block, it is detected whether there is a flat part where image quality deterioration is noticeable, or whether the image is prone to quantization errors on the decoder side. quantization at a high rate with a low compression ratio in image parts where image quality deterioration is noticeable. In this way, it is possible to output an image signal in which noise is not noticeable even in flat areas. [0030] In the high efficiency encoding device of the 2.4 and 7.9 inventions,
The blocked digital image signal is further divided into sub-blocks, a reference judgment value is calculated according to the image signal of the pixel in each sub-block, the image condition is judged based on this judgment value, and appropriate weighting is performed. Select coefficients. Is there a flat area in each block where image quality deterioration is more noticeable?
Alternatively, the decoder side detects whether the image is prone to quantization errors, performs weighting at a low rate with a high compression rate for image parts where image quality deterioration is not noticeable, and lowers the compression rate for image parts where image quality deterioration is more noticeable. Do small, high-rate waits. In this way, it is possible to output an image signal in which noise is not noticeable even in flat areas. [0003] In the high-efficiency encoding device of the 5th and 10th inventions, weighting is applied to the transform coefficients using a weighting means having a smaller number of multipliers than the number of pixels in each block. Specifically, weighting is performed using weighting coefficients suitable for the horizontal sequence order and the vertical sequence order within each block. In this way, weighting can be performed using N2/4 or less multipliers within each block of size NXN, for example. [0032]

【Example】

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof. [0033] In FIG. 1 showing the configuration of the first embodiment of the present invention, 1, 4
．． 5 is a blocking circuit that divides an input digital image into a plurality of blocks, a variable length encoder that variable length encodes the output of the adaptive quantizer 12, and a buffer memory that stores the output of the variable length encoder 4. These are equivalent to those shown in the conventional example of FIG. 34 or 35. In addition to these, the first embodiment includes an orthogonal transform circuit 11 that performs orthogonal transform on each block of the image signal from the blocking circuit 1, and an adaptive quantization for the transform coefficients from the orthogonal transform circuit 11. An adaptive quantizer 12 having a plurality of quantization tables, and a first and second judgment that further divides each block divided in the blocking circuit 1 into a plurality of sub-blocks and serve as criteria for selecting a quantization table. A determination reference value calculation unit 13 that calculates and outputs a reference value, and a determiner 14 that selects a quantization table based on the output from the determination reference value calculation unit 13 and outputs its contents to the adaptive quantizer 12.
and a controller 15 that controls selection of quantization steps so that the buffer memory 5 does not overflow. Note that the quantization table may be a uniform quantizer with a fixed step width or a nonlinear quantizer with an uneven step width. [0034] As shown in FIG. 2, the determination reference value calculation unit 13 includes a sub-blocking circuit 21 that divides each block of the image signal output from the blocking circuit 1 into, for example, four sub-blocks.
and four arithmetic units 22, 23, 24, and 25 that calculate the sum of absolute values of image signal differences between horizontally and vertically adjacent pixels in each subblock, and outputs of the four arithmetic units. a maximum lJ1 value detector 26 that detects the minimum value A of;
A maximum value detector 27 detects the maximum value B of the outputs of the four arithmetic units, and a minimum value detector 2 detects the output B of the maximum value detector 27.
and a subtracter 28 for subtracting the output A of 6. The determination reference value calculation unit 13 uses the output A of the minimum value detector 26 as the first determination reference value and the output C of the subtractor 28 (=B−A
) is output to the determiner 14 as the second determination reference value. [0035] Next, the operation will be explained. The digital image signals (luminance signal and two color difference signals or RGB signals) input to the blocking circuit 1 are time-division multiplexed in the blocking circuit 1 and are divided into blocks, for example, 8 pixels x 8 lines. be done. Each block of the divided image signal is output to the orthogonal transform circuit 11 and the determination reference value calculation section 13. The orthogonal transform circuit 11 performs Discrete Cosine Transform on the image signal.
An orthogonal transformation such as m(D CT ) is performed. The transform coefficients output from the orthogonal transform circuit 11 are sent to the adaptive quantizer 12.
Output to. [0036] In the determination reference value calculation unit 13, as shown in FIG.
Each block of 8 pixels x 8 lines output from the blocking circuit 1 is divided into 4 sub-blocks y of 4 pixels x 4 lines.
,yy,y. Here, each subblock y1. y2. y3. The image signals of y41 2' 3 4 are respectively y (i, j) and y (i, j)
y3 (i, j), y (il
2 4j) (i
, j=1.2, 3.4). Arithmetic unit 22.23.2
4.25 sub-block y1. y2. y3. Each image signal of y4 is inputted. The computing unit 22 computes the sum v1 of the absolute values of differences in image signals between horizontally and vertically adjacent pixels in the subblock y1 for the subblock y1 as shown in the following equation. [0037]

[Math 5] [0038] Operates like an expression. [0039]

[0040] It is output to the determiner 14 as the first determination reference value for redundancy, and is also output to the subtracter 28. On the other hand, maximum value detector 2
7c, arithmetic unit 22.23.24.25 (7) output v1.
V2. v3. Maximum value of V4 B = MAX (vl, V2.v
3. v4) is detected and output to the subtracter 28. Subtractor 2
8 calculates the difference C by calculating B−A, and outputs the subtracted value C to the determiner 14 as a second determination reference value for selecting a quantization step. [0041] The first judgment reference value A is for detecting a flat part of the image, and if this first judgment reference value A is small, there is a flat part in the block where image quality deterioration is easily noticeable on the decoder side. Show that. On the other hand, the second judgment standard value C is for detecting changes in the image, and the larger the second judgment standard value C is, the larger the change in the image in that block is, and the more quantization error occurs on the decoder side. Show that it is easy. [0042] The determiner 14 determines the first . Depending on the second determination reference values A and C, a quantization step is selected when the adaptive quantizer 12 quantizes the transform coefficient. The adaptive quantizer 12 holds quantization tables with different quantization steps, such as a high rate quantization table, a medium rate quantization table, and a low rate quantization table. A high rate quantization table is a quantization table with a fine quantization step, a medium rate quantization table is a quantization table with a medium quantization step,
A low rate quantization table is a quantization table with coarse quantization steps. The determiner 14 selects the first . Depending on the second determination reference values A and C, the optimum quantization table is selected from these three quantization tables based on FIG. 4 or FIG. 5. If the first determination reference value A is small, the block has a flat portion where image quality deterioration is easily noticeable, so a high rate or medium rate quantization table is selected. In addition, if the second judgment criterion value C is large, the image changes greatly within the block and quantization errors are likely to occur on the decoder side, so a high-rate quantization table with fine quantization steps is used. Select. [0043] The operation of the determiner 14 will be specifically explained. Here, to simplify the explanation, we will use the sum V (n=1.2, 3°4
), the average variation amount M = V /24 will be used. n [0044] FIG. 6(a) is a block with a single diagonal line in a high contrast on a flat background. This block is
Since the image is an image in which quantization noise is spread over flat parts and deterioration is easily noticeable on the decoder side, it is sufficient to quantize it using a high-rate quantization table. The average variation amount within each subblock in this block is M1=2, M=2
．． M3=10. M4=33. The criterion value in this case is A/24. C/24 is respectively A/24=MIN (Ml, M2.M3.M4'r =
2C/24=MAX (M,, M2.M3.M4) −
MIN (Ml, M2.M3.M4) = 31,
In the determination diagram of FIG. 7, since it is located at point α, the determiner 14 selects a high rate quantization table. [0045] FIG. 6(b) is a block with edges that do not have very high contrast on a flat background. This block cannot be used with a low-rate quantization table because it has flat parts, but since the contrast is not very high, the quantization error on the decoder side is small, so it is quantized with a medium-rate quantization table. It is fine if it is done. The average amount of variation within each subblock in this block is M1=2
2M2=3, M3=14. M4=I5. The criterion value in this case is A/24. C/24 is respectively A/24=
2, C/24=13, and is located at point β in the determination diagram of FIG. 7, so the determiner 14 selects the medium rate quantization table. [0046] FIG. 6(C) is a block with large contrast changes throughout. Since the quantization error of this block is less noticeable on the decoder side, it is sufficient to quantize it using a low-rate quantization table to increase the compression rate. The average variation amount within each subblock in this block is M1=289M2=30
1M3=241M4=16. The criterion value in this case is A/24. C/24 is A/24=16, C/24, respectively.
24=14 and is located at point 7 in the determination diagram of FIG. 7, so the determiner 14 selects a low rate quantization table. [0047] By the way, the selection criteria for the quantization step, that is, the occupancy rates of the three quantization tables are different in FIGS. determined by The controller 15 senses the amount of data stored in the buffer memory 5, and has the role of adjusting the rate at which the transform coefficients are quantized in the adaptive quantizer 12 so that the buffer memory 5 does not overflow. fulfill. That is, when there is sufficient storage capacity in the buffer memory 5, the controller 15 selects a high-rate quantization table at a high rate based on the selection criteria shown in the determination diagram of FIG. Let it be,
On the other hand, when the buffer memory 5 is close to being saturated, the selection criteria as shown in the determination diagram of FIG. 5 is used to increase the rate of selection of low-rate quantization tables. In this way, the controller 15 adjusts the rate at which the conversion coefficients are output to the buffer memory 5. [0048] According to the selection result of the determiner 140 as described above, the adaptive quantizer 12 selects an appropriate quantization step for each block, quantizes the transform coefficients output from the orthogonal transform circuit 11, and quantizes the selected quantizer. The conversion step and the quantized transform coefficients are output to the variable length encoder 4. The variable-length coded transform coefficients are stored in the buffer memory 5, then read out at a fixed rate and sent to the outside. [0049] In the above embodiment, the first . The second criteria values A and C were obtained, but especially when processing is performed within one field in interlaced scanning, the distance between adjacent pixels in the vertical direction is large, so it is difficult to detect a flat part. As for the first determination reference value for , the difference in image signals between adjacent pixels only in the horizontal direction may be used. [0050] FIG. 8 shows the configuration of the determination reference value calculation section 13 in such a modified example. Arithmetic unit 31, 32, 33, 34 that calculates the sum of absolute values of image signal differences between adjacent pixels in this judgment direction
and a minimum value detector 35 that detects the minimum value from among the values obtained in each arithmetic unit 31, 32, 33, and 34, and a minimum value detector 35 that detects the minimum value from among the values obtained in each of the arithmetic units 31, 32, 33, and 34, and a Arithmetic unit 36.37.38 for calculating the sum of absolute values.
39 and an adder 60 that adds the outputs of the arithmetic units 31 and 36.
and an adder 61 that adds the outputs of the arithmetic units 32 and 37,
The minimum value is detected from the outputs of the adder 62 that adds the outputs of the arithmetic units 33 and 38, the adder 63 that adds the outputs of the arithmetic units 34 and 39, and each of the adders 60, 61, 62, and 63. Minimum value detector 26 and each adder 60°61, 62.6
3, and a subtracter 28 that subtracts the output of the minimum value detector 26 from the output of the maximum value detector 27. [0051] Next, the operation will be explained. Sub-blocking circuit 21
The four sub-blocks y1. y2. y3.
The image signals of y4 are respectively y1 (i, j) y2
(i, j), y (i, j), y4 (i, j)
(i, j=1.2, 3.4). Arithmetic unit 31.32
．． 33. Subblock y1.34. y2. y3. y4 are respectively input. The arithmetic unit 31 calculates the sum V of the absolute values of differences in image signals between horizontally adjacent pixels in the sub-block y1.
Calculate h□ as shown below. [0052]

[0053] Similarly, the other arithmetic units 32, 33, and 34 perform subblocks y2. y3. The sum Vh2''h3''h4 of the absolute values of differences in image signals between horizontally adjacent pixels in y4 is calculated as shown in the following equation. [0054]

[Equation 8] [0055] Minimum value detector 35c, arithmetic unit 31, 32, 33, 34 (
7) Output Vhl” h2- vh3” Minimum value A of h4
= M engineering N (vhl, Vh2.vh3.vh4) is detected and output. The minimum value Ah is output to the determiner 14 as a first determination reference value for selecting a quantization step in the adaptive quantizer 12. [0056] On the other hand, sub-blocks y1. y2. y3. y4 are respectively input. Arithmetic unit 36
calculates the sum VV1 of the absolute values of differences in image signals between vertically adjacent pixels in the sub-block y1 as shown in the following equation. [0057]

[0058] Similarly, the other arithmetic units 37, 38, and 39 perform subblocks y2. y3. The summation vv2"v3"v4 of the absolute values of differences in image signals between vertically adjacent pixels in y4 is calculated as shown in the following equation. [0059]

[Equation 101 [0060] Calculated. Similarly, V (
=■h2+Vv3), V3 (=Vh3) is detected and output to the subtracter 28. Further, the maximum value detector 27 outputs to the subtracter 28 through adders 60, 61, and 62. Subtractor 2
8 calculates and outputs the difference C between the maximum value B and the minimum value A. This subtraction value C is the second value for selecting the quantization step.
is output to the determiner 14 as a determination reference value. [0061] Note that the subsequent operations are similar to those in the above-described embodiment, so
The explanation will be omitted. [0062] Next, a second embodiment of the present invention will be described. [0063] In the first embodiment described above, the subtraction value C obtained by subtracting the minimum value A from the maximum value B was used as the second criterion value for selecting the quantization step. Instead to,
The maximum value B may be adopted. In the first embodiment, the maximum value B is the minimum value A, similar to the second example. [0064] In FIG. 9 showing the configuration of the second embodiment, 1. 4. 5
．． 11, 12, 14, and 15 are respectively a blocking circuit, a variable length encoder, a buffer memory, an orthogonal transform circuit, an adaptive quantizer judger, and a controller, which are equivalent to those shown in Fig. 1. Therefore, the explanation will be omitted here. Further, 16 is a determination reference value calculating section in the second embodiment whose configuration is shown in FIG. The configuration of the determination reference value calculation unit 16 is different from that of the determination reference value calculation unit 13 shown in FIG.
The difference is that the subtracter 28 is removed, and the determination reference value calculation unit 16 uses the sub-blocks y1. y2. y3. The sum of absolute values of image signal differences between adjacent pixels in the horizontal and vertical directions in y4 v1. v2. v3. The minimum value A of v4,
, large value B are detected, and the minimum value A and the maximum value are outputted to the determiner 14 as first and second determination reference values for determining the quantization step. [0065] Next, the operation will be explained. The determiner 14 determines the first . According to the second judgment reference values A and B,
The adaptive quantizer 12 selects a quantization step for quantizing the transform coefficients based on FIG. 11 or FIG. 12. Here, as an example of an image block as shown in FIG.
The operation of the determiner 14 will be specifically explained based on the determination diagram in FIG. The average variation amount within each subblock is M1=2.
M2=2. In FIG. 6(a) where M3=10° and M4=33, A/24=2. Since B/24=33 and is located at point α in the determination diagram of FIG. 13, the determiner 14 selects a high rate quantization table. Furthermore, the average variation amount within each subblock is M = 2. M=3. 14 on M3.
In Fig. 6(b) where M4 is 15, A/24=2
, B/24=15, and is located at point β in the determination diagram of FIG. 13, so the determiner 14 selects the medium rate quantization table. The average amount of variation within each subblock is M1=2
8. M2=30. M3=24. Figure 6 where M4=16 (
In C), A/24=16 and B/24=30, which is located at point 7 in the determination diagram of FIG. 13, so the determiner 14 selects a low-rate quantization table. [0066] Note that the other operations are the same as those in the first embodiment described above, so a description thereof will be omitted. Further, as in the first embodiment, especially when processing is performed within one field in interlaced scanning, since the distance between adjacent pixels in the vertical direction is large, the first As for the determination reference value, it is sufficient to use only the difference in image signals between adjacent pixels in the horizontal direction. FIG. 14 shows the configuration of the determination reference value calculation unit 18 in such a modified example. In FIG. 14,
The same numbers as in FIG. 8 indicate the same parts. This judgment reference value calculation unit 18 calculates the total sum V (n=1
．． The minimum value Ah of 2, 3.4) is output as the first n determination reference value to the determiner 14, and the sum V of the absolute values of the differences in image signals between vertically adjacent pixels in each sub-block is The maximum value B of the added value Vnn with the total sum vhn of absolute values is outputted to the determiner 14 as a second determination reference value. [0067] Next, a third embodiment of the present invention will be described. [0068] In the third embodiment, the criteria for selecting the quantization steps in the adaptive quantizer 12 are different. In FIG. 15 showing the configuration of the third embodiment, 1. 4. 5.11.12.15
are a blocking circuit, a variable length encoder, a buffer memory, an orthogonal transform circuit, an adaptive quantizer, and a controller, respectively, and since these are equivalent to those shown in FIG. 1, their explanation will be omitted here. . Further, 17 is a determiner that divides one block into a plurality of subblocks and selects a quantization step in the adaptive quantizer 12 based on the minimum value and maximum value in the dynamic range of each subblock. be. As shown in FIG. 16, the determiner 17 includes a subblocking circuit 21 that divides each block output from the blocking circuit 1 into four subblocks, and a dynamic range (minimum and maximum value) of each subblock. ), a minimum value detector 45 that detects the minimum value of the output from the dynamic range detector 41.42.43.44, and a dynamic range detector 41.42. A maximum value detector 46 detects the maximum value of the output from .43.44, and a subtractor 47 subtracts the output of the minimum value detector 45 from the output of the maximum value detector 46.
and a control signal generator 48 that outputs a control signal for selecting a quantization step to the adaptive quantizer 12 based on the output from the minimum value detector 45 and the output from the subtracter 47. [0069] Next, the operation will be explained. As in the first embodiment, the image signal divided into 8 pixels x 8 lines by the blocking circuit 1 is further processed by the sub-blocking circuit 21 into four sub-blocks y1. y2.
y3. It is divided into y4. Here, each subblock y,
The image signals of yyy are respectively y1 (i, j)1
2'3' 4 y (i, j), y3 (i, j) y4 (
i, j) (i, j=1.2, 3.4). Dynamic range detectors 41, 42, 43, 44 are connected to sub-blocks y1. y2. Depending on the image signals of y3 and y4, the dynamic range of each sub-block DR1, DR2°DR
3. Calculate and output DR4 as shown below. [00701 DR=MAX (yl (i, j): i, j=1.2
,3.4)-MIN(yl(i,j); i,j=
1.2, 3.4) DR=MAX (y2 (i, j):
i, j=1.2, 3.4)-MIN (y2 (i,
j): i, J=1.2, 3.4) DR=MAX (y
3 (i, j): i, j = 1.2, 3.4) - MIN
(y3 (i, j): 1.j=1.2,3.4)D
R=MAX (y4 (i, j): i, j=1.2,
3.4)-MIN (y4 (i, j): i, j=1
．． 2, 3.4) [00713 The minimum value detector 45 is the dynamic range detector 41.
The minimum value D=MIN (DRl, DR2, DR3, DR4) of the outputs DR1 and DRDRDR of 42, 43, and 44 is detected and output to the 2' 3= 4 subtracter 47 and the control signal generator 48. on the other hand,
The maximum value detector 46 is a dynamic range detector 41 .
42.43.44 output DR1, DR2, DR3, DR
Maximum value of 4 E = MAX (DRl, DR2, DR3, DR
4) is detected and output to the subtracter 47. The minimum value and the maximum value E are subtracted by a subtracter 47 to obtain F=E−D,
The subtraction value F is output to the control signal generator 48. [0072] If the output of the minimum value detector 45 is small, there is a flat part in that block where image quality deterioration is easily noticeable on the decoder side.
In this case high or medium rate quantization is required. On the other hand, if the output F of the subtracter 47 is large, it indicates that the image changes within the block are large and quantization errors are likely to occur on the decoder side. Therefore, if the output F is small and the output F is large, the rate is quantization is required. [0073] The control signal generator 48 outputs the adaptive quantizer 12 based on FIG. 17 or 18 according to F (=ED).
outputs a control signal for selecting the optimal quantization step to the adaptive quantizer 12. Here, the operation of the determiner 17 (control signal generator 48) will be specifically explained based on the determination diagram of FIG. 19 using an image block as shown in FIG. 6 as an example. [0074] In FIG. 6(a), in an example of an image signal in which the dynamic range in each sub-block is quantized to 8 bits, DR1=9. DR2=8. DR3=78,
DR4=114. In this case, glue, F (=E-D)
are respectively D=MIN (DRl, DR2, DR3, DR
4) =8F=MAX(DRl, DR2, DR3, DR
4)-MIN (DRl, DR2, DR3, DR4)
=106 and is located at point α in the determination diagram of FIG. 19, so the determiner 17 selects a high rate quantization table. Also, the dynamic range within each sub-block is D
R1=8, DR2=7. DR3=64. In FIG. 6(b) where DR4=57, D=7. F=57, and Figure 19
Since it is located at the β point in the decision diagram, the decider 17 selects the medium rate quantization Q pull. Since the dynamic range within each sub-block is DR1=61°66, which is located at point 7 in the determination diagram of FIG. 19, the determiner 17 selects a low rate quantization table. [0075] [0076] Next, a fourth embodiment of the present invention will be described. [0077] In FIG. 20 showing the fourth embodiment of the present invention, 1.4.
5.11.13.15 are respectively a blocking circuit, a variable length encoder, a buffer memory, an orthogonal transform circuit, a judgment reference value calculating section, and a controller, which are equivalent to those shown in FIG. It is something. Further, 18 is an adaptive weighting device that applies adaptive weighting to the transform coefficients output from the orthogonal transform circuit 11, and 19 is a judgment reference value calculation unit 1.
This is a decision device that selects a weighting coefficient in the adaptive weighting device 18 based on the output from the adaptive weighting device 3. Note that the determination reference value calculation section 13 has an internal configuration shown in FIG. 2. [0078] Next, the operation will be explained. [0079] Similar to the first embodiment described above, the maximum value A and the subtraction value C calculated by the determination reference value calculation unit 13 are calculated by the first . It is input to the determiner 19 as a second determination reference value. The determiner 19 uses this first . Depending on the second determination reference values A and C, a weighting coefficient to be used in the adaptive weighting device 18 is selected based on FIG. 4 or FIG. here,
For example, the adaptive weighting device 18 holds weighting coefficients for the following three types of rates. [0080] [Equation 11] W, (m, n) = 1 (m, 11=:Q, L 2t .... [0081] Wl (m, n) is a high rate weighting coefficient, W
2 (m, n) is the weighting coefficient of the medium rate, W3
Let (m, n) be called low rate weighting coefficients, respectively. If the first determination reference value A is small, the block has a flat portion where image quality deterioration is more noticeable on the decoder side, so high-rate or medium-rate weighting is applied. Furthermore, if the second criterion value C is large, the image of that block changes greatly within the block, and quantization errors are likely to occur on the decoder side, so if A is small and C is large, the effect of high spatial frequency cannot be ignored, so a high rate of weighting is applied. [0082] Here, the operation of the determiner 19 will be specifically explained using an image block as shown in FIG. 6 as an example. Note that here, the criteria for selecting high rate, medium rate, and low rate are the same criteria as in the first embodiment (FIG. 7). Figure 6 (
In a), high rate weighting is applied. In the determination diagram of FIG. 7, since it is located at point α, the determiner 19 selects the high rate weighting coefficient W1 (m, n). In Figure 6(b), where there are edges with low contrast on a flat background, low-rate weighting cannot be used because there are flat parts, but since the contrast is not very high, the quantization error on the decoder side is small, so a medium rate weighting is applied. In the determination diagram of FIG. 7, since it is located at point β, the determiner 19 selects the weighting coefficient W2 (rnn) of the middle rate. In FIG. 6C, where contrast changes are large over the entire image, the quantization error is less noticeable, so it is possible to increase the compression ratio by weighting at a low rate. In the determination diagram of FIG. 7, since it is located at the γ point, the determiner 19 selects the low rate weighting coefficient W3 (m, n). [0083] According to the selection result of the determiner 19 as described above, the adaptive weighting unit 18 selects an appropriate weighting coefficient for each block, weights the transform coefficients output from the orthogonal transform circuit 11, and calculates the weighting for each block. The coefficients and the weighted transform coefficients are output to the variable length encoder 4. The output of the adaptive weighting device 18 is variable length encoded by the variable length encoder 4 and stored in the buffer memory 5. Data stored in buffer memory 5 is read out at a fixed rate. [0084] By the way, the controller 15 senses the amount of data stored in the buffer memory 5 and controls the selection of weighting coefficients so that the buffer memory 5 does not overflow. That is, when there is sufficient storage capacity in the buffer memory 5, the selection criteria as shown in the judgment diagram of FIG. 4 is used to increase the proportion of high-rate weighting coefficients selected; When the buffer memory 5 is close to saturation, the selection criteria shown in the determination diagram of FIG. 5 is used to increase the proportion of low-rate weighting coefficients selected. [0085] Also in this fourth embodiment, as in the first embodiment, the distance between adjacent pixels in the vertical direction is large, especially when processing is performed within one field in interlaced scanning. Therefore, for the first determination reference value for detecting a flat portion, it is sufficient to use only the difference in image signals between adjacent pixels in the horizontal direction. In such a case, the configuration of the determination reference value calculation section 13 may be configured as shown in FIG. [0086] Next, a fifth embodiment of the present invention will be described. [0087] In the fourth embodiment described above, the subtraction value C was adopted as the second criterion value for selecting the weighting coefficient, but instead of this, the maximum value B may be adopted. . The fifth example is an example in which the maximum value B is adopted as the second determination reference value in the fourth example. Note that the first determination reference value is the minimum value A, as in the fourth embodiment. In FIG. 21 showing the configuration of the fifth embodiment, 1.4. 5.11.
15, 18, and 19 are a blocking circuit, a variable-length encoder, a buffer memory, an orthogonal transform circuit, a controller, an adaptive weighting device, and a determiner, respectively, which are equivalent to those shown in FIG. It is. Further, 16 is a determination reference value calculating section equivalent to the second embodiment whose configuration is shown in FIG. In the fifth embodiment, the criteria for selecting the weighting coefficients in the fourth embodiment are the same as in the second embodiment. Therefore, the operation of this fifth embodiment is similar to that of the second embodiment. Since it can be easily understood by appropriately referring to the fourth embodiment, its explanation will be omitted. [0088] Next, a sixth embodiment of the present invention will be described. [0089] The sixth embodiment is an example in which the criteria for selecting weighting coefficients in the adaptive weighting unit 18 in the fourth embodiment are the same as those in the third embodiment described above. In FIG. 22 showing the configuration of the sixth embodiment, 1. 4. 5.11.1
5.18 are respectively a blocking circuit, a variable length encoder, a buffer memory, an orthogonal transform circuit, a controller, and an adaptive weighting device, which are equivalent to those shown in FIG. 20, and Reference numeral 20 designates a determiner similar to the determiner 17 of the third embodiment whose configuration is shown in FIG. This sixth
The operation of the embodiment is described in Section 3. Since it can be easily understood by appropriately referring to the fourth embodiment, its explanation will be omitted. [0090] Note that in each of the above embodiments, one block is divided into four sub-blocks, but it is not necessary to divide it into four.
The number of sub-blocks may be arbitrarily determined depending on the size of one block, etc. [0091] In addition, we decided to use two types of criterion values when selecting the quantization step or weighting coefficient, but the two
It is not necessary that there are different types, and n types (n≧1) of determination reference values may be used. When n=1, for example, the sum of the absolute values of image signal differences between adjacent pixels in the horizontal and vertical directions in a sub-block is used as the determination reference value, and the quantization step or weighting is performed based on this determination reference value. It is also possible to select a coefficient. [0092] Next, a seventh embodiment of the present invention will be described. [0093] In FIG. 23 illustrating the configuration of the seventh embodiment, the high-efficiency encoding device performs a high-efficiency encoding process on the blocking circuit 1, the orthogonal transform circuit 11, and the transform coefficients output from the orthogonal transform circuit 11. It has a weighting device 51 that performs variable length encoding, and a variable length encoder 4 that performs variable length encoding. Waiting device 51
As shown in FIG. 24, it includes a zigzag scanning circuit 52 that scans pixels in a block in a zigzag manner, a weighting table 53 that stores a plurality of weighting coefficients, and a multiplier 54 that multiplies a conversion coefficient by a weighting coefficient. and has. [0094] Next, the operation will be explained. The input digital image signals are time-division multiplexed in the blocking circuit 1 and are divided into blocks for each plurality of pixels. Each block output from the blocking circuit 1 is subjected to orthogonal transformation such as DCT transformation in an orthogonal transformation circuit 11. The transform coefficients output from the orthogonal transform circuit 11 are transmitted to the weighting device 5.
Weighting is performed by 1. The output of the weighting unit 51 is variable-length encoded by the variable-length encoder 4. [0095] The operation of the weighting device 51 will be described in detail below. For example, the blocking circuit 1 generates a block of 8 pixels x 8 lines (image signal x (i, j) (i, j=0.1...
7)), the orthogonal transform circuit 11 outputs 8×8 transform coefficients F (m, n) (m, n=o, 1...
, 7) is output. Here, the conversion coefficients are rearranged into a one-dimensional data string by a zigzag scanning circuit 52 having zigzag scanning characteristics as shown in FIG. 25, and the zigzag scanning circuit 52 sends the conversion coefficients F ( m, n). Furthermore, the zigzag scanning circuit 52 outputs zigzag scanning address information for each data string to the weighting table 53. The weighting table 53 is accessed by this address information, and the weighting table 53 is accessed by the zigzag scanning circuit 52.
The weighting coefficient W for the output data of the multiplier 5
Output to 4. [0096] Here, the weighting coefficient is determined by, for example, eight types of multipliers as shown in FIG. Maximum value M=M with order n of
AX (m, n) (m, n=0.1..., 7)
It is expressed by the following formula using . [0097]

[0098] The conversion coefficient F (m, n) output from the zigzag scanning circuit 52 and the weighting coefficient W (M) output from the weighting table 53 are input to the multiplier 54 and are expressed as follows. The conversion coefficients are weighted as follows. [0099]

[Formula 13] F' (m, n)=F (m, n)XW (M) [0
1003 To more specifically illustrate the operation of the weighting device 51, a certain 4:2 signal quantized to 8 bits at 13.5 MHz
:2 component digital image data (information amount is 1
66Mbps). 64 DCT transform coefficients F obtained by performing DCT transform on a block of 8 pixels x 8 lines
When a weighting of α=0.6 is used for (m, n), the weighted DCT transform coefficient F
' (m, n) was run-length encoded using a bitmap table as shown in FIG. 27, and the amount of information was calculated. As a result, the image data was 54.7 Mbps. In the decoding system, as shown in FIG. 28, DCT transform coefficients F' (m, n
) is decoded by the decoder 55, and further, the inverse weighting unit 56 calculates the weighting coefficient W as shown below.
Multiply F' (m, n) by the reciprocal of (M) to F'' (
m, n). [0101]

[Formula 14] F" (m, n)=F' (m, n)X1/W (M
) [0102] Further, in the inverse DCT circuit 57, an inverse D is applied to F″ (m, n).
A reconstructed image X1(i,j) is obtained by performing CT. here,
Defining the SN ratio within one block for the reproduced image Xi (1, j) as follows, in the case of the sample image mentioned above, the SN ratio is 43.5 dB for the Y signal and 44 dB for the R-Y signal.
．． 6 dB, and B-Y was 45.0 dB. [0103]

[0104] On the other hand, in conventional weighting, when α=0.7, the information amount is 54.8 Mbps, the S/N ratio is 43.5 dB for the Y signal, 44.6 dB for the R-Y signal, and 44.6 dB for the B- Y is 45.
0 dB, and the same result as in the example of the present invention is obtained. However, in conventional weighting, 64 types of weighting units are required. [0105] In the above embodiment, the weighting device is composed of eight types of weighting coefficients depending on the maximum values of the order of the sequence in the horizontal and vertical directions, but it is not necessarily the case that the weighting coefficient is the maximum value of the order of the sequence in the horizontal and vertical directions. It is not necessary to select the weighting coefficients according to the zigzag scanning order shown in FIG. 25. [0106] In this case, since zigzag scanning repeats scanning in a diagonal direction, the weighting coefficients are summed by making this diagonal scanning the minimum range and selecting the same weighting coefficient within this scanning range. Eight types of weighting coefficients are prepared. For example, the coefficient W(s) may be used for weighting the DCT transform coefficient F (m, n). [0107]

[Formula 16] As shown in Figure 29, the following weighting S = 0 (m + n = 0) s = 1 (m + n
=1) s=2 (m+n=2) s=3 (m
+n=3)s=4 (4≦m 10n≦5) s=5
(6≦m+n≦7) s=6 (8≦m+n≦9)
5=7 (10≦m 10n≦14) [0108] Although eight types of weighting coefficients were used in the above embodiment, it is not necessarily necessary to use eight types of weighting coefficients, and up to 15 types of weighting coefficients can be used. For example, for weighting in the case of 15 types, as shown in FIG.
The following weighting coefficient W(s) may be used. [0109]

[Formula 17] [01101 In the above embodiment, weighting was considered within a two-dimensional plane, but it is not necessarily necessary to consider within a two-dimensional plane. The above weighting can be applied.

As mentioned above, in the seventh embodiment, a high-efficiency code that has an information compression rate equivalent to a high-efficiency encoding device using a weighting device for NXN blocks and is easy to implement in hardware is used. A device is obtained. [0112] By the way, in each of the above-mentioned embodiments, the case where the image signal output from the blocking circuit is made up of 8 pixels x 8 lines as one block has been described, but such two-dimensional blocks (horizontal and The present invention can be applied not only to three-dimensional blocks (horizontal, vertical, and temporal directions), but also to three-dimensional blocks (horizontal, vertical, and time directions). An example in which the present invention is applied to a three-dimensional block will be described below. [0113] An example of such a three-dimensional block corresponding to the first example described above will be described. In FIG. 31 showing the configuration of this embodiment, 1a is a blocking circuit that divides an input digital image into a plurality of three-dimensional blocks so that one block has 8 pixels x 8 lines x 8 fields. lla is an orthogonal transform circuit that performs three-dimensional DCT transform on each block from the blocking circuit 1a;
Reference numeral 3a denotes a determination reference value calculation unit that further divides each block divided by the blocking circuit 1a into a plurality of subblocks, and calculates and outputs a determination reference value for the quantization step. Note that the other configurations are the same as in the first embodiment, so the same parts are given the same numbers and their explanation will be omitted. [0114] As shown in FIG. 32, the determination reference value calculation unit 13a divides each block output from the blocking circuit 1a into 32 blocks, for example.
A subblocking circuit 21a divides the image into subblocks (one subblock is 4 pixels x 4 lines), and calculates the sum of the absolute values of the differences in image signals between horizontally and vertically adjacent pixels in each subblock. A calculation unit 22a to obtain, a minimum value detector 26a that detects the minimum value A1 of 32 values successively output from the calculation unit 22a, and
A maximum value detector 27a detects the maximum value B1 of the values, and a minimum value detector 26 detects the output B1 of the maximum value detector 27a.
and a subtracter 28a that subtracts the output A1 of a. From the determination reference value calculation unit 13a, the output A of the minimum value detector 26a
1 is outputted to the determiner 14 as the first determination reference value, and the output C (=B1-A1) of the subtracter 28a is outputted as the second determination reference value. [0115] Next, the operation will be explained. The digital image signal input to the blocking circuit 1a is divided into one block of 8 pixels x 8 lines x 8 fields. Each divided block is output to the orthogonal transform circuit 11a and the determination reference value calculation section 13a. Judgment reference value calculation unit 13
In the sub-blocking circuit 21a in a, as shown in FIG.
Each block of lines x 8 fields is divided into 4 subblocks of 4 pixels x 4 lines per field, making a total of 32 subblocks. Here, the image signals of each sub-block are respectively y (i, j) (i, j=i,
2, 3.4), the arithmetic unit 22a calculates, for each sub-block, the pixels between adjacent pixels in the horizontal and vertical directions within the sub-block [0116] [Equation 18] [0117] Minimum value detector 26a is the 32 values successively output from the arithmetic unit 22a, that is, the 3 values forming the - block.
Minimum value A1 of the value of V for each of the two subblocks
is detected, and this minimum value A1 is output to the determiner 14 as a first determination reference value for selecting a quantization step, and is also output to the subtracter 28a. On the other hand, the maximum value detector 27a detects the maximum value B1 of the 32 values of V that are continuously output from the arithmetic unit 22a, and outputs it to the subtracter 28a. The subtracter 28a calculates B1-A1 and calculates the difference C.
1 is calculated, and the subtracted value C1 is output to the determiner 14 as a second determination reference value for selecting a quantization step. [0118] Since the subsequent operations are the same as those in the first embodiment described above, the explanation thereof will be omitted. [0119] In the above embodiment, a two-dimensional block is constructed within a field, and a three-dimensional block is constructed by bundling the two-dimensional blocks of a plurality of fields. A three-dimensional block may be constructed by bundling a plurality of frames. [01201 In addition to the above-described embodiment corresponding to the first embodiment, a three-dimensional block is constructed from neighboring pixels in the horizontal direction, vertical direction, and time direction, and sub-blocks are formed within each two-dimensional plane as shown in FIG. By performing blocking, the above-mentioned 2.3, 4, 5.
Embodiments corresponding to the sixth embodiment can also be considered. Note that the configuration and operation of each of these embodiments can be easily understood by appropriately referring to each of the above-mentioned embodiments, so a description thereof will be omitted.

December [Effects of the Invention] As detailed above, in the high-efficiency encoding device of inventions 1.3 and 6.8, blocks in which image quality deterioration is less noticeable are quantized in a low-rate quantization step. Since blocks in which image quality deterioration tends to be noticeable are quantized in a high-rate quantization step, it is possible to output an image signal of good image quality without noise even in flat areas. [0122] Furthermore, in the high-efficiency encoding device of the 2.4 and 7.9 inventions,
Low rate weighting is applied to blocks where image quality deterioration is less noticeable, and high rate weighting is applied to blocks where image quality deterioration is more noticeable, so good image quality can be obtained despite the relatively simple configuration. [0123] Furthermore, in the high-efficiency encoding devices of the fifth and tenth inventions, the weighting is configured to have a smaller number of multipliers than the number of pixels in each block, so it has an information compression rate equivalent to that of the conventional device, A highly efficient encoding device with simple hardware can be obtained. [Brief explanation of drawings]

[Figure 1] FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

[Figure 2] 1st. FIG. 7 is a block diagram showing an example of a configuration of a determination reference value calculating section in a fourth embodiment.

FIG. 3 is an explanatory diagram of the operation of the sub-blocking circuit in the determination reference value calculation section.

[Figure 4] 1st. FIG. 7 is a determination diagram for explaining the operation of the determiner in the fourth example.

[Figure 5] 1st. FIG. 7 is a determination diagram for explaining the operation of the determiner in the fourth example.

FIG. 6 is a diagram showing an example of an image block. 1 for each image block shown in FIG. 6. It is a figure which shows the example of a determination in 4th Example.

[Figure 8] 1st. FIG. 12 is a block diagram showing the configuration of another example of the determination reference value calculation unit in the fourth example.

[Figure 9] FIG. 2 is a block diagram showing the configuration of a second embodiment of the present invention.

[Figure 10] Second. It is a block diagram showing an example of composition of a judgment standard value calculation part in a 5th example.

[Figure 11] Second. FIG. 7 is a determination diagram for explaining the operation of a determiner in a fifth embodiment.

[Figure 12] Second. FIG. 7 is a determination diagram for explaining the operation of a determiner in a fifth embodiment.

FIG. 13 shows the second image for each image block shown in FIG. It is a figure which shows the example of a determination of 5th Example.

[Figure 14] Second. FIG. 12 is a block diagram showing the configuration of another example of the determination reference value calculating section in the fifth embodiment.

[Figure 15] FIG. 3 is a block diagram showing the configuration of a third embodiment of the present invention.

[Figure 16] 3rd. FIG. 12 is a block diagram showing the configuration of a determiner in a sixth embodiment.

[Figure 17] Third. FIG. 7 is a determination diagram for explaining the operation of a determiner in a sixth embodiment.

[Figure 18] 3rd. FIG. 7 is a determination diagram for explaining the operation of a determiner in a sixth embodiment.

FIG. 19 shows the third image for each image block shown in FIG. It is a figure which shows the example of a determination of 6th Example.

[Figure 201 FIG. 3 is a block diagram showing the configuration of a fourth embodiment of the present invention. [Figure 21] FIG. 3 is a block diagram showing the configuration of a fifth embodiment of the present invention.

[Figure 22] FIG. 3 is a block diagram showing the configuration of a sixth embodiment of the present invention.

[Figure 23] FIG. 3 is a block diagram showing the configuration of a seventh embodiment of the present invention.

FIG. 24 is a block diagram showing the configuration of a weighting device in a seventh embodiment.

FIG. 25 is a conceptual diagram showing the operation of zigzag scanning in the seventh embodiment.

FIG. 26 is a conceptual diagram showing an example of weighting coefficients in the seventh embodiment.

FIG. 27 is a diagram showing a bitmap possessed by a variable length encoder in a seventh embodiment.

FIG. 28 is a block diagram showing the configuration of a decoding device for decoding data encoded in a seventh embodiment.

FIG. 29 is a conceptual diagram showing another example of weighting coefficients in the seventh embodiment.

FIG. 30 is a conceptual diagram showing another example of weighting coefficients in the seventh embodiment.

FIG. 31 is a block diagram showing the configuration of an application example of the present invention in three-dimensional blocking.

32 is a block diagram showing the configuration of a determination reference value calculating section in the application example shown in FIG. 31. FIG.

FIG. 33 is a schematic diagram showing how a three-dimensional block is divided into subblocks.

FIG. 34 is a block diagram showing the configuration of a conventional high-efficiency encoding device.

FIG. 35 is a block diagram showing the configuration of another conventional high-efficiency encoding device.

36 is a conceptual diagram for explaining the operation of the weighting device in the conventional device shown in FIG. 35. FIG.

37 is a conceptual diagram illustrating the implementation of weighting in the conventional device shown in FIG. 35. FIG.

[Explanation of symbols]

1 Blocking circuit 1a Blocking circuit Variable length encoder buffer memory Orthogonal transform circuit Orthogonal transform circuit Adaptive quantizer Judgment reference value calculation section Judgment reference value calculation section Judge controller Judgment reference value calculation section Judgment device Adaptive weighting device Judgment device Determiner subblocking circuit subblocking circuit 23, 24.25 Arithmetic unit arithmetic unit minimum value detector minimum value detector maximum value detector maximum value detector 32, 33.34 arithmetic unit minimum value detector 37, 38. 39 Arithmetic unit 42, 43.44 Dynamic range detector Minimum value detector Maximum value detector Control signal generator Weighting device Multiplier

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[Figure 37] W (m, n)

Claims (10)

[Claims] 1. A high-efficiency encoding device for compressing a digital image signal, comprising: blocking means for dividing the digital image signal into blocks for each of a plurality of pixels; and orthogonal transformation for performing orthogonal transformation on the blocked image signal. quantization means for quantizing transform coefficients obtained by orthogonal transformation; each block of the image signal outputted from the blocking means is further divided into a plurality of subblocks, and the distance between adjacent pixels in each subblock is and means for determining a quantization step when the quantization means performs quantization based on the determination reference value. High efficiency encoding device. 2. A high-efficiency encoding device for compressing a digital image signal, comprising: blocking means for dividing the digital image signal into blocks for each of a plurality of pixels; and orthogonal transformation for performing orthogonal transformation on the blocked image signal. weighting means for weighting transform coefficients obtained by orthogonal transformation; further dividing each block of the image signal output from the blocking means into a plurality of subblocks, and dividing adjacent pixels in each subblock into High-efficiency encoding characterized by comprising: means for determining a determination reference value from the sum of absolute values of differences between image signals; and means for determining a weighting coefficient in the weighting means based on the determination reference value. Device. 3. A high-efficiency encoding device for compressing a digital image signal, comprising: blocking means for dividing the digital image signal into blocks for each of a plurality of pixels; and orthogonal transformation for performing orthogonal transformation on the blocked image signal. quantization means for quantizing transform coefficients obtained by orthogonal transformation; each block of the image signal output from the blocking means is further divided into a plurality of subblocks, and an image of pixels in each subblock is created. A high-efficiency code comprising: means for determining the maximum value and minimum value of a signal; and means for determining a quantization step when the quantization means performs quantization based on the maximum value and minimum value. conversion device. 4. A high-efficiency encoding device for compressing a digital image signal, comprising: blocking means for dividing the digital image signal into blocks for each of a plurality of pixels; and orthogonal transformation for performing orthogonal transformation on the blocked image signal. means, weighting means for weighting transform coefficients obtained by orthogonal transformation, and further dividing each block of the image signal outputted from the blocking means into a plurality of sub-blocks, and dividing the pixels in each sub-block into A high-efficiency encoding device comprising: means for determining a maximum value and a minimum value of an image signal; and means for determining a weighting coefficient in the weighting means based on the maximum value and minimum value. 5. A high-efficiency encoding device for compressing a digital image signal, comprising: blocking means for dividing the digital image signal into blocks for each of a plurality of pixels; and orthogonal transformation for performing orthogonal transformation on each block. means, weighting means having a smaller number of multipliers than the number of pixels in each block and weighting transform coefficients obtained by orthogonal transformation, and means for variable length encoding the weighted transform coefficients. A high-efficiency encoding device comprising: 6. A high-efficiency encoding device for compressing a digital image signal, comprising a blocking means for three-dimensionally blocking the digital image signal for each of a plurality of pixels, and a three-dimensional block for the blocked image signal. orthogonal transformation means for performing orthogonal transformation of units; quantization means for quantizing transform coefficients obtained by the orthogonal transformation; and further dividing each block of the image signal output from the blocking means into a plurality of sub-blocks, means for determining a determination reference value from the sum of absolute values of differences in image signals between adjacent pixels in each sub-block; and based on the determination reference value, the quantization means determines a quantization step when quantizing. 1. A high-efficiency encoding device characterized by comprising means for. 7. A high-efficiency encoding device for compressing a digital image signal, comprising: a blocking means for three-dimensionally blocking the digital image signal for each of a plurality of pixels; and a three-dimensional block for the blocked image signal. orthogonal transformation means for performing unit orthogonal transformation; weighting means for weighting the transform coefficients obtained by the orthogonal transformation; and further dividing each block of the image signal output from the blocking means into a plurality of sub-blocks. , comprising means for determining a determination reference value from the sum of absolute values of image signal differences between adjacent pixels in each sub-block, and means for determining a weighting coefficient in the weighting means based on the determination reference value. A high-efficiency encoding device featuring: 8. A high-efficiency encoding device for compressing a digital image signal, comprising a blocking means for three-dimensionally blocking the digital image signal for each of a plurality of pixels, and a three-dimensional block for the blocked image signal. orthogonal transformation means for performing orthogonal transformation of units; quantization means for quantizing transform coefficients obtained by the orthogonal transformation; and further dividing each block of the image signal output from the blocking means into a plurality of sub-blocks, comprising means for determining the maximum value and minimum value of the image signal of the pixels in each sub-block, and means for determining a quantization step when the quantization means performs quantization based on the maximum value and minimum value. A high-efficiency encoding device characterized by the following. 9. A high-efficiency encoding device for compressing a digital image signal, comprising: blocking means for three-dimensionally blocking the digital image signal for each of a plurality of pixels; and a three-dimensional block for the blocked image signal. orthogonal transformation means for performing unit orthogonal transformation; weighting means for weighting the transform coefficients obtained by the orthogonal transformation; and further dividing each block of the image signal output from the blocking means into a plurality of sub-blocks. , means for determining the maximum and minimum values of image signals of pixels in each sub-block;
and means for determining a weighting coefficient in the weighting means based on the maximum value and the minimum value. 10. A high-efficiency encoding device for compressing a digital image signal, wherein the digital image signal is
a blocking means for forming blocks into dimensions; an orthogonal transformation means for performing an orthogonal transformation on each block in three-dimensional blocks; and a multiplication unit that is smaller in number than the number of pixels included in a two-dimensional plane in each block. 1. A high-efficiency encoding device comprising: weighting means for weighting transform coefficients obtained by orthogonal transform; and means for variable-length encoding the weighted transform coefficients.