JP2545302B2 - High efficiency encoder - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-efficiency coding apparatus used in a device for recording a digital image signal such as a digital VCR and compressing the data amount of the digital image signal.

[0002]

2. Description of the Related Art FIG. 34 shows, for example, IEEE Transactions on C.
onsumer Electronics, Vol.34, No.3 (AUGUSUT, 1988) “AN EXPERIMENTAL DIGITAL VCR WITH 40MM DRUM, SINGL
FIG. 1 is a block diagram showing a configuration of a conventional high-efficiency encoding device shown in “E ACTUATOR AND DCT-BASED BIT-RATE REDUCTION”. In the figure, 1 is a block for dividing an input digital image into a plurality of blocks. The block circuit 1 is a DCT circuit 2 for converting the image signal of each block.
Output to. The DCT circuit 2 uses the Discrete Cosine for each block of the image signal output from the blocking circuit 1.
Transform (hereinafter abbreviated as DCT) is performed and the transform coefficient is output to the quantizer 3. The quantizer 3 holds a plurality of quantization tables having different quantization steps, selects and quantizes an optimum quantization table according to the transform coefficient in the block, and quantizes the quantized transform coefficient. Output to 4.
The variable length encoder 4 performs variable length coding on the quantized transform coefficient, and outputs the variable length coded transform coefficient to the buffer memory 5. The buffer memory 5 converts the variable-length coded image signal at a fixed rate and stores it. The controller 6 is
In order to prevent the buffer memory 5 from overflowing, the quantization parameter of the quantizer 3 is selected and the transform coefficient coded by the variable length encoder 4 is selected.

Next, a specific operation will be described. The input digital image signal is composed of, for example, a luminance signal and two color difference signals, and these signals are time-division multiplexed in the block forming circuit 1 and divided into blocks of, for example, 8 pixels × 8 lines and output to the DCT circuit 2. To be done. DCT circuit 2
Then, for the image signal of each block, the image signal x
When expressed as (i, j) (i, j = 0, 1, ..., 7), 8-point DCT in the horizontal direction according to the following equation is performed.

[0004]

[Equation 1]

Converted image signals f (0, j), f
The vertical 8-point DCT according to the following equation is applied to (m, j), and the image signal is transformed into a transform coefficient F (m, n) (m, n =
0, 1, ..., 7) and output to the quantizer 3.

[0006]

[Equation 2]

The obtained transform coefficient is quantized in the quantizer 3 according to the quantization step selected based on the content of the transform coefficient and the quantization parameter from the controller 6. A coarse quantization step is selected when the content of the transform coefficient indicates an image of a rising portion with high contrast, and a fine quantization step is selected when the content thereof indicates an image of a small amplitude detail portion. .

The quantized transform coefficient is supplied to the variable length encoder 4
It is stored in the buffer memory 5 after variable-length coding in. The amount of data stored in the buffer memory 5 is detected by the controller 6 so that the buffer memory 5 does not overflow. The controller 6 selects a quantization parameter according to the amount of data stored in the buffer memory 5 and outputs it to the quantizer 3, and the variable length encoder 4 encodes it according to this amount of data. The transform coefficient to be converted is selected and output to the variable length encoder 4. The data stored in the buffer memory 5 is
It is read at a fixed rate.

FIG. 35 is a block diagram showing the configuration of another conventional high-efficiency coding apparatus disclosed in the above-mentioned document, for example. In the figure, the parts given the same numbers as in FIG. 34 show the same parts, and therefore their explanations are omitted. In this example, a weighting device 7 for weighting the transform coefficient obtained by the DCT circuit 2 is provided between the blocking circuit 1 and the quantizer 3. The quantizer 3 quantizes each weighted transform coefficient.

Next, the operation will be described. Similar to the above-mentioned example, the DCT circuit 2 performs 8-point DCT in the horizontal and vertical directions on the image signal of each block divided in the blocking circuit 1 to obtain the transform coefficient F.
(M, n) is output to the weighting device 7. Each transform coefficient from the DCT circuit 2 is weighted by the weighting unit 7. Specifically, when the result of the DCT calculation for each block of 8 pixels × 8 lines is divided into four regions as shown in FIG. 36, by utilizing the fact that human vision is dull for high spatial frequencies, A weighting coefficient W (m, m) for performing low-rate weighting in the area of F ₄ containing a high spatial frequency component and high-rate weighting in the area of F ₁ containing a low spatial frequency component n) is used (see FIG. 37).

[0011]

(Equation 3)

The weighted transform coefficient is output to the quantizer 3. The subsequent operations in the quantizer 3, buffer memory 5 and controller 6 are the same as those shown in FIG. 34, and therefore their explanations are omitted.

[0013]

Although the conventional high-efficiency coding apparatus is configured as described above, there are the following problems regarding the selection of the quantization step and the configuration of the weighting device. .

The quantizer 3 selects a quantization step according to the AC power E obtained from the conversion coefficient F (m, n) by the following equation.

[0015]

[Equation 4]

When the value of the AC power E is small, it is quantized in fine steps, and when E is large, it is quantized in coarse steps. That is, the detail part in which the amplitude change of the image is small is finely quantized, and the edge part with high contrast is roughly quantized. In an image in which a flat portion, which is a flat background with little change in the image signal, has lines with high contrast, the image block is roughly quantized, but when inverse DCT is performed on the decoder side, The quantization error spreads over the entire block and noise is superimposed even on the flat portion. Since such noise in the flat portion is very noticeable visually, there is a problem that the image quality is significantly deteriorated.

Further, for example, in order to apply weighting to a conversion coefficient having a block size of 8 × 8, 8 ² = 6
Since four types of multipliers are required, there is a problem that the size of the weighting device is large.

The present invention has been made to solve such a problem, and it is possible to quantize an image signal so that a good image quality can be maintained on the decoder side even in a flat portion where image quality deterioration is noticeable. , And also with a small number of multipliers,
An object of the present invention is to provide a high-efficiency coding device capable of performing image signal compression in which image quality deterioration is not noticeable.

[0019]

A high-efficiency coding apparatus according to the first invention of the present application is a high-efficiency coding apparatus for compressing a digital image signal, and a blocking means for dividing the digital image signal into blocks for each of a plurality of pixels. An orthogonal transform means for performing an orthogonal transform on the blocked image signal, a quantizing means for quantizing a transform coefficient obtained by the orthogonal transform, and a quantizing step when the quantizing means quantizes. Determining means, the means for determining the quantization step further divides each block output from the blocking means into a plurality of sub-blocks, and for each sub-block, the pixel value in the sub-block A means for obtaining an index indicating the degree of change, and a determination reference value indicating the degree of local image change of the block from the indices of a plurality of sub-blocks forming each block. Characterized in that it comprises a that means.

The high-efficiency coding apparatus of the second invention of the present application is characterized in that the index is a sum of absolute values of differences between image signals between adjacent pixels in each sub-block.

The high-efficiency encoder of the third invention of the present application is characterized in that the index is the dynamic range of the image signal of the pixel in each sub-block.

The high-efficiency coding apparatus of the fourth invention of the present application is characterized in that the criterion value is the maximum value or the minimum value of the indices of the plurality of sub-blocks constituting each block.

The high-efficiency coding apparatus of the fifth invention of the present application is a high-efficiency coding apparatus for compressing a digital image signal,
Blocking means for dividing the digital image signal into blocks for each of a plurality of pixels, orthogonal transformation means for performing orthogonal transformation on the blocked image signal, and weighting for transform coefficients obtained by the orthogonal transformation. Means for determining the weighting coefficient in the weighting means, and the means for determining the weighting coefficient further divides each block output from the blocking means into a plurality of sub-blocks. And means for obtaining an index indicating the degree of change in pixel value within each sub-block, and a determination indicating the degree of local image change of the block from the indices of a plurality of sub-blocks constituting each block And a means for obtaining a reference value.

The high-efficiency coding apparatus of the sixth invention of the present application is characterized in that the index is a sum of absolute values of differences in image signals between adjacent pixels in each sub-block.

The high-efficiency coding apparatus of the seventh invention of the present application is characterized in that the index is a dynamic range of an image signal of a pixel in each sub-block.

The high-efficiency coding apparatus of the eighth invention of the present application is characterized in that the judgment reference value is the maximum value or the minimum value of the indices of a plurality of sub-blocks constituting each block.

The high-efficiency coding apparatus according to the ninth invention of the present application is the high-efficiency coding apparatus for compressing a digital image signal,
Blocking means for dividing the digital image signal into a plurality of pixels into blocks, orthogonal transformation means for performing an orthogonal transformation on each of the blocked blocks, and a weighting coefficient smaller than the number of pixels in each block are provided. However, a weighting means for performing weighting on the transform coefficient obtained by orthogonal transform, and means for variable-length coding the weighted transform coefficient, the weighting means, The present invention is characterized by including a means for obtaining a reference value from the horizontal sequence and the vertical sequence and determining the weighting coefficient based on the reference value.

The high-efficiency coding apparatus of the tenth invention of the present application is
In a high-efficiency coding apparatus for compressing a digital image signal, a blocking means for blocking the digital image signal into a three-dimensional block for each of a plurality of pixels, and an orthogonal transform for performing a three-dimensional orthogonal transform on the blocked image signal. Means, means for quantizing a transform coefficient obtained by orthogonal transformation, and means for determining a quantization step when the quantization means quantizes, and means for determining the quantization step is the block Means for further dividing each block output from the converting means into a plurality of sub-blocks, means for obtaining an index indicating the degree of change in the pixel value in each sub-block, and a plurality of sub-blocks constituting each block Means for obtaining a judgment reference value indicating the degree of local image change of the block from the index of the block.
A high-efficiency coding apparatus according to an eleventh invention of the present application is a high-efficiency coding apparatus for compressing a digital image signal, which includes a blocking means for three-dimensionally blocking the digital image signal into a plurality of pixels, and a blocking means. An orthogonal transform means for performing a three-dimensional orthogonal transform on the image signal, a weighting means for weighting the transform coefficient obtained by the orthogonal transform, and a means for determining the weighting coefficient in the weighting means are provided. A means for determining the weighting coefficient, the means for further dividing each block output from the blocking means into a plurality of sub-blocks, and an index indicating the degree of change in the pixel value in each sub-block From the index of a plurality of sub-blocks that make up each block, and Characterized in that it comprises a means for obtaining a criterion value indicating a focus. A high-efficiency coding apparatus according to a twelfth invention of the present application is a high-efficiency coding apparatus for compressing a digital image signal, which is a blocking unit that three-dimensionally blocks the digital image signal into a plurality of pixels, and is blocked. An orthogonal transform means for performing a three-dimensional orthogonal transform on each block and a weighting coefficient smaller than the number of pixels included in the two-dimensional plane in each block are provided, and a weighting coefficient is applied to the transform coefficient obtained by the orthogonal transform. A weighting means for performing weighting and a means for variable length encoding the weighted transform coefficient are provided, and the weighting means obtains a reference value from the horizontal sequence and the vertical sequence of each transform coefficient. It is characterized by further comprising means for determining the weighting coefficient based on the reference value.

[0029]

The main features of the present invention are that the means for determining the quantization step further divides each of the plurality of blocks into a plurality of sub-blocks, and means for obtaining an index indicating the degree of change in the pixel value within the sub-blocks. , A means for obtaining a judgment reference value indicating the degree of local image change of the block from the indices of a plurality of sub-blocks constituting each block, and the quantization step is performed by the judgment reference value obtained by these means. Make a decision.

Such characteristics are also provided for determining the weighting coefficient. As the index, the sum of the absolute values of the differences between the image signals between adjacent pixels in the sub-block or the dynamic range of the image signal of the pixels in the sub-block is used. As the determination reference value, the maximum value and the minimum value of the index of the plurality of sub-blocks are used. Claims 1-4
The invention of (1) has a basic configuration of such an encoding device, and the invention of claims 5 to 8 comprises means for weighting the transform coefficient obtained by orthogonal transform. The ninth aspect has means for determining the weighting coefficient. Furthermore, the inventions of claims 10 to 12 apply the above-mentioned invention three-dimensionally.

According to these inventions, low-rate quantization or weighting with a high compression rate is performed in the image portion where the image quality deterioration is not noticeable, and high-rate quantization or a small compression rate is performed in the image portion where the image quality deterioration is noticeable. You will be doing weighting. Then, noise is not noticeable even in the flat part. In the inventions of claims 9 and 12, a weighting coefficient smaller than the number of pixels is used, for example, N × N.
In the block size of, it becomes possible to perform weighting with N ^2/4 or fewer multipliers.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments.

In FIG. 1 showing the configuration of the first embodiment of the present invention, reference numerals 1, 4 and 5 respectively denote a blocking circuit for dividing an input digital image into a plurality of blocks, and an adaptive quantizer.
A variable-length encoder for variable-length coding the output of 12 and a buffer memory for storing the output of the variable-length encoder 4, which are equivalent to those shown in the conventional example of FIG. 34 or FIG. In addition to these, the first embodiment performs an orthogonal transformation circuit 11 that performs orthogonal transformation on each block of the image signal from the blocking circuit 1 and a quantization that is adapted to the transformation coefficient from the orthogonal transformation circuit 11. An adaptive quantizer 12 having a plurality of quantization tables, and each of the blocks divided in the blocking circuit 1 is further divided into a plurality of sub-blocks, and first and second determinations are used as a criterion for selecting a quantization table. A judgment reference value calculation unit 13 that calculates and outputs a reference value, and a judgment unit 14 that selects a quantization table based on the output from the judgment reference value calculation unit 13 and outputs the contents to the adaptive quantizer 12. , A controller 15 for controlling the selection of the quantization step so that the buffer memory 5 does not overflow. The quantization table may be a uniform quantizer having a fixed step width or a non-linear quantizer having a non-constant step width.

As shown in FIG. 2, the judgment reference value calculation unit 13
Is a sub-blocking circuit 21 that divides each block of the image signal output from the blocking circuit 1 into, for example, four sub-blocks, and an image signal between pixels that are horizontally and vertically adjacent in each sub-block. Of the four arithmetic units 22, 23, 24, 25 for obtaining the sum of the absolute values of the differences, the minimum value detector 26 for detecting the minimum value A of the outputs of the four arithmetic units, and the four arithmetic units Maximum value detector 27 that detects the maximum value B of the output
And a subtractor 28 for subtracting the output A of the minimum value detector 26 from the output B of the maximum value detector 27. Judgment reference value calculation unit 13
Therefore, the output A of the minimum value detector 26 is output to the determiner 14 as the first determination reference value, and the output C (= BA) of the subtractor 28 is output to the determination device 14 as the second determination reference value.

Next, the operation will be described. A digital image signal (luminance signal and two color difference signals or RGB signals) input to the blocking circuit 1 is time-division multiplexed in the blocking circuit 1, and for example, 8 pixels × 8 lines are divided into one block. To be done. Each block of the divided image signal is output to the orthogonal transformation circuit 11 and the determination reference value calculation unit 13. In the orthogonal transformation circuit 11, the image signal is subjected to orthogonal transformation such as Discrete Cosine Transform (DCT). The transform coefficient output from the orthogonal transform circuit 11 is output to the adaptive quantizer 12.

In the judgment reference value calculation unit 13, as shown in FIG. 3, 8 pixels × 8 outputted from the blocking circuit 1
Each block of lines is divided into _four sub blocks y ₁ , y ₂ , y ₃ , y ₄ of 4 pixels × 4 lines. Here, the image signals of the sub-blocks y ₁ , y ₂ , y ₃ , y ₄ are respectively y ₁ ,
(I, j), y ₂ , (i, j), y ₃ , (i, j), y ₄ ,
(I, j) (i, j = 1, 2, 3, 4). Arithmetic unit
The image signals of the sub blocks y ₁ , y ₂ , y ₃ , y ₄ are input to 22, 23, 24, 25, respectively. The calculator 22 is a sub-block y
_With respect to ₁ , the sum V ₁ of the absolute values of the differences between the image signals between the adjacent pixels in the horizontal and vertical directions within the sub-block y ₁ is calculated by the following equation.

[0037]

(Equation 5)

Similarly, the other arithmetic units 23, 24, 25 also sum the absolute values of the differences in the image signals between the adjacent pixels in the horizontal and vertical directions in the sub-blocks y ₂ , y ₃ , y ₄ . V ₂ , V ₃ and V ₄
Is calculated according to the following equation.

[0039]

(Equation 6)

The minimum value detector 26 is composed of arithmetic units 22, 23, 24, 25.
Output V ₁ , V ₂ , V ₃ , V ₄ minimum value A = MIN {V ₁ , V ₂ ,
V ₃ , V ₄ } is detected, and the minimum value A is output to the determiner 14 as the first determination reference value for selecting the quantization step and to the subtractor 28. On the other hand, the maximum value detector 27
Is a subtracter that detects the maximum value B = MAX {V ₁ , V ₂ , V ₃ , V ₄ } of the outputs V ₁ , V ₂ , V ₃ , V ₄ of the computing units 22, 23, 24, 25.
Output to 28. The subtractor 28 calculates B-A and calculates the difference C
And outputs the subtraction value C to the determiner 14 as the second determination reference value for selecting the quantization step.

The first judgment reference value A is for detecting a flat portion of the image. When the first judgment reference value A is small, there is a flat portion in the block where image quality deterioration is noticeable on the decoder side. Indicates that. On the other hand, the second judgment reference value C
Indicates that the change in the image is detected. The larger the second determination reference value C, the larger the change in the image in the block and the more likely the quantization error is to occur on the decoder side.

The decision unit 14 determines the first,
The quantization step for quantizing the transform coefficient in the adaptive quantizer 12 is selected according to the second judgment reference values A and C. The adaptive quantizer 12 holds a quantization table having different quantization steps, for example, a high-rate quantization table, a medium-rate quantization table, and a low-rate quantization table. A high-rate quantization table has a fine quantization step, a medium-rate quantization table has a medium quantization step, and a low-rate quantization table has a coarse quantization step. It is a quantization table. The determiner 14 selects the optimum quantization table from these three quantization tables based on FIG. 4 or FIG. 5 according to the first and second determination reference values A and C. When the first determination reference value A is small, there is a flat portion in which the image quality deterioration is conspicuous in that block, so a high-rate or medium-rate quantization table is selected. If the second criterion value C is large, the image change in the block changes greatly and quantization errors are likely to occur on the decoder side. Therefore, a high-rate quantization table with a fine quantization step should be used. Select.

Here, the operation of the decision unit 14 will be concretely described based on the decision diagram of FIG. 7 by taking the image block as shown in FIG. 6 as an example. Here, in order to simplify the explanation,
Instead of the total sum V _n (n = 1, 2, 3, 4) of the absolute values of the differences between the image signals between the adjacent pixels in the sub block, the average variation M _n = V _n / 24 is used. .

FIG. 6 (a) is a block in which one diagonal line has a high contrast on a flat background. Since this block is an image in which quantization noise spreads in a flat part and deterioration is apt to be noticeable on the decoder side, it may be quantized by a high-rate quantization leble. The average variation in each sub-block in this block is M ₁ =
2, M ₂ = 2, M ₃ = 10, M ₄ = 33. The determination reference values A / 24 and C / 24 in this case are, respectively, A / 24 = MIN {M ₁ , M ₂ , M ₃ , M ₄ } = 2 C / 24 = MAX {M ₁ , M ₂ , M _{3 , M 4} -MIN {M 1} , M 2, M 3, M 4} = 31 , and the since the decision diagram of Figure 7 located in the α point determiner
14 selects a high rate quantization table.

FIG. 6B shows a block in which a flat background has an edge with not so high contrast. This block cannot use a low-rate quantization table because it has a flat part, but the quantization error on the decoder side is small because the contrast is not so high. It should be done. The average fluctuation amount in each sub-block in this block is M ₁ = 2, M ₂ = 3, M ₃ = 14, M ₄ = 15. The judgment reference values A / 24 and C / 24 in this case are A /
Since 24 = 2 and C / 24 = 13, which is located at point β in the determination diagram of FIG. 7, the determiner 14 selects the quantization table of the medium rate.

FIG. 6C shows a block in which the change in contrast is large over the entire block. Since the quantization error of this block is not noticeable on the decoder side, it is sufficient if the block is quantized by a low-rate quantization table to increase the compression rate. The average fluctuation amount in each sub-block in this block is M ₁ = 28, M ₂ = 30, M ₃ = 24, M ₄ = 16. In this case, the judgment reference values A / 24 and C / 24 are A and
Since / 24 = 16 and C / 24 = 14, which is located at point γ in the determination diagram of FIG. 7, the determiner 14 selects a low-rate quantization table.

By the way, the selection criterion of the quantization step, that is, the occupation ratios of the three quantization tables are different in FIGS. 4 and 5, and which of these FIGS. 4 and 5 is used as the determination diagram is controlled. Determined by instrument 15. The controller 15 senses the amount of data stored in the buffer memory 5, and adjusts the rate at which the transform coefficient is quantized in the adaptive quantizer 12 so that the buffer memory 5 does not orb flow. Play a role. That is, when the storage capacity of the buffer memory 5 has a sufficient margin, the controller 15 has a high rate of selecting a high-rate quantization table based on the selection criteria shown in the determination diagram of FIG. 4, for example. On the other hand, when the buffer memory 5 is close to the saturated state, the role of selecting the low-rate quantization table is increased by taking the selection criterion as shown in the determination diagram of FIG. In this way, the controller 15 adjusts the rate at which the transform coefficient is output to the buffer memory 5.

According to the selection result of the decision unit 14 as described above, the adaptive quantizer 12 selects an appropriate quantization step for each block, quantizes the transform coefficient output from the orthogonal transform circuit 11, and selects it. The quantization step and the quantized transform coefficient are output to the variable length encoder 4. The variable-length coded transform coefficient is stored in the buffer memory 5, then read at a fixed rate and sent to the outside.

It should be noted that in the above embodiment, the first and second pixel values are determined from the difference in the image signals between the pixels that are adjacent in the horizontal and vertical directions.
The determination reference values A and C are obtained. Especially, when the processing is performed within one field in the interlaced scanning, the distance between adjacent pixels in the vertical direction is large, so that the flat portion is detected. For the first determination reference value, only the difference between the image signals of adjacent pixels in the horizontal direction may be used.

FIG. 8 shows the configuration of the judgment reference value calculation unit 13 in such a modified example. This judgment reference value calculation unit 13 is
The sub-blocking circuit 21, the arithmetic units 31, 32, 33, 34 for obtaining the sum total of the absolute values of the image signal differences between horizontally adjacent pixels in each of the four sub-blocks, and the arithmetic units 31, 32, 33, 34
A minimum value detector 35 for detecting the minimum value among the values obtained in step 3 and an arithmetic unit 3 for obtaining the sum of absolute values of differences in image signals between vertically adjacent pixels in each of the four sub-blocks.
6, 37, 38, 39 and adder 60 that adds the outputs of calculators 31 and 36, adder 61 that adds the outputs of calculators 32 and 37, and adder that adds the outputs of calculators 33 and 38 Unit 62 and calculators 34, 39
Adder 63 for adding the outputs of each, and each adder 60, 61, 62, 63
Of the minimum value detector 26 that detects the minimum value from among the outputs of, the maximum value detector 27 that detects the maximum value among the outputs of the adders 60, 61, 62, 63, and the maximum value detector 27 And a subtractor 28 for subtracting the output of the minimum value detector 26 from the output.

Next, the operation will be described. The four sub-blocks y ₁ , y ₂ , output from the sub-blocking circuit 21
The image signals of y ₃ and y ₄ are converted into y ₁ (i, j) and y _{2 respectively.}
(I, j), y ₃ (i, j), y ₄ (i, j) (i, j
= 1, 2, 3, 4). Sub-blocks y ₁ , y ₂ , y ₃ , y ₄ are input to the arithmetic units 31, 32, 33, 34, respectively. Arithmetic unit
31 calculates the total sum V _h1 of the absolute values of the differences between the image signals between adjacent pixels in the horizontal direction within the sub-block y _{1 as} in the following equation.

[0052]

(Equation 7)

Similarly, the other computing units 32, 33 and 34 similarly sum up the absolute values V _h2 and V of the absolute values of the differences in the image signals between horizontally adjacent pixels in the sub-blocks y ₂ , y ₃ and y ₄ . _h3 and _Vh4 are calculated as in the following equation.

[0054]

(Equation 8)

The minimum value detector 35 is composed of arithmetic units 31, 32, 33, 34.
Output V _h1 , V _h2 , V _h3 , V _h4 minimum value A _h = MIN
{V _h1 , V _h2 , V _h3 , V _h4 } is detected and output. This minimum value A _h is output to the determiner 14 as a first determination reference value for selecting the quantization step in the adaptive quantizer 12.

On the other hand, the sub-blocks y ₁ , y ₂ , y ₃ , y ₄ are also input to the arithmetic units 36, 37, 38, 39, respectively. The calculator 36 is
The sum V _v1 of the absolute values of the differences in the image signals between the adjacent pixels in the vertical direction within the sub-block y ₁ is calculated by the following equation.

[0057]

[Equation 9]

Similarly, the other arithmetic units 37, 38, 39 also sum up the absolute values V _v2 , V of the absolute values of the differences in the image signals between the adjacent pixels in the vertical direction within the sub-blocks y ₂ , y ₃ , y ₄ . _v3 and V _v4 are calculated as in the following equation.

[0059]

[Equation 10]

The outputs V _h1 and V _v1 of the arithmetic units 31 and 36 are added to the adder 60.
Is input to V ₁ = V _h1 + V _v1 . Similarly,
In adders 61, 62 and 63, V ₂ (= V _h2 + V _v2 ), V ₃ (=
V _h 3 + V _v3 , V ₄ (= V _h4 + V _v4 ) are calculated respectively. The minimum value detector 26 is the output V of the adders 60, 61, 62, 63.
Minimum value of ₁ , V ₂ , V ₃ , V ₄ A = MIN {V ₁ , V ₂ , V ₃ , V
₄ } is detected and output to the subtractor 28. Further, the maximum value detector 27 outputs the outputs V ₁ , V ₂ , V ₃ , V ₄ of the adders 60, 61, 62, 63.
The maximum value B = MAX {V ₁ , V ₂ , V ₃ , V ₄ } of the above is detected and output to the subtractor 28. The subtractor 28 calculates and outputs the difference C between the maximum value B and the minimum value A. The subtraction value C is used as a second determination reference value for selecting the quantization step, and the determination unit
Output to 14.

Since the subsequent operation is the same as that of the above-mentioned embodiment, its explanation is omitted.

Next, a second embodiment of the present invention will be described.

In the above-described first embodiment, the subtraction value C obtained by subtracting the minimum value A from the maximum value B is adopted as the second judgment reference value for selecting the quantization step. Alternatively, the maximum value B may be adopted. The second embodiment is an example in which the maximum value B is adopted as the second determination reference value in the first embodiment. The first criterion value is the first
It is the minimum value A as in the embodiment.

In FIG. 9 showing the configuration of the second embodiment,
1, 4, 5, 11, 12, 14, 15 are block circuits,
A variable-length encoder, a buffer memory, an orthogonal transform circuit, an adaptive quantizer, a determiner, and a controller, which are equivalent to those shown in FIG. 1 and therefore will not be described here. Further, reference numeral 16 is a judgment reference value calculation unit in the second embodiment whose configuration is shown in FIG. The configuration of the determination reference value calculation unit 16 is different from the configuration of the determination reference value calculation unit 13 shown in FIG. 2 in that the subtractor 28 is removed.
16, the smallest sub-block y _1, y _2, y _3, the sum V ₁ of the absolute value of the difference of the image signal between the horizontal and vertical adjacent pixels in the y within _{4, V 2, V 3,} V 4 The value A and the maximum value B are detected,
The minimum value A and the maximum value B are output to the determiner 14 as the first and second determination reference values for determining the quantization step.

Next, the operation will be described. Judge 14
Is the first and second determination reference values A,
Depending on B, the adaptive quantizer 12 selects the quantization step for quantizing the transform coefficient based on FIG. 11 or FIG. Here, the operation of the determiner 14 will be specifically described based on the determination diagram of FIG. 13 using an image block as shown in FIG. 6 as an example. The average variation in each sub-block is M ₁ =
2, M ₂ = 2, M ₃ = 10, M ₄ = 33 In FIG. 6A, A / 24 = 2, B / 24 = 33, which is located at the α point in the determination diagram of FIG. 13. The decision unit 14 selects a high-rate quantization table. Further, in FIG. 6B in which the average variation amount in each sub-block is M ₁ = 2, M ₂ = 3, M ₃ = 14, M ₄ = 15, A / 24 = 2, B / 24 = Since this is 15, which is located at point β in the determination diagram of FIG. 13, the determiner 14 selects a medium-rate quantization table. In FIG. 6C in which the average fluctuation amount in each sub-block is M ₁ = 28, M ₂ = 30, M ₃ = 24, M ₄ = 16, A / 24 = 16, B / 24 = 30 , Figure
Since it is located at the point γ in the determination diagram of 13, the determiner 14 selects a low-rate quantization table.

Since the other operations are the same as those in the first embodiment, the description thereof will be omitted. Further, as in the first embodiment, particularly when the processing is performed within one field in the interlaced scanning, the distance between adjacent pixels in the vertical direction is large, so that the first portion for detecting the flat portion is used. As for the determination reference value, the difference between image signals between adjacent pixels in the horizontal direction only may be used. FIG. 14 shows the configuration of the judgment reference value calculation unit 18 in such a modified example. In FIG. 14, the same numbers as those in FIG. 8 indicate the same parts. The determination reference value calculation unit 18 calculates the sum V _hn (n = n) of absolute values of differences between image signals between adjacent pixels in the horizontal direction in each sub-block.
1, 2, 3, 4) minimum value A _h is output to the determiner 14 as a first determination reference value, and the sum of absolute values of differences in image signals between vertically adjacent pixels in each sub-block is added. The maximum value B of the added value V _n of V _vn and the sum V _{hn of} absolute values is output to the determiner 14 as the second determination reference value.

Next, a third embodiment of the present invention will be described.

In the third embodiment, the criterion for selecting the quantization step in the adaptive quantizer 12 is different. In FIG. 15 showing the configuration of the third embodiment, 1, 4, 5, 11, 12, and 15 are a block circuit, a variable length encoder, a buffer memory, an orthogonal transform circuit, an adaptive quantizer, and a controller, respectively. However, these are equivalent to those shown in FIG. 1, and therefore the description is omitted here. Further, 17 is a determiner that divides one block into a plurality of sub-blocks and selects the quantization step in the adaptive quantizer 12 based on the minimum value and the maximum value in the dynamic range of each sub-block. is there.
As shown in FIG. 16, the determiner 17 includes a sub-blocking circuit 21 that divides each block output from the blocking circuit 1 into four sub-blocks, and a dynamic range (minimum value and maximum value) of each sub-block. ), The minimum value detector 45 for detecting the minimum value of the output from the dynamic range detectors 41, 42, 43, 44, and the dynamic range detectors 41, 42 , 43, 44
Maximum value detector 46 for detecting the maximum value of the output from, the subtracter 47 for subtracting the output of the minimum value detector 45 from the output of the maximum value detector 46, the output from the minimum value detector 45 and the subtractor A control signal generator 48 for outputting a control signal for selecting a quantization step to the adaptive quantizer 12 based on the output from 47.

Next, the operation will be described. Similar to the first embodiment, the image signal divided into 8 pixels × 8 lines by the block forming circuit 1 is further divided by the sub block forming circuit 21 into four sub blocks y of 4 pixels × 4 lines.
It is divided into ₁ , y ₂ , y ₃ and y ₄ . Here, the image signals of the sub-blocks y ₁ , y ₂ , y ₃ , y ₄ are respectively y ₁ (i, j), y
₂ (i, j), y ₃ (i, j), y ₄ (i, j) (i,
j = 1, 2, 3, 4). Dynamic range detectors 41, 42, 43, 44, in accordance with an image signal of a subblock _{y 1, y 2, y 3} , y 4, the dynamic range DR ₁ of each _{sub-block, DR 2, DR 3, DR} 4 Is calculated and output as in the following formula.

DR ₁ = MAX {y ₁ (i, j); i, j = 1,2,3,4} -MIN {y ₁ (i, j); i, j = 1,2,3,4 } DR ₂ = MAX {y ₂ (i, j); i, j = 1,2,3,4} -MIN {y ₂ (i, j); i, j = 1,2,3,4} DR _{3 = MAX {y 3 (i} , j); i, j = 1,2,3,4} -MIN {y 3 (i, j); i, j = 1,2,3,4} DR 4 = MAX {y ₄ (i, j); i, j = 1,2,3,4} -MIN {y ₄ (i, j); i, j = 1,2,3,4}

The minimum value detector 45 is a minimum value D = MIN {DR ₁ , DR ₂ , DR ₃ , of the outputs DR ₁ , DR ₂ , DR ₃ , DR ₄ of the dynamic range detectors 41, 42, 43, 44. DR ₄ } is detected and output to the subtractor 47 and the control signal generator 48. On the other hand, the maximum value detector 46 is the dynamic range detector 41,
42, 43, 44 outputs DR ₁ , DR ₂ , DR ₃ , DR ₄ maximum value E
= MAX {DR ₁ , DR ₂ , DR ₃ , DR ₄ } is detected and output to the subtractor 47. The minimum value D and the maximum value E are subtracted by the subtractor 47 to obtain F = ED, and the subtracted value F is output to the control signal generator 48.

When the output D of the minimum value detector 45 is small, there is a flat portion in the block where image quality deterioration is conspicuous on the decoder side. In this case, high-rate or medium-rate quantization is required. On the other hand, when the output F of the subtractor 47 is large, it means that the image change in the block is large and the quantization error is likely to occur on the decoder side. Therefore, when the output D is small and the output F is large, the high rate is high. Needs to be quantized.

The control signal generator 48 outputs the outputs D and F (= E-
According to D), based on FIG. 17 or FIG. 18, the adaptive quantizer 12 outputs a control signal for selecting the optimum quantization step to the adaptive quantizer 12. Here, the operation of the determiner 17 (control signal generator 48) will be specifically described based on the determination diagram of FIG. 19 by taking an image block as shown in FIG. 6 as an example.

In FIG. 6A, in an example of an image signal in which the dynamic range in each sub-block is quantized to 8 bits, DR ₁ = 9, DR ₂ = 8, DR ₃ = 78 , DR
₄ = 114. D in this case, F (= E-D) are _{each, D = MIN {DR 1,} DR 2, DR 3, DR 4} = 8 F = MAX {DR 1, DR 2, DR 3, DR 4} - Since MIN {DR ₁ , DR ₂ , DR ₃ , DR ₄ } = 106, which is located at point α in the determination diagram of FIG.
17 selects a high rate quantization table. Further, the dynamic range in each sub-block is DR ₁ = 8, D
In FIG. 6 (b) where R ₂ = 7, DR ₃ = 64, DR ₄ = 57, D = 7, F = 57, which is located at point β in the determination diagram of FIG. Select a rate quantization table. The dynamic range within each sub-block is D
In FIG. 6 (c) where R ₁ = 61, DR ₂ = 53, DR ₃ = 119, DR ₄ = 119, D = 53, F = 66, which is located at the γ point in the determination diagram of FIG. 19. The determiner 17 selects a low rate quantization table.

Since the other operations are the same as those in the first embodiment, the description thereof will be omitted.

Next, a fourth embodiment of the present invention will be described.

In FIG. 20 showing the fourth embodiment of the present invention,
1, 4, 5, 11, 13, and 15 are a block circuit, a variable-length encoder, a buffer memory, an orthogonal transformation circuit, a judgment reference value calculator, and a controller, respectively, which are shown in FIG. It is equivalent to the one. Further, 18 is an adaptive weighting device that performs weighting adapted to the transform coefficient output from the orthogonal transform circuit 11, and 19 is a weighting in the adaptive weighting device 18 based on the output from the determination reference value calculation unit 13. This is a judging device for selecting a coefficient. The judgment reference value calculator 13 has the internal structure shown in FIG.

Next, the operation will be described.

Similar to the first embodiment described above, the maximum value A and the subtraction value C calculated by the judgment reference value calculation unit 13 are input to the judgment unit 19 as the first and second judgment reference values. . The determining device 19 is an adaptive weighting device based on FIG. 4 or FIG. 5 according to the first and second determination reference values A and C.
The weighting coefficient to be used in 18 is selected.
Here, for example, the adaptive weighting device 18 has the following 3
Holds weighting coefficients for different types of rates.

[0080]

[Equation 11]

W ₁ (m, n) is called a high rate weighting coefficient, W ₂ (m, n) is called a medium rate weighting coefficient, and W ₃ (m, n) is called a low rate weighting coefficient. I will decide. When the first determination reference value A is small, the block has a flat portion where image quality deterioration is noticeable on the decoder side, and therefore high-rate or medium-rate weighting is performed. Further, when the second judgment criterion value C is large, the image in that block changes greatly and quantization errors are likely to occur on the decoder side. Therefore, when A is small and C is large, the effect of high spatial frequency is high. Since it cannot be ignored, high-rate weighting is applied.

Here, the operation of the decision unit 19 will be specifically described by taking an image block as shown in FIG. 6 as an example. Here, the selection criteria for high rate, medium rate, and low rate are:
The same criteria as those in the first embodiment (FIG. 7) are used. In FIG. 6A, which is an image in which quantization noise is spread over a flat portion and deterioration is easily noticeable, high-rate weighting is performed. Since it is located at the point α in the judgment diagram of FIG. 7, the judgment unit 19 selects the high-rate weighting coefficient W ₁ (m, n). In FIG. 6 (b), where there is an edge where the contrast is not so high on the flat background, it is not possible to use low-rate weighting because there is a flat portion, but since the contrast is not so high, quantization at the decoder side is not possible. Since the error is small, a medium rate weighting is applied.
Since it is located at point β in the determination diagram of FIG. 7, the determination unit 19 selects the weighting coefficient W ₂ (m, n) for the medium rate.
The change in contrast is large over the entire area in FIG.
Since the quantization error is not noticeable, the compression rate can be increased by low-rate weighting. Since it is located at the point γ in the judgment diagram of FIG. 7, the judgment unit 19 selects the low-rate weighting coefficient W ₃ (m, n).

According to the selection result of the decision unit 19 as described above, the adaptive weighting unit 18 selects an appropriate weighting coefficient for each block, weights the transform coefficient output from the orthogonal transform circuit 11, and weights the block. Each weighting coefficient and the weighted transform coefficient are output to the variable length encoder 4. The output of the adaptive weighting device 18 is variable-length coded by the variable-length encoder 4 and stored in the buffer memory 5. The data stored in the buffer memory 5 is read at a fixed rate.

The controller 15 senses the amount of data stored in the buffer memory 5 and controls the selection of the weighting coefficient so that the buffer memory 5 does not overflow. That is, when the storage capacity of the buffer memory 5 has a sufficient margin, for example, the selection criterion as shown in the determination diagram of FIG. When the buffer memory 5 is close to the saturated state, the selection criterion as shown in the determination diagram of FIG. 5 is used to increase the proportion of selecting the low-rate weighting coefficient.

Also in the fourth embodiment, as in the first embodiment, particularly when the processing is performed within one field in the interlaced scanning, the distance between adjacent pixels in the vertical direction is large. So the first for detecting flats
As for the determination criterion, the difference between the image signals between adjacent pixels in the horizontal direction only may be used. In such a case, the configuration of the determination reference value calculation unit 13 may be set as shown in FIG.

Next, a fifth embodiment of the present invention will be described.

In the above-described fourth embodiment, the subtraction value C is adopted as the second judgment reference value for selecting the weighting coefficient, but instead of this, the maximum value B may be adopted. Good. The fifth embodiment is an example in which the maximum value B is adopted as the second determination reference value in the fourth embodiment. The first criterion value is the minimum value A, as in the fourth embodiment. 21, which shows the configuration of the fifth embodiment, 1, 4,
5, 11, 15, 18, and 19 are a block circuit, a variable length encoder, a buffer memory, an orthogonal transform circuit, a controller, an adaptive weighting device, and a decision device, respectively, which are shown in FIG. It is equivalent to the one. Further, reference numeral 16 is a judgment reference value calculation unit equivalent to that of the second embodiment whose configuration is shown in FIG. In the fifth embodiment, the weighting coefficient selection criterion in the fourth embodiment is the same as that in the second embodiment. Therefore, the operation of the fifth embodiment can be easily understood by appropriately referring to the second and fourth embodiments, and the description thereof will be omitted.

Next, a sixth embodiment of the present invention will be described.

The sixth embodiment is an example in which the weighting coefficient selection criteria in the adaptive weighting device 18 in the fourth embodiment are the same as those in the third embodiment. 22, which shows the configuration of the sixth embodiment, 1, 4, 5, 11,
Reference numerals 15 and 18 are a block circuit, a variable length encoder, a buffer memory, an orthogonal transform circuit, a controller, and an adaptive weighting device, respectively, which are equivalent to those shown in FIG. Further, reference numeral 20 is a judging device similar to the judging device 17 of the third embodiment whose configuration is shown in FIG. The operation of the sixth embodiment will be described with reference to the third and fourth embodiments as appropriate.
The explanation is omitted because it is easily understood.

Although each block is divided into four sub-blocks in each of the above-described embodiments, it is not always necessary to divide into four sub-blocks, and the number of sub-blocks can be arbitrarily determined according to the size of one block or the like. Good.

Although two kinds of judgment reference values are used when selecting the quantization step or the weighting coefficient, they do not have to be two kinds, and n kinds (n ≧ 1)
May be used. When n = 1, for example, the sum of the absolute values of the differences between the image signals of adjacent pixels in the horizontal direction and the vertical direction in the sub-block is used as the determination reference value, and the quantization step or the way is performed based on this determination reference value. It is also possible to select the Ting coefficient.

Next, a seventh embodiment of the present invention will be described.

In FIG. 23 showing the configuration of the seventh embodiment, the high-efficiency coding apparatus includes a blocking circuit 1 and an orthogonal transformation circuit.
11, a weighting unit 51 that weights the transform coefficient output from the orthogonal transform circuit 11, and a variable length encoder 4 that performs variable length coding. Weighting device
As shown in FIG. 24, 51 is a zigzag scanning circuit 52 that scans pixels in a block in a zigzag manner,
The weighting table 53 stores a plurality of weighting coefficients, and a multiplier 54 that multiplies the conversion coefficient by the weighting coefficient.

Next, the operation will be described. The input digital image signal is time-division multiplexed in the blocking circuit 1 and is divided into blocks for each of a plurality of pixels. Each block output from the blocking circuit 1 is an orthogonal transform circuit.
At 11, orthogonal transformation such as DCT transformation is performed.
The transform coefficient output from the orthogonal transform circuit 11 is weighted by the weighting unit 51. The output of the weighting device 51 is variable-length coded by the variable-length encoder 4.

The operation of the weighting device 51 will be described in detail below. For example, the blocking circuit 1 uses a block of 8 pixels × 8 lines (image signal x (i, j) (i, j = 0,
1, ..., 7)) is output, the orthogonal transformation circuit 11 outputs 8 ×
Eight conversion coefficients F (m, n) (m, n = 0,1, ...,
7) is output. Here, the conversion coefficients are rearranged into a one-dimensional data string by the zigzag scanning circuit 52 having the zigzag scanning characteristics as shown in FIG. 25, and the zigzag scanning circuit 52 transfers the conversion coefficient F (to the multiplier 54 in the scanning order). m, n) is output. In addition, the zigzag scanning circuit 52 outputs the address information of the zigzag scanning for each data string to the weighting table.
Output to 53. The waiting table 53 is accessed by this address information, and the waiting table 53 is accessed.
Outputs the weighting coefficient W for the output data of the zigzag scanning circuit 52 to the multiplier 54.

Here, the weighting coefficient is, for example, as shown in FIG.
As shown in 26, it is determined by 8 types of multipliers,
Specifically, the weighting coefficient W is a maximum value M = MAX {m, n} (m, n = 0, 1, ..., 7) of the order m of the horizontal sequence and the order n of the vertical sequence.
Is expressed by the following equation.

[0097]

(Equation 12)

The conversion coefficient F (m, n) output from the zigzag scanning circuit 52 and the weighting coefficient W (M) output from the weighting table 53 are multiplied by a multiplier 54.
And the weighting is applied to the conversion coefficient as shown below.

[0099]

(Equation 13)

In order to more specifically show the operation of the weighting device 51, consider some 4: 2: 2 component digital image data (information amount is 166 Mbps) quantized to 8 bits at 13.5 MHz. When a weighting of α = 0.6 is used for 64 DCT transform coefficients F (m, n) obtained by DCT transforming a block of 8 pixels × 8 lines, the weighted DCT transform coefficients F '
As a result of performing run-length coding on (m, n) using a bitmap table as shown in FIG. 27 and calculating the amount of information, the image data was 54.7 Mbps. Decoding system
As shown in FIG. 28, the weighted and encoded DCT transform coefficient F ′ (m, n) is decoded by the decoder 55, and the inverse weighter 56 further calculates the weighting coefficient W ′ as described below. The inverse of (M) is F '(m,
Multiply n) to obtain F ″ (m, n).

[0101]

[Equation 14]

Further, in the inverse DCT circuit 57, F ″ (m,
Inverse DCT is applied to n) to obtain a reproduced image x ₁ (i, j). Here, if the SN ratio in one block for the reproduced image x ₁ (i, j) is defined as follows, in the case of the above-mentioned sample image, the SN ratio is 43.5 dB for the Y signal and RY is
It was 44.6 dB and BY was 45.0 dB.

[0103]

(Equation 15)

On the other hand, in conventional weighting, α
= 0.7, the amount of information is 54.8 Mbps and the SN ratio is Y
Signal is 43.5 dB, RY is 44.6 dB, BY is 45.0 dB.
Therefore, the same result as in the case of the example of the present invention can be obtained. However, in the conventional weighting, the number of multipliers of the weighting device is required to be 64.

In the above-mentioned embodiment, the weighting device is 8 depending on the maximum value of the order of the horizontal and vertical sequences.
It consisted of various weighting factors,
It is not always necessary to select the weighting coefficient according to the maximum value of the horizontal and vertical sequence orders.
The weighting coefficient may be selected according to the zigzag scanning order shown in 25.

In this case, since the zigzag scanning repeats the diagonal scanning in the diagonal direction, the weighting coefficient is set to a minimum range with respect to the diagonal scanning.
Within this scanning range, a total of eight types of weighting coefficients are prepared so that the same weighting coefficient is selected. For example, the DCT transform coefficient F (m, n)
For the weighting with respect to the above, as shown in FIG. 29, the following weighting coefficient W (s) may be used.

[0107]

[Equation 16]

Although the weighting coefficient is set to eight in the above embodiment, it is not always necessary to set eight kinds of weighting coefficients.
Fifteen types of weighting factors can be used. For example, in the case of 15 types of weighting, as shown in FIG. 30, the following weighting coefficient W (s) may be used.

[0109]

[Equation 17]

Although the weighting in the two-dimensional plane has been considered in the above-mentioned embodiment, it is not always necessary to consider it in the two-dimensional plane, and even for the three-dimensional block, 2
The above weighting may be performed in units of dimensional planes.

As described above, in the seventh embodiment, the number of multipliers in the weighting unit is N for N × N blocks.
^{Since the} number is set to 2/4 or less, it is possible to obtain a high-efficiency coding device which has an information compression rate equivalent to that of the conventional high-efficiency coding device using a weighting device and is easy to implement in hardware.

In each of the above-described embodiments, the case where the image signal output from the block forming circuit has 8 pixels × 8 lines as one block has been described, but such a two-dimensional block (horizontal direction and horizontal direction The present invention can be similarly applied to not only the vertical direction but also the three-dimensional block (horizontal direction, vertical direction, and time direction).
Hereinafter, an example in which the present invention is applied to a three-dimensional block will be described.

Such a 3 corresponding to the first embodiment described above
An example of the dimension block will be described. In FIG. 31 showing the configuration of this embodiment, 1a is a blocking circuit for dividing an input digital image into a plurality of three-dimensional blocks so that one block has 8 pixels × 8 lines × 8 fields. , 11a is an orthogonal transform circuit that performs a three-dimensional DCT transform on each block from the block formation circuit 1a, and 13a divides each block divided by the block formation circuit 1a into a plurality of sub-blocks. , A judgment reference value calculation unit for calculating and outputting a judgment reference value for the quantization step. Since the other structure is the same as that of the first embodiment, the same parts are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 32, the judgment reference value calculator 13a
Is a sub-blocking circuit 21a that divides each block output from the blocking circuit 1a into, for example, 32 sub-blocks (1 sub-block is 4 pixels × 4 lines), and horizontal and vertical directions within each sub-block. 22a for obtaining the sum of absolute values of differences in image signals between pixels adjacent to each other
And a minimum value detector 26a for detecting the minimum value A ₁ of 32 values continuously output from the arithmetic unit 22a, and a maximum value detector 27a for detecting the maximum value B ₁ of these 32 values, Maximum value detector
And a subtractor 28 _a for subtracting the output A ₁ of the minimum value detector 26 a from the output B _{1 of} 27 a. From the determination reference value calculation unit 13 _a, the minimum value detector as 26 output A ₁ of _a first criterion value and the subtractor 28a outputs C ₁ (B ₁ -A ₁₎ a second
Is output to the determiner 14 as the determination reference value.

Next, the operation will be described. The digital image signal input to the blocking circuit 1a is divided into 8 pixels × 8 lines × 8 fields as one block. Each divided block is output to the orthogonal transformation circuit 11a and the judgment reference value calculation unit 13a. In the sub-blocking circuit 21a in the judgment reference value calculation unit 13a, as shown in FIG. 33, 8 pixels × 8 output from the blocking circuit 1a
Each block of line x 8 fields has 4 sub-blocks of 4 pixels x 4 lines for each field, as a whole
It is divided into 32 sub-blocks. Here, the image signals of the respective sub-blocks are y (i, j) (i, j = 1, 2,
When 3,4), arithmetic unit 22a, for each sub-block, the sum V _{n (n} = 1,2 of the absolute value of the difference between the horizontal and the image signals between vertical adjacent pixels in the sub-block ，
, 32) is calculated as the following equation.

[0116]

(Equation 18)

The minimum value detector 26a has 32 values continuously output from the calculator 22a, that is, the minimum value A ₁ of the value of V _n for each of the 32 sub-blocks constituting one block. And outputs the minimum value A ₁ to the determiner 14 as the first determination reference value for selecting the quantization step and to the subtractor 28a. On the other hand, the maximum value detector
27a is 32 V _n that are continuously output from the computing unit 22a.
The maximum value B ₁ of the values is detected and output to the subtractor 28a. The subtractor 28a calculates B ₁ −A ₁ to obtain the difference C ₁ ,
The subtraction value C ₁ is output to the decision unit 14 as a second decision reference value for selecting the quantization step.

Since the subsequent operation is the same as that of the first embodiment described above, its explanation is omitted.

In the above embodiment, a two-dimensional block is formed in a field and two-dimensional blocks of a plurality of fields are bundled to form a three-dimensional block. However, a two-dimensional block is formed in a frame and A plurality of frames may be bundled to form a three-dimensional block.

In addition to the above-described embodiment corresponding to the first embodiment, a three-dimensional block is constructed from neighboring pixels in the horizontal direction, the vertical direction, and the time direction, and in each two-dimensional plane as shown in FIG. By sub-blocking,
Examples corresponding to the 3, 4, 5, and 6 examples are also conceivable.
Note that the configuration and operation of each of these embodiments can be easily understood by referring to the above-mentioned embodiments as appropriate, and therefore description thereof will be omitted.

[0121]

As described in detail above, in the high-efficiency coding apparatus according to the first to fourth aspects of the present invention, the block in which the image quality deterioration is not noticeable is quantized in the low-rate quantization step, and the image quality deterioration is noticeable. Since easy blocks are quantized in a high-rate quantization step, it is possible to output an image signal of good image quality without noise even in a flat portion.

In the high-efficiency coding apparatus according to the fifth to eighth aspects of the invention, low-rate weighting is applied to blocks where image quality deterioration is less noticeable, and high-rate weighting is applied to blocks where image quality deterioration is more noticeable. Therefore, good image quality can be obtained despite the relatively simple configuration.

Furthermore, in the high-efficiency coding apparatus of the present invention, the weighting has a smaller number of multipliers than the number of pixels in each block, so that the information compression rate equivalent to that of the conventional apparatus is provided. Therefore, it is possible to obtain a high-efficiency coding device having a small amount of hardware. Claim 10
The high-efficiency coding device of the inventions of to 12 can deal with a three-dimensional block, and the above-mentioned effects can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an example of a determination reference value calculation unit in the first and fourth embodiments.

FIG. 3 is an explanatory diagram of an operation of a sub-blocking circuit in the determination reference value calculation unit.

FIG. 4 is a determination diagram for explaining the operation of the determiner in the first and fourth examples.

FIG. 5 is a determination diagram for explaining the operation of the determiner in the first and fourth examples.

FIG. 6 is a diagram showing an example of an image block.

FIG. 7 is a diagram showing a determination example in the first and fourth embodiments for each image block shown in FIG.

FIG. 8 is a block diagram showing the configuration of another example of the judgment reference value calculation unit in the first and fourth embodiments.

FIG. 9 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of an example of a judgment reference value calculation unit in the second and fifth embodiments.

FIG. 11 is a determination diagram for explaining the operation of the determiner in the second and fifth embodiments.

FIG. 12 is a determination diagram for explaining the operation of the determiner in the second and fifth embodiments.

FIG. 13 is a diagram showing a determination example of the second and fifth embodiments for each image block shown in FIG.

FIG. 14 is a block diagram showing the configuration of another example of the judgment reference value calculation unit in the second and fifth embodiments.

FIG. 15 is a block diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 16 is a block diagram showing a configuration of a determiner in third and sixth embodiments.

FIG. 17 is a determination diagram for explaining the operation of the determiner in the third and sixth embodiments.

FIG. 18 is a determination diagram for explaining the operation of the determiner in the third and sixth embodiments.

FIG. 19 is a diagram showing a determination example of the third and sixth embodiments for each image block shown in FIG. 6.

FIG. 20 is a block diagram showing a configuration of a fourth exemplary embodiment of the present invention.

FIG. 21 is a block diagram showing a configuration of a fifth exemplary embodiment of the present invention.

FIG. 22 is a block diagram showing a configuration of a sixth exemplary embodiment of the present invention.

FIG. 23 is a block diagram showing the configuration of a seventh embodiment of the present invention.

FIG. 24 is a block diagram showing a configuration of a weighting device according to a seventh embodiment.

FIG. 25 is a conceptual diagram showing a zigzag scanning operation in the seventh embodiment.

FIG. 26 is a conceptual diagram showing an example of a weighting coefficient in the seventh embodiment.

FIG. 27 is a diagram showing a bitmap included in the variable length encoder in the seventh embodiment.

FIG. 28 is a block diagram showing the structure of a decoding device for decoding the data encoded in the seventh embodiment.

FIG. 29 is a conceptual diagram showing another example of the weighting coefficient in the seventh embodiment.

FIG. 30 is a conceptual diagram showing another example of the weighting coefficient in the seventh embodiment.

FIG. 31 is a block diagram showing a configuration of an application example of the present invention in three-dimensional block formation.

32 is a block diagram showing a configuration of a determination reference value calculation unit in the application example shown in FIG. 31.

FIG. 33 is a schematic diagram showing sub-blocking of a three-dimensional block.

FIG. 34 is a block diagram showing a configuration of a conventional high efficiency encoding device.

FIG. 35 is a block diagram showing the configuration of another conventional high efficiency encoding device.

FIG. 36 is a conceptual diagram for explaining the operation of the weighting device in the conventional device shown in FIG. 35.

FIG. 37 is a conceptual diagram illustrating the implementation of weighting in the conventional device shown in FIG. 35.

[Explanation of symbols]

 1 Blocking circuit 1a Blocking circuit 4 Variable length encoder 5 Buffer memory 11 Orthogonal transformation circuit 11a Orthogonal transformation circuit 12 Adaptive quantizer 13 Judgment reference value calculation unit 13a Judgment reference value calculation unit 14 Judgment unit 15 Controller 16 Judgment reference Value calculator 17 Judgment device 18 Adaptive weighting device 19 Judgment device 20 Judgment device 21 Sub-blocking circuit 21a Sub-blocking circuit 22, 23, 24, 25 Calculation device 22a Calculation device 26 Minimum value detector 26a Minimum value detector 27 Maximum value detector 27a Maximum value detector 31, 32, 33, 34 Operator 35 Minimum value detector 36, 37, 38, 39 Operator 41, 42, 43, 44 Dynamic range detector 45 Minimum value detector 46 Maximum Value detector 48 Control signal generator 51 Waiting device 54 Multiplier

 ─────────────────────────────────────────────────── ─── Continuation of front page (31) Priority claim number Japanese Patent Application No. 2-179121 (32) Priority Day Hei 2 (1990) July 4 (33) Priority claim country Japan (JP)

Claims (12)

(57) [Claims] 1. A high-efficiency coding apparatus for compressing a digital image signal, a blocking means for blocking the digital image signal into a plurality of pixels, and an orthogonal transform for performing an orthogonal transform on the blocked image signal. Means, quantizing means for quantizing a transform coefficient obtained by orthogonal transformation, and means for determining a quantizing step when the quantizing means quantizes, and means for determining the quantizing step, A unit that further divides each block output from the blocking unit into a plurality of sub-blocks, a unit that obtains an index that indicates the degree of change in the pixel value within the sub-block for each sub-block, and a unit that configures each block Means for obtaining a determination reference value indicating the degree of local image change of the block from the index of the sub-block. 2. The high efficiency coding apparatus according to claim 1, wherein the index is a sum of absolute values of differences between image signals between adjacent pixels in each sub-block. 3. The high efficiency coding apparatus according to claim 1, wherein the index is a dynamic range of an image signal of a pixel in each sub-block. 4. The high-efficiency coding according to claim 1, wherein the criterion value is a maximum value or a minimum value of the indices of a plurality of sub-blocks forming each block. apparatus. 5. A high-efficiency coding apparatus for compressing a digital image signal, a blocking means for blocking the digital image signal into a plurality of pixels, and an orthogonal transform for performing an orthogonal transform on the blocked image signal. Means, weighting means for weighting the transform coefficient obtained by orthogonal transform, and means for determining the weighting coefficient in the weighting means, wherein the means for determining the weighting coefficient is the block Means for further dividing each block output from the converting means into a plurality of sub-blocks, means for obtaining an index indicating the degree of change in the pixel value in each sub-block, and a plurality of sub-blocks constituting each block And means for obtaining a criterion value indicating the degree of local image change of the block from the index of the block. High-efficiency encoding apparatus according to claim. 6. The high efficiency coding apparatus according to claim 5, wherein the index is a sum of absolute values of differences in image signals between adjacent pixels in each sub-block. 7. The high efficiency coding apparatus according to claim 5, wherein the index is a dynamic range of an image signal of a pixel in each sub-block. 8. The high efficiency according to claim 5, wherein the judgment reference value is a maximum value or a minimum value among indexes of a plurality of sub-blocks constituting each block. Encoding device. 9. A high-efficiency coding apparatus for compressing a digital image signal, a blocking means for blocking the digital image signal into a plurality of pixels, and an orthogonal transform for performing an orthogonal transform on each of the blocked blocks. Means, a weighting means having a smaller number of weighting coefficients than the number of pixels in each block, and performing weighting on the transform coefficients obtained by orthogonal transformation, and a variable length of the weighted transform coefficients. And a means for encoding, wherein the weighting means obtains a reference value from the horizontal sequence and the vertical sequence of each conversion coefficient, and has a means for determining the weighting coefficient based on this reference value. Encoding device. 10. A high-efficiency coding apparatus for compressing a digital image signal, wherein the digital image signal is divided into a plurality of pixels every 3 pixels.
Blocking means for blocking into three dimensions, orthogonal transformation means for subjecting the blocked image signal to three-dimensional orthogonal transformation, means for quantizing transform coefficients obtained by orthogonal transformation, and the quantizing means for quantizing Means for determining a quantization step at the time of quantization, the means for determining the quantization step further divides each block output from the blocking means into a plurality of sub-blocks, and each sub-block A means for obtaining an index indicating the degree of change of the pixel value in the sub-block, and a means for obtaining a determination reference value indicating the degree of local image change of the block from the indexes of a plurality of sub-blocks constituting each block And a high-efficiency coding device. 11. A high-efficiency encoding apparatus for compressing a digital image signal, wherein the digital image signal is divided into a plurality of pixels for every three pixels.
A blocking means for blocking into three dimensions, an orthogonal transform means for performing a three-dimensional orthogonal transform on the blocked image signal, a weighting means for weighting the transform coefficient obtained by the orthogonal transform, Means for determining a weighting coefficient in the weighting means, the means for determining the weighting coefficient further divides each block output from the blocking means into a plurality of sub-blocks, and each sub-block A means for obtaining an index indicating the degree of change of the pixel value in the sub-block, and a means for obtaining a determination reference value indicating the degree of local image change of the block from the indexes of a plurality of sub-blocks constituting each block And a high-efficiency coding device. 12. A high-efficiency encoding apparatus for compressing a digital image signal, wherein the digital image signal is divided into a plurality of pixels for every three pixels.
A block forming means for forming blocks into three dimensions, an orthogonal transform means for performing a three-dimensional orthogonal transform on each of the blocked blocks, and a weighting coefficient smaller than the number of pixels included in the two-dimensional plane in each block. Having a weighting means for weighting the transform coefficient obtained by the orthogonal transform, and a means for variable-length coding the weighted transform coefficient, wherein the weighting means is provided for each transform coefficient. A high-efficiency coding apparatus comprising means for obtaining a reference value from the horizontal sequence and the vertical sequence and determining the weighting coefficient based on the reference value.