JPH03291030A - Frame synchronizing equipment - Google Patents

Abstract

PURPOSE:To operate a low speed frequency division clock by controlling a frequency division ratio of a variable frequency division counter so as to rearrange a parallel data in a prescribed expansion order. CONSTITUTION:A received serial data (a) is stored sequentially in a shift register 8 while being shifted by a clock pulse (b). A variable frequency division counter 9 generates a frequency division clock (g) for each of n-set of the pulses (b). A latch circuit 10 latches a data in the register 8 at that time according to the clock (g). The data latched in the circuit 10 is outputted as a parallel data (e). The data (e) is given to a pattern detection section 2, in which a frame pattern is detected. The result of detection by the detection section 2 is fed to a frame synchronization section 3. When the data (e) is not expanded in parallel in a prescribed order, the synchronization section 3 changes its frequency division ratio with a load data (f) to the variable frequency division counter 9. Thus, the data (e) keeps a prescribed expansion order and the frame synchronization is maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame synchronization device for synchronizing frames in a receiving section of a digital communication device, particularly a high-speed digital communication device.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional frame synchronization device disclosed in, for example, Japanese Unexamined Patent Publication No. 1-157138. In the figure, 1 is a serial/parallel converter that converts serial data a into n-bit parallel data C based on a clock pulse b, and 2 is a pattern detector that takes in the parallel data C and detects a frame pattern. . 3 is a frame synchronization section for controlling the phase shift of the frame pattern detected by the butter/detection section 2, and includes, for example, a frame counter, a frame synchronization circuit, and the like. 4
is a selector section which controls the order of the parallel data C according to the select signal d output from the frame synchronization section 3 and outputs parallel data e in a predetermined order.

Next, operation 9 will be explained. When the serial-parallel converter 1 receives serial data a, it converts the serial data a into n-bit parallel data C based on the clock pulse b, and outputs it to the selector unit 4. On the other hand, this n-bit parallel data C is also taken into the pattern detection section 2. The pattern detection unit 2 extracts 7 patterns from the captured parallel data C (
The turn is detected and the result is output to the frame synchronization unit 3.

The frame synchronization section 3 performs well-known forward and backward protection by timing the pattern detection position detected by the pattern detection section 2 and an internal frame counter.

Here, the parallel data C subjected to serial-to-parallel conversion by the serial-to-parallel converter 1 may not be developed in a predetermined order. In such a case, the frame synchronization unit 3 generates a select signal d for controlling the order of the parallel data C and sends it to the selector unit 4. The selector section 4 rearranges the order of the parallel data C developed by the serial/parallel converter 1 based on the select signal d from the frame synchronizer 3. As a result, frame synchronization is achieved, and parallel data e in a predetermined development order is
is also output from the selector section 4.

Further, FIG. 5 is a block diagram showing another conventional frame synchronization device disclosed in, for example, Japanese Unexamined Patent Publication No. 1-138831. In the figure, 1 is a serial-to-parallel converter, and 2 is a pattern detector, which are equivalent to those shown in FIG. 5
6 is a 1-bit prohibition circuit that prohibits the transmission of 1 bit of the input clock pulse b, and 6 is a 1-bit prohibition circuit that divides the frequency of the clock pulse b that has passed through the 1-bit prohibition circuit 5 and inputs it to the serial/parallel converter 1. It is a frequency dividing circuit. A frame counter 7 performs a counting operation according to the detection result of the pattern detection section 2 and controls the operation of the 1-bit inhibition circuit 5.

Next, the operation will be explained. The frame counter 7 is reset when the pattern detection section 2 detects a frame synchronization pulse, and starts counting from a signal indicating the position of the frame pulse. Therefore, the parallel data e converted by the serial/parallel converter 1 is taken into the synchronization pattern detector 2 by the count output from the frame counter 7 at that position.

On the other hand, if the frame synchronization pulse cannot be detected, a signal indicating the position of the frame pulse is sent to the 1-bit inhibition circuit 5. When the 1-bit inhibiting circuit 5 receives the signal, it inhibits the supply of the clock pulse b to the frequency dividing circuit 6 by 1 bit. The serial/parallel converter 1 expands the serial data a in parallel using the divided clock from the frequency dividing circuit 6. Frame synchronization is then achieved, and parallel data e rearranged in a predetermined development order is output.

[Problem to be solved by the invention]

Since the conventional frame synchronizer is configured as described above, in the one shown in FIG. Although the circuit does not require high-speed circuit elements and the timing design is easy, when the number of parallel expansions by the serial-parallel converter 1 increases, the control of the selector unit 4 becomes complicated and the circuit scale increases. In the case shown in FIG. 5, the circuit size does not increase even if the number of parallel expansions by the serial-to-parallel converter 1 increases.
The bit inhibiting circuit 5 also requires a high-speed circuit element, making timing design difficult.

This invention was made to solve the above-mentioned problems, and it can be operated with a low-speed divided clock after parallel expansion, and timing design is easy, and even when the number of parallel expansions increases, control is easy. The purpose of this invention is to obtain a frame synchronization device that can suppress an increase in circuit scale.

[Means to solve the problem]

The frame synchronization device according to the present invention functions as a frequency dividing circuit that generates a frequency-divided clock when input serial data is expanded into parallel data. This uses a variable frequency division counter whose frequency division ratio is controlled.

[Function] The variable frequency division counter in the present invention changes its frequency division ratio in response to a signal from the frame synchronization section, and controls the phase shift of a frame pattern detected from parallel data developed from serial data (7). By rearranging the parallel data in a predetermined order of expansion, even if the number of parallel expansions increases, control is easy and the increase in circuit size can be suppressed, and it operates with a low-speed divided clock, making timing design easy. Realize a frame synchronizer.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 2 is a turn detection section, and 3 is a frame synchronization section, which are the same parts as those in FIG. Also,
Reference numeral 8 denotes an n-bit shift register that sequentially shifts and accumulates received serial data a in accordance with clock pulses b. Reference numeral 9 denotes a variable frequency division counter whose frequency division ratio is controlled by the load data f from the frame synchronization section 3, and which divides the clock pulse b by the frequency division ratio to generate a frequency divided clock g. A latch circuit 10 latches the n-bit output signal from the shift register 8 based on the frequency-divided clock g output from the variable frequency-divided counter 9 and develops it into n-bit parallel data e.

Further, FIG. 2 is a block diagram showing the configuration of the variable frequency dividing counter 9. As shown in FIG. In the figure, 91 is a general binary counter with a preset, and 92 and 93 are inverters. No; Inari counter 91 terminal. The load data f is input to the terminal CLK, the clock pulse b is input to the terminal CLK, and the output from the terminal CO is input to the terminal CLK.
It is input as a load signal via the input terminal 93. Further, an inverter 92 for outputting the frequency-divided clock g is connected to the terminal Qn.

Next, the operation will be explained. It is now assumed that the frequency division ratio of the variable frequency division counter 9 is set to "n".

The received serial data a is sequentially accumulated in the shift register B while being shifted by the clock pulse b.
”, the frequency-divided clock g is generated every n clock pulses b.The latch circuit 10 generates the frequency-divided clock g from the variable frequency-divided counter 9 at that time in the shift register 8. The data latched by the latch circuit 10 is expanded in parallel and output as parallel data e.

This parallel data e is also taken in by the pattern detection section 2,
Frame pattern detection is performed. The detection result by the pattern detection section 2 is sent to the frame synchronization section 3, and the frame synchronization section 3 uses the timing of the pattern detection position of the turn detection section 2 and the built-in frame counter to determine the well-known forward and backward directions. Provide protection.

At this time, if the parallel data e is not expanded in parallel in a predetermined order, the frame synchronization unit 3 detecting this,
The frequency division ratio is changed depending on the load data f to the variable frequency division counter 9. FIG. 3 is a timing diagram for explaining the rearrangement of the parallel data e by the variable frequency division counter 9 at that time. Here, a case is shown in which there is a deviation of 2 bits from the predetermined parallel expansion order.

In the variable frequency division counter 9, when the load data f from the frame synchronization unit 3 changes from "0" to "1", the value "1" of this load data f is preset to the binary counter 91 when load force occurs. be done. Therefore, the frequency division ratio of the variable frequency division counter 9 changes from "n" to "IH", and the expansion order of the parallel data e is sequentially rearranged.
After two cycles, the parallel data e becomes in a predetermined expansion order.

When the parallel data e reaches a predetermined expansion order, the frame synchronizer 3 returns the load data f to "0" and sets the frequency division ratio of the variable frequency division counter 9 to "n". As a result, the parallel data e maintains a predetermined expansion order and frame synchronization is ensured.

Here, since the delay time t'' allowed for controlling the load data f is approximately equal to the period of the frequency-divided clock g, the circuit that performs this control can be operated using the frequency-divided clock g. It becomes possible to configure the circuit using low-speed circuit elements.

In the above embodiment, the variable frequency division counter is configured with a binary counter, but a variable frequency division counter with another configuration may be used, and the frequency division ratio may be set to 1.
Although we have explained the case where the expansion order of parallel data is rearranged by decreasing the frequency by ``2'' or ``3'', it is also possible to use other values such as ``2'' or ``3'', or even increase the division ratio. In this case, the same effects as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, parallel data is arranged in a predetermined expansion order by controlling the frequency division ratio of the variable frequency division counter, so that operation with a low-speed frequency division clock is possible. This makes it possible to easily design timing, and furthermore, even when the number of parallel expansions increases, it is possible to obtain a frame synchronization device that is easy to control and can suppress an increase in circuit scale.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a frame synchronization device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a variable frequency dividing counter, and FIG. 3 is a timing diagram for explaining rearrangement of parallel data. , 4 and 5 are block diagrams showing conventional frame synchronization devices. 2 is a pattern detection section, 3 is a frame synchronization section, 8 is a shift register, 9 is a variable frequency division counter, and 10 is a latch circuit. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] a shift register that sequentially shifts and accumulates received serial data in accordance with a clock pulse; a variable frequency division counter that divides the clock pulse by a controllable frequency division ratio to generate a frequency-divided clock; a latch circuit that latches the output data of the shift register and develops it into parallel data based on a frequency-divided clock from a frequency counter; and a pattern detection section that captures the parallel data output from the latch circuit and detects a frame pattern. and a frame synchronization section that controls a frequency division ratio of the variable frequency division counter based on a phase shift of the frame pattern detected by the pattern detection section.