JPH03291017A - Polarity switching type josephson driving circuit - Google Patents

Polarity switching type josephson driving circuit

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Publication number
JPH03291017A
JPH03291017A JP9341290A JP9341290A JPH03291017A JP H03291017 A JPH03291017 A JP H03291017A JP 9341290 A JP9341290 A JP 9341290A JP 9341290 A JP9341290 A JP 9341290A JP H03291017 A JPH03291017 A JP H03291017A
Authority
JP
Japan
Prior art keywords
circuit
josephson
gate circuit
input terminal
direct
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9341290A
Other languages
Japanese (ja)
Inventor
Shuichi Nagasawa
秀一 永沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9341290A priority Critical patent/JPH03291017A/en
Publication of JPH03291017A publication Critical patent/JPH03291017A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce the circuit area, to simplify the layout of the circuit and to attain high circuit integration by forming a polarity switching type Josephson driving circuit with only a direct coupling type Josephson gate circuit. CONSTITUTION:Josephson junctions J11, J12 of a 1st direct coupling type Josephson gate circuit G11 in a 1st driving voltage generating circuit 1 are switched from the superconducting state into the voltage state at a time T1, a bias current is supplied to a junction J13 of a direct coupling type Josephson gate circuit G12 through a resistor R13 (in this case, R110<R13), then the junctions J13, J14 are switched from the superconducting state into the voltage state (in this case, R120<R13) at a time T2, a bias current is injected to a line to be driven 3 and supplied to ground through a junction J23 of a driving voltage generating circuit 2. In such a case, a signal inputted from a terminal S1A flows to ground through the resistors R12, R120 when the junctions J12, J14 in the circuit 1 are switched into the voltage state so as to separate the bias current from the input and output signal.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ジョセフソン素子を用いた超伝導集積回路に
関し、よシ詳しくは超伝導記憶集積回路のワード線及び
ヒツト線などの被駆動線路に電流を注入しかつ任意に電
流の方向を反転できる極性切換型ジ萱セフノン駆動回路
に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a superconducting integrated circuit using a Josephson device, and more particularly to driven lines such as word lines and human lines of a superconducting memory integrated circuit. The present invention relates to a polarity switching type jikagasenon drive circuit that can inject a current into the circuit and arbitrarily reverse the direction of the current.

〔従来の技拘〕[Traditional techniques]

第3図に、従来から知られている極性切換型ジョセフソ
ン駆動回路を説明するための等価回路図を示す(昭和6
3年電子情報通信学会春季全国大会)、第3図を参照し
て従来の技術の説明を行なう。
Figure 3 shows an equivalent circuit diagram for explaining the conventionally known polarity switching type Josephson drive circuit (Showa 6).
The conventional technology will be explained with reference to FIG. 3 (IEICE Spring National Conference).

第3図に示すように従来の極性切換型ジョセフソン駆動
回路は、4個の磁界結合型ショセフノンゲート回路Gl
、G2,03.(j4と3個の抵抗31、R2,Rとメ
モリセルアレイ4のワード造またはビット線などの被駆
動線路よシ構成され2本回路においてバイアス入力端B
1からバイア2電流を供給した状態で、信号入力端81
に信号咽入力すると磁界結合型ジミセフソンゲート回路
(1、G3が超伝導状態から電圧状態にスイッチしバイ
アス電流は被駆動線路3に注入される。被層Jk11線
路3に流れたバイアス電tlILは、磁界結合型シシセ
フソングート回路G4を通って接地に流れ込む。以上の
動作により被駆動線路に時計回シ方直に出力電流を発生
させることができる。一方、)・イアス入力端B2から
バイアス電流を供給したり態で、信号入力端S2に信号
を入力すると磁界綻合型ジョセフソンゲート回路G2、
G4が超伝導状態から電圧状態にスイッチし、バイアス
電流は被駆動線路(リターンライン5)に注入される。
As shown in Fig. 3, the conventional polarity switching type Josephson drive circuit consists of four magnetic field coupling type Josephson non-gate circuits Gl.
, G2,03. (j4, three resistors 31, R2, R, and the word structure of the memory cell array 4 or a driven line such as a bit line) are connected to the bias input terminal B in the two circuits.
1 to via 2, the signal input terminal 81
When a signal is input to the magnetic field coupling type Jimi Sefson gate circuit (1, G3 switches from the superconducting state to the voltage state and the bias current is injected into the driven line 3. The bias current tlIL flowing through the covered Jk11 line 3 flows into the ground through the magnetic field coupling type output circuit G4.By the above operation, an output current can be generated directly in the clockwise direction on the driven line.On the other hand, the bias from the input terminal B2 of ) When a signal is input to the signal input terminal S2 while supplying current, a magnetic field integration type Josephson gate circuit G2,
G4 switches from the superconducting state to the voltage state and a bias current is injected into the driven line (return line 5).

被駆動線路に流れたバイアス電流は、磁界結合型ジロセ
フソンケート回路G3を通って接地に流れ込む。以上の
動作により被駆動線路に長時引回9方向に出力電流を発
生させることができる。
The bias current flowing through the driven line flows into the ground through the magnetic field coupling type Girosefsoncate circuit G3. By the above operation, it is possible to generate an output current in the long-duration 9 directions in the driven line.

以上説明したように、従来の技術によシ被駆動線路に電
流を注入し、かつ任意に電流の方向を反転できる極性切
換型ジロセフソン駆動回路を実現することができる。
As described above, it is possible to realize a polarity-switching type Jirosefson drive circuit that can inject a current into a driven line and arbitrarily reverse the direction of the current using the conventional technology.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の技術におりては、磁界結合型ジョセフソンゲート
回路(2接合5QUIDケート)を用いているため、入
力信号を注入するための制御配鯉と8QUIDループと
の磁界結合のための領域を得るために素子の面積が大き
くなシ大規模な集積化が困難であるという問題点があっ
た。
In the conventional technology, since a magnetically coupled Josephson gate circuit (two-junction 5QUID gate) is used, a region for magnetic coupling between the control circuit and the 8QUID loop for injecting the input signal is obtained. Therefore, there is a problem in that the area of the element is large and large-scale integration is difficult.

本発明の目的は、このような従来の極性切換型ジョセフ
ソン駆動回路の問題点を除去し、回路の微細化が可能な
極性切換型ジlセフノン駆動回路を提供することにある
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the problems of the conventional polarity switching type Josephson drive circuit and to provide a polarity switching type dilcefnon drive circuit which allows miniaturization of the circuit.

〔肱題を解決するための手段〕[Means to solve the problem]

本発明によれは、バイアス入力端に第一の直接結合型ジ
ョセフソンゲート回路のバイアス入力端が接続され、前
記第一の直接結合型ジ目セフソングート回路の出力端に
負荷抵抗を介して第二の直接結合型ジョセ7ンンゲート
回路のバイアス入力端が接続され、信号入力端に第一の
入力抵抗を介して前記第一の直接結合型ジョセフソンケ
ート回路の信号入力端が接続され、か」記信号入力鴻に
第二の入力抵抗を介して前記第二の直接結合型ジョセフ
ソンケート回路の信号入力端が接続され、前記第二の直
接結合型ショセフノノゲート回路の出力端が出力端に接
続されてなる第一〇駆動電圧発生回路と、前記第一の駆
動電圧発生回路と同一の回路構成を南する第二の駆動電
圧発生回路と、前記第一及び第二の駆動電圧発生回路の
出力端間に接続された被駆動線路とから構成される極性
切換型ジョセフソン駆動回路が得られる。
According to the present invention, the bias input terminal of the first direct coupling type Josephson gate circuit is connected to the bias input terminal, and the second bias input terminal is connected to the output terminal of the first direct coupling type Josephson gate circuit via a load resistor. The bias input terminal of the direct coupling type Josephsongate circuit is connected to the bias input terminal of the direct coupling type Josephson gate circuit, and the signal input terminal of the first direct coupling type Josephson gate circuit is connected to the signal input terminal via a first input resistor, and The signal input terminal of the second direct coupling type Josephsongate circuit is connected to the signal input terminal through a second input resistor, and the output terminal of the second direct coupling type Josephsongate circuit is connected to the output terminal. 10 drive voltage generation circuits connected to each other, a second drive voltage generation circuit having the same circuit configuration as the first drive voltage generation circuit, and the first and second drive voltage generation circuits. A polarity-switchable Josephson drive circuit is obtained, which includes a driven line connected between the output terminals.

〔実施例〕〔Example〕

第1図は、本発明の一実施例を説明するための等価回路
図である。
FIG. 1 is an equivalent circuit diagram for explaining one embodiment of the present invention.

第1図に示す実施例は、2個のllAl#J電圧発生回
路(1,2)と、メモリセルアレイからなる被動す線路
3と、メモリセルアレイ4のリターン之イ15からなる
被ll1AIJJ線路と、抵抗比とから構成され、第一
の駆動電圧発生回路IAの出力端01Aと抵抗比の一端
に被駆動線路3が接続され、抵抗Rの他端と第二の駆動
電圧発生回路2人の出力端02Aに被駆動線路であるリ
ターンライン5が接続された構成を有する。第一、第二
の駆動電圧発生回路は同一の回路構成を肩しているので
、以下、第一の駆動電圧発生回路を例として説明する。
The embodiment shown in FIG. 1 includes two llAl#J voltage generating circuits (1, 2), a driven line 3 consisting of a memory cell array, a driven ll1AIJJ line consisting of a return line 15 of a memory cell array 4, The driven line 3 is connected to the output terminal 01A of the first drive voltage generation circuit IA and one end of the resistance ratio, and the output of the two second drive voltage generation circuits is connected to the other end of the resistor R. It has a configuration in which a return line 5, which is a driven line, is connected to the end 02A. Since the first and second drive voltage generation circuits have the same circuit configuration, the first drive voltage generation circuit will be described below as an example.

第一の駆動電圧発生回路1は、2個のジョセフンン接合
Jll、J12と抵抗比110からなる第一の直接結合
型シミセフノンゲート回路Gllと、2個のジ1セフン
ン接合J13.J14と抵抗比120からなる第二の直
接結合型ジョセフソンゲート回路012と、第一の入力
抵抗kL11、第二の入力抵抗R12と、負荷抵抗R1
3とで構成される。第一の直接結合型ジョセフソンゲー
ト回路G11の出力端011に負荷抵抗R13を介して
第二の直接結合型ジ町セフソンゲート回路G12のバイ
アス入力端B12が接続され、第一の直接結合型シ日セ
フノンゲート回路(jllの信号入力端811に第一、
第二の入力抵抗比11.凡12を介して第二の直接結合
型ジョセフソンゲート回路G12の信号入力端812が
接続されている。ここで、第一の入力抵抗R11は第二
の入力抵抗R12に比べて小さいとする。
The first drive voltage generation circuit 1 includes a first direct coupling type non-gate circuit Gll consisting of two Josephson junctions Jll, J12 and a resistance ratio of 110, and two di-1cefun junctions J13. A second direct coupling type Josephson gate circuit 012 consisting of J14 and a resistance ratio of 120, a first input resistance kL11, a second input resistance R12, and a load resistance R1.
It consists of 3. A bias input terminal B12 of a second direct coupling type Josephson gate circuit G12 is connected to the output terminal 011 of the first direct coupling type Josephson gate circuit G11 via a load resistor R13. Cefnon gate circuit (first at the signal input terminal 811 of jll,
Second input resistance ratio 11. A signal input terminal 812 of a second direct-coupled Josephson gate circuit G12 is connected through the line 12. Here, it is assumed that the first input resistance R11 is smaller than the second input resistance R12.

本実施例の極性切換型ジョセフソン駆動回路は、直接結
合型のジョセフソンゲート回路のみで形成されているの
で従来の技術で示した磁界結合型のジョセフソンゲート
回路に比べて回路の面積を大幅に減少させることができ
る。
Since the polarity switching type Josephson drive circuit of this embodiment is formed only with a direct coupling type Josephson gate circuit, the circuit area can be significantly reduced compared to the magnetic field coupling type Josephson gate circuit shown in the conventional technology. can be reduced to

本実施例の極性切換型ジョセフソン駆動回路の動作原理
は以下の如くである。
The operating principle of the polarity switching type Josephson drive circuit of this embodiment is as follows.

バイアス入力端BIAからバイアス電流を供給した状態
で、信号入力端81AK第2図で示したような立ち上が
シ時間Tの入力信号電流を入力すると、入力信号電流は
第一、第二の入力抵抗all。
When a bias current is supplied from the bias input terminal BIA and an input signal current with a rising time T as shown in FIG. resistance all.

凡12の比に分流されて第一、第二の直接結合型ジョセ
フソンゲート回路Gll、G12の入力端S11.81
2に流れる。今ここで入力抵抗R11゜R12の比を1
対2にするとゲート回路G11゜G12の入力端に流れ
る電流値は第2図の破線で1 示したように一1N、−¥INとなる(INは端子SI
Aから入力される入力電流値である)、第2図において
、ICは直接結合型ジョセフソンケート回路(jll、
G12が超伝導状態から電圧状態にスイッチする臨界電
流値である。従って、第一の駆動電圧発生回路1におい
て、直接結合型ジョセフソンケート回路Gllのジョセ
フソン接合J11゜J12が時刻T1で超伝導状態から
電圧状態にスイッチし、バイアス電流は抵抗R13を通
して直接結合型ジョセフソンケート回路G12のジョセ
フソン接合J13に流れ(但し、R110<R13とす
る)、その後時刻T2でジョセフソン接合J13、J1
4が超伝導状態から電圧状態にスイッチしく但し、R1
20<Rとする)、バイアス電流は被駆動線路3に注入
される。被駆動線路3に流れたバイアス電流は、駆動電
圧発生回路2のジョセフソン接合J23を通って接地に
流れ込む。このとき端子81Aから入力された信号は、
駆動電圧発生回路1において、ジョセフソン接合J12
゜J14が電圧状態にスーツチした時点で抵抗凡12゜
R120を通って接地に流れるためバイアス電流との入
出力分離が計られている。以上の動作により被駆動線路
に時計回り方向に出力電iを発生させることができる。
The input terminals S11.81 of the first and second directly coupled Josephson gate circuits Gll and G12 are divided into a ratio of approximately 12.
It flows to 2. Now, set the ratio of input resistance R11゜R12 to 1
When the pair is 2, the current value flowing to the input terminal of the gate circuit G11°G12 becomes -1N, -\IN, as shown by the broken line in Figure 2 (IN is the terminal SI
In Fig. 2, the IC is a direct-coupled Josephsongate circuit (jll,
G12 is the critical current value for switching from the superconducting state to the voltage state. Therefore, in the first drive voltage generation circuit 1, the Josephson junctions J11 and J12 of the direct-coupled Josephson gate circuit Gll switch from the superconducting state to the voltage state at time T1, and the bias current is transferred to the direct-coupled type through the resistor R13. The flow flows to Josephson junction J13 of Josephson gate circuit G12 (however, R110<R13), and then at time T2 Josephson junctions J13 and J1
4 switches from the superconducting state to the voltage state. However, R1
20<R), a bias current is injected into the driven line 3. The bias current flowing through the driven line 3 flows into the ground through the Josephson junction J23 of the drive voltage generating circuit 2. At this time, the signal input from terminal 81A is
In the drive voltage generation circuit 1, Josephson junction J12
When J14 reaches the voltage state, it flows to ground through resistor R120, so that the input and output are separated from the bias current. The above operation allows the output current i to be generated in the clockwise direction on the driven line.

一方、バイアス入力端B2Aからバイアス電流を供給し
た状態で、信号入力端82Aに第2図で示したような立
ち上がシ時間Tの入力信号電流を入力すると、駆動電圧
発生回路2において、直接結合型ジョセフソンケート回
路G21のジョセフソン接合J21 、J22が時刻T
1で超伝導状態から電圧状態にスイッチし、バイアス電
流は抵抗R23を通して直接結合型ジョセフソンゲート
回路G22のジョセフソン接合J23に流れ、その後時
刻T2でジョセフソン接合J23゜J24が超伝導状態
から電圧状態にスイッチし、バイアス電流Fi被駆動線
路5に注入される。被駆動線路Kfiれたバイアス電流
は、駆動電圧発生回路1のジョセフソン接合J13を通
って接地に流れ込む。このとき端子S2Aから入力され
た信号は、駆動電圧発生回路2において、ジョセフソン
接合J22.J24が電圧状態にスイッチした時点で抵
抗ル22.R220を通って接地に流れるためバイアス
電流との入出力分離が計られている。以上の動作によシ
被駆動線路に反時計回り方向に出力電流を発生させるこ
とができる。ここで、入力抵抗凡11とル21.R12
とR22値は上で述べたように、直接結合型ジョセフソ
ンケート回路G11゜G21が電圧状態にスイッチして
その出力電流を直接結合型ジラセフソンゲート回路01
2 、G22のバイアス端に入力した後、入力信号によ
り直接結合型ジョセフソンゲート回路G12.G22が
電圧状態にスイッチするように決定する必要がある。
On the other hand, when a bias current is supplied from the bias input terminal B2A and an input signal current with a rising time T shown in FIG. The Josephson junctions J21 and J22 of the coupled Josephson Kate circuit G21 are at time T.
1, the bias current flows through the resistor R23 to the Josephson junction J23 of the direct-coupled Josephson gate circuit G22, and then at time T2, the Josephson junction J23~J24 switches from the superconducting state to the voltage state. A bias current Fi is injected into the driven line 5. The bias current flowing through the driven line Kfi flows through the Josephson junction J13 of the drive voltage generating circuit 1 to ground. At this time, the signal input from the terminal S2A is sent to the Josephson junction J22. When J24 switches to the voltage state, resistor L22. Since it flows to ground through R220, the input and output are separated from the bias current. By the above operation, an output current can be generated in the driven line in the counterclockwise direction. Here, the input resistances are 11 and 21. R12
As mentioned above, the value of R22 is determined by the direct coupling type Josephson gate circuit G11゜G21 switching to the voltage state and transmitting its output current to the direct coupling type Josephson gate circuit 01.
2. After inputting to the bias end of G22, the input signal causes a direct coupling type Josephson gate circuit G12. It is necessary to decide for G22 to switch to the voltage state.

本実施例の極性切換型ジョセフソン駆動回路を広い動作
マージ/で動作させるためには、例えば以下のように回
路定数を決定すればよい。
In order to operate the polarity switching type Josephson drive circuit of this embodiment with a wide operation margin, circuit constants may be determined as follows, for example.

11:I3.I2:I4.II/2<I2<11R11
(=R21)<R12(=R22)ここで、IO,I2
.I3.I4はジョセフソン接合JllとJ21.J1
2とJ22.J13とJ23.J14とJ24の超伝導
臨界電流値である。
11:I3. I2:I4. II/2<I2<11R11
(=R21)<R12 (=R22) where IO, I2
.. I3. I4 is a Josephson junction Jll and J21. J1
2 and J22. J13 and J23. These are the superconducting critical current values of J14 and J24.

以上説明したように、本実施例によシ回路のしイアウド
面積が小さくなり高集積化が可能な極相切換型ジョセフ
ソン駆動回路を実現することができる。
As described above, according to the present embodiment, it is possible to realize a pole phase switching type Josephson drive circuit in which the area of the circuit is reduced and high integration is possible.

本冥施例においては被駆動線路中に抵抗5を挿入したが
、この代わ〕にジョセフソン接合で構成されるリセット
ゲートを用いても同様の効果を荀ることができる。
In this embodiment, the resistor 5 is inserted into the driven line, but the same effect can be obtained by using a reset gate composed of a Josephson junction instead.

なお、一実施例においてジ1セフンンIE’合Jl I
J12、・・・の代シにそれぞれこれらを複数個、例え
ば41!直列に接続したものを使用してもよい。
In addition, in one embodiment, the
J12, . . . have a plurality of these, for example 41! Those connected in series may also be used.

回路の動作時間は記憶セルアレイからなる被駆動線路の
インダクタンスをL1駆動電圧をV、駆動電流(出力電
流)をIとすると、LI/Vで評価することができる。
The operating time of the circuit can be evaluated by LI/V, where the inductance of the driven line consisting of the memory cell array is V and the drive current (output current) is V and I is the drive current (output current).

駆動電圧Vは、ジョセフソン接合が電圧状態にスイッチ
したときの発生電圧である。従って、ジョセフソン接合
を複数個直列接続することで一実施例に比べて被数倍の
駆動電圧を発生し、動作時間の短縮化が可能となる。
The drive voltage V is the voltage generated when the Josephson junction switches to a voltage state. Therefore, by connecting a plurality of Josephson junctions in series, it is possible to generate a driving voltage several times higher than that in one embodiment, and to shorten the operating time.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明により、回路の微細化と高速
動作が可能な極性切換型ジョセフソン駆動回路を実現す
ることができる。
As described above, according to the present invention, it is possible to realize a polarity switching type Josephson drive circuit that is capable of miniaturizing the circuit and operating at high speed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明による極性切換型ジョセフノン駆動回
路の一実施例を説明するだめの等価回路図、第2図は、
本発明による極性切換型ジコセフノン駆動回路の動作原
理を説明するための入力電流波形を示した概略図、第3
図は、従来の技術による極性切換型ジョセフソン駆動回
路を説明するための等価回路図である。 1・・・第一の駆動電圧発生回路、2・・・第二の駆動
電圧発生回路、3・・・被lIA動線路、4・・・メモ
リセルアレイ、5・・・リターンライン、BIA、Bl
l、B12、B2A、B21.B22−・・バイアス入
力端、01〜G4・・・磁界結合型ジョセフソンケート
回路、Gll・・・第一の駆動電圧発生回路の第一の直
接結合型ジョセフソンゲート回路、G12・・・第一の
駆動電圧発生回路の第二の直接結合型ショセフンングー
ト回路、G21・・・第二の駆動電圧発生回路の第一の
直接結合型ジョセフソンゲート回路、G22・・・第二
の駆動電圧発生回路の第二の直接結合型シ百セフソンゲ
ート回路、 Jll、J12.J13゜J14.J21
.J22.J23.J24・・・ジョセフソン接合、M
1〜MN・・・メモリセル、011,012゜(1)I
A、021,022.U2A−ffi力!、R11−・
・1の第一の入力抵抗、1(12・・・1cD第二の入
力抵抗、R21・・・2の第一の入力抵抗、凡22・・
・2の第二の入力抵抗、81.81人、52,82A・
・・信号入力端。
FIG. 1 is an equivalent circuit diagram illustrating an embodiment of the polarity switching type Joseph Non drive circuit according to the present invention, and FIG.
A schematic diagram showing an input current waveform for explaining the operating principle of the polarity switching type zicocefnon drive circuit according to the present invention.
FIG. 1 is an equivalent circuit diagram for explaining a polarity switching type Josephson drive circuit according to the prior art. DESCRIPTION OF SYMBOLS 1...First drive voltage generation circuit, 2...Second drive voltage generation circuit, 3...IIA flow line, 4...Memory cell array, 5...Return line, BIA, Bl
l, B12, B2A, B21. B22--bias input terminal, 01-G4...magnetic field coupling type Josephson gate circuit, Gll...first direct coupling type Josephson gate circuit of the first drive voltage generation circuit, G12...th A second direct-coupled Josephson gate circuit of the first drive voltage generation circuit, G21...a first direct-coupling Josephson gate circuit of the second drive voltage generation circuit, G22...second drive Second Directly Coupled Sefson Gate Circuit of Voltage Generating Circuit, Jll, J12. J13゜J14. J21
.. J22. J23. J24...Josephson junction, M
1~MN...Memory cell, 011,012°(1)I
A, 021,022. U2A-ffi power! , R11-・
・First input resistance of 1, 1 (12...1cD second input resistance, R21...2 first input resistance, about 22...
・Second input resistance of 2, 81.81 people, 52,82A・
...Signal input terminal.

Claims (1)

【特許請求の範囲】[Claims] バイアス入力端に第一の直接結合型ジョセフソンゲート
回路のバイアス入力端が接続され、前記第一の直接結合
型ジョセフソンゲート回路の出力端に負荷抵抗を介して
第二の直接結合型ジョセフソンゲート回路のバイアス入
力端が接続され、信号入力端に第一の入力抵抗を介して
前記第一の直接結合型ジョセフソンゲート回路の信号入
力端が接続され、前記信号入力端に第二の入力抵抗を介
して前記第二の直接結合型ジョセフソンゲート回路の信
号入力端が接続され、前記第二の直接結合型ジョセフソ
ンゲート回路の出力端が出力端に接続されてなる第一の
駆動電圧発生回路と、前記第一の駆動電圧発生回路と同
一の回路構成を有する第二の駆動電圧発生回路と、前記
第一及び第二の駆動電圧発生回路の出力端間に接続され
た被駆動線路とから構成されることを特徴とする極性切
換型ジョセフソン駆動回路。
A bias input terminal of a first direct-coupled Josephson gate circuit is connected to the bias input terminal, and a second direct-coupled Josephson gate circuit is connected to the output terminal of the first direct-coupled Josephson gate circuit via a load resistor. A bias input terminal of the gate circuit is connected, a signal input terminal of the first direct coupling type Josephson gate circuit is connected to the signal input terminal via a first input resistor, and a second input terminal is connected to the signal input terminal. A first drive voltage, in which the signal input terminal of the second direct-coupled Josephson gate circuit is connected to the output terminal of the second direct-coupled Josephson gate circuit, and the output terminal of the second direct-coupled Josephson gate circuit is connected to the output terminal. a generating circuit, a second driving voltage generating circuit having the same circuit configuration as the first driving voltage generating circuit, and a driven line connected between the output terminals of the first and second driving voltage generating circuits. A polarity switching type Josephson drive circuit comprising:
JP9341290A 1990-04-09 1990-04-09 Polarity switching type josephson driving circuit Pending JPH03291017A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9341290A JPH03291017A (en) 1990-04-09 1990-04-09 Polarity switching type josephson driving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9341290A JPH03291017A (en) 1990-04-09 1990-04-09 Polarity switching type josephson driving circuit

Publications (1)

Publication Number Publication Date
JPH03291017A true JPH03291017A (en) 1991-12-20

Family

ID=14081587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9341290A Pending JPH03291017A (en) 1990-04-09 1990-04-09 Polarity switching type josephson driving circuit

Country Status (1)

Country Link
JP (1) JPH03291017A (en)

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