JPH0328757U - - Google Patents

Info

Publication number
JPH0328757U
JPH0328757U JP8971589U JP8971589U JPH0328757U JP H0328757 U JPH0328757 U JP H0328757U JP 8971589 U JP8971589 U JP 8971589U JP 8971589 U JP8971589 U JP 8971589U JP H0328757 U JPH0328757 U JP H0328757U
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
metal plate
thin metal
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8971589U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8971589U priority Critical patent/JPH0328757U/ja
Publication of JPH0328757U publication Critical patent/JPH0328757U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】
第1図は本考案の一実施例の半導体集積回路装
置の斜視図、第2図は第1図の断面図、第3図は
従来の半導体集積回路装置の斜視図、第4図は第
3図の断面図である。 1,1′……半導体集積回路素子、2,2′…
…リードフレーム、3,3′……プラスチツク樹
脂、4,4′……リード、5,5′……ボンデイ
ングワイヤ。

Claims (1)

    【実用新案登録請求の範囲】
  1. 複数の半導体集積回路素子を搭載し、樹脂封止
    してなる半導体集積回路装置において、第一の金
    属薄板の主表面に第一の半導体集積回路素子が固
    着され、第二の金属薄板の主表面に第二の半導体
    集積回路素子が固着され、前記第一の金属薄板と
    第二の金属薄板が互いに対向していることを特徴
    とする半導体集積回路装置。
JP8971589U 1989-07-28 1989-07-28 Pending JPH0328757U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8971589U JPH0328757U (ja) 1989-07-28 1989-07-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8971589U JPH0328757U (ja) 1989-07-28 1989-07-28

Publications (1)

Publication Number Publication Date
JPH0328757U true JPH0328757U (ja) 1991-03-22

Family

ID=31639284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8971589U Pending JPH0328757U (ja) 1989-07-28 1989-07-28

Country Status (1)

Country Link
JP (1) JPH0328757U (ja)

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