JPH03286539A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03286539A JPH03286539A JP8860990A JP8860990A JPH03286539A JP H03286539 A JPH03286539 A JP H03286539A JP 8860990 A JP8860990 A JP 8860990A JP 8860990 A JP8860990 A JP 8860990A JP H03286539 A JPH03286539 A JP H03286539A
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- metal
- gaas
- resist
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 10
- 230000003287 optical effect Effects 0.000 claims description 13
- 238000005530 etching Methods 0.000 abstract description 3
- 230000008021 deposition Effects 0.000 abstract 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 3
- 239000004926 polymethyl methacrylate Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、GaAsFET、HEMT等の半導体装置
の製造方法に関し、特にゲート電極形式方法を提供する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing semiconductor devices such as GaAsFETs and HEMTs, and particularly provides a gate electrode type method.
第2図は従来の半導体装置の製造方法の製造工程を示す
断面図である。FIG. 2 is a cross-sectional view showing the manufacturing process of a conventional semiconductor device manufacturing method.
初めに第2図(a)のように、まずGaAs半絶縁性基
板(1)の上に活性層(2)を成長させ、活性層(2)
上にオーミック性電極のソース電極(3)、ドレイン電
極(4)をリフトオフ法により形成する。次に第2図(
blのようにゲートパターン形成用のフォトレジスト(
EB直接描画を行う場合は、P MM Aフォトレジス
ト(7))をGaAs基板(1)上に塗布し、EB直接
描画等で、写真製版を行い所定のパターンを形成した後
、エツチングによりリセス(8)を形成する。次に第2
図(C)のように、ゲート電極用金属(9)を全面に蒸
着した後に、第2図fd)のようにリフトオフ法により
、フォトレジスト(7)、ゲート金属(9)の不用部分
を除去し、ゲート形成を行う。First, as shown in FIG. 2(a), an active layer (2) is grown on a GaAs semi-insulating substrate (1).
A source electrode (3) and a drain electrode (4), which are ohmic electrodes, are formed thereon by a lift-off method. Next, Figure 2 (
Photoresist for gate pattern formation like bl (
When performing EB direct writing, a PMM A photoresist (7)) is applied onto the GaAs substrate (1), photolithography is performed using EB direct writing, etc. to form a predetermined pattern, and then a recess (7) is formed by etching. 8). Then the second
As shown in Figure (C), after depositing the gate electrode metal (9) on the entire surface, the unnecessary parts of the photoresist (7) and gate metal (9) are removed by lift-off method as shown in Figure 2 (fd). Then perform gate formation.
従来の半導体装置の製造方法は以上のように形成されて
いたので、ゲート形成を行う場合、GaAsFET、H
EMT等の素子の性能を向上させるためのケート長(L
g )が0.25μm以下のパターンには光学露光では
困難であるため、EB直接描画が必要となる。しかし、
EB直接描画を行うには、従来の光学用フォトレジスト
に代わり、P M M A等のEB用のフォトレジスト
が必要となる。このEB用フォトレジストは従来の光学
用フォトレジストに比べ、 GaAsとの密着性が劣る
他、耐プラズマ性も悪く、エツチングを行ったとき、液
の浸み込み、又RIE等のプラズマによるフォトレジス
トの膜ベリがあるなどの問題点があった。Conventional semiconductor device manufacturing methods have been formed as described above, so when forming gates, GaAsFET, H
Cate length (L) to improve the performance of elements such as EMT
Since optical exposure is difficult to produce patterns with g ) of 0.25 μm or less, direct EB writing is required. but,
To perform EB direct writing, an EB photoresist such as PMMA is required in place of the conventional optical photoresist. Compared to conventional optical photoresists, this EB photoresist has poor adhesion to GaAs and poor plasma resistance, and when etching is performed, liquid may seep in, and photoresists exposed to plasma during RIE etc. There were problems such as the film being stained.
この発明は、上記のような問題点を解消するためになさ
れたもので、GaAsとフォトレジストとの密着性及び
耐プラズマ性の向上を図ることを目的とする。This invention was made to solve the above-mentioned problems, and aims to improve the adhesion between GaAs and photoresist and the plasma resistance.
本発明に係る半導体装置の製造方法は、GaAs基板上
のフォトレジストにGaAsとの密着性の高い光学用フ
ォトレジスト用い、その上に、光学用フォトレジストの
マスクドして用いる遮光用のTiorCr等の金属を入
れ、最上部にEB用フォトレジストを塗布したものであ
る。The method for manufacturing a semiconductor device according to the present invention uses an optical photoresist with high adhesion to GaAs as a photoresist on a GaAs substrate, and on top of that, a light shielding layer such as TiorCr used as a mask for the optical photoresist is applied. A metal is inserted and an EB photoresist is applied to the top.
即ち、最上部のEB用フォトレジストは、EB直接描画
により露光を、1層目の光学用フォトレジストは、遮光
用の金属をマスクとして全面露光を行う。That is, the uppermost EB photoresist is exposed to light by EB direct writing, and the first layer of optical photoresist is exposed to light using a light-shielding metal as a mask.
この発明における半導体装置の製造方法は、GaAs基
板上のフォトレジストにGaAsと密着性の高い光学用
フォトレジストを用いフォトレジストの密着性を向上さ
せるとともに、遮光用の金属をマスクドするため、微細
パターンのマスク合わせが不用となる。The method for manufacturing a semiconductor device according to the present invention improves the adhesion of the photoresist by using an optical photoresist that has high adhesion to GaAs as the photoresist on the GaAs substrate, and also uses a fine pattern to mask the light-blocking metal. Mask alignment is no longer necessary.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図(a)〜(f+はこの発明の一実施例である半導
体装置の製造方法のゲート形成の主要部分の製造工程を
示す断面図である。FIGS. 1(a) to 1(f+) are cross-sectional views showing the manufacturing process of the main part of gate formation in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
まず、第1図(a)のように、GaAs半絶縁性基板(
1)上に活性層(2)を成長させ、その上に写真製版、
リフトオフ法を用いてソース電極(3)、ドレイン電極
(4)を形成し、その上にGaAs基板(1)と密着性
の高い光学用フォトレジスト(5)を塗布する。次に第
1図(b)のように、全面にTi 、Cr等の遮光用金
属(6)を蒸着、スパッタ等で形成する。次に、第1図
(C)のように、PMMA等のEB用フォトレジスト(
7)を塗布し、所定のパターンをEBで直接描画、現像
を行い、ゲートパターンを形成する。次に第1図fd)
のように、EB用フォトレジスト(7)をマスクとし、
Ti 、Cr等をエツチングする。その後、遮光用金属
Ti、Cr(61をマスクとして、全面露光、現像を行
い、パターンを形成する。このとき、微細パターンの形
成は、遮光金属をマスクとして行うため、マスク合わせ
は不要となり、精度の高い微細なパターンが形成できる
。次に第1図(e)のように、リセス(8)を形成した
後、ゲート金属(9)を蒸着等で形成する。次いで第1
図(f)のようにリフトオフ法にて、1層目の光学用フ
ォトレジスト(5)、遮光用金属(6)、EB用フォト
レジスト(7)、及びゲート金属(9)の不用部分を除
去し、ゲート電極を形成する。First, as shown in Figure 1(a), a GaAs semi-insulating substrate (
1) Grow an active layer (2) on top, photolithography on top of it,
A source electrode (3) and a drain electrode (4) are formed using a lift-off method, and an optical photoresist (5) having high adhesion to the GaAs substrate (1) is applied thereon. Next, as shown in FIG. 1(b), a light-shielding metal (6) such as Ti or Cr is formed on the entire surface by vapor deposition, sputtering, or the like. Next, as shown in FIG. 1(C), an EB photoresist such as PMMA (
7) is applied, a predetermined pattern is directly drawn using EB, and development is performed to form a gate pattern. Next, Figure 1fd)
Using the EB photoresist (7) as a mask,
Etch Ti, Cr, etc. After that, using the light-shielding metals Ti and Cr (61) as a mask, the entire surface is exposed and developed to form a pattern. At this time, since the fine pattern is formed using the light-shielding metal as a mask, mask alignment is not required, and accuracy is Next, as shown in FIG. 1(e), after forming a recess (8), a gate metal (9) is formed by vapor deposition or the like.
As shown in Figure (f), unnecessary parts of the first layer of optical photoresist (5), light shielding metal (6), EB photoresist (7), and gate metal (9) are removed using the lift-off method. Then, a gate electrode is formed.
以上のようにこの発明によればGaAs基板とEB用フ
ォトレジスト(PMMA)の間に、GaAsとの密着性
の優れた光学用フォトレジスト、及び遮光用のTior
Cr等の金属を入れることにより、EB用フォトレジス
トの密着性が向上し、またGaAs基板上の光学露光用
フォトレジストの露光は、EB用フォトレジストのパタ
ーンで形成された遮光用金属の開口部をマスクとして行
うので、マスク合わせが不用で、全面露光ができ、微細
なパターンが精度よく形成できるという効果が有る。As described above, according to the present invention, between the GaAs substrate and the EB photoresist (PMMA), an optical photoresist with excellent adhesion to GaAs and a Tior for light shielding are used.
By adding a metal such as Cr, the adhesion of the EB photoresist is improved, and the exposure of the optical exposure photoresist on the GaAs substrate is performed through the opening of the light-shielding metal formed in the pattern of the EB photoresist. Since this is performed using a mask, there is no need for mask alignment, the entire surface can be exposed, and a fine pattern can be formed with high precision.
第1図はこの発明の一実施例による半導体装置の製造方
法の製造工程を示す断面図、第2図は従来の半導体装置
の製造方法の製造工程を示す断面図である。
図において、(1)はGaAs半絶縁性基板、(2)は
活性層、(3)はソース電極、(4)はトレイン電極、
(5)は光学用フォトレジスト、(6)は遮光用金属(
Ti’orCr)、(7)はEB用フォトレジスト、(
8)はリセス、(9)はゲート金属である。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a sectional view showing the manufacturing process of a semiconductor device manufacturing method according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the manufacturing process of a conventional semiconductor device manufacturing method. In the figure, (1) is a GaAs semi-insulating substrate, (2) is an active layer, (3) is a source electrode, (4) is a train electrode,
(5) is an optical photoresist, (6) is a light-shielding metal (
(Ti'orCr), (7) is a photoresist for EB, (
8) is a recess, and (9) is a gate metal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
フォトレジストと、遮光用のTiorCr等の金属を用
いたことを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, characterized in that an optical photoresist and a light-shielding metal such as TiorCr are used between the GaAs substrate and the EB photoresist.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8860990A JPH03286539A (en) | 1990-04-02 | 1990-04-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8860990A JPH03286539A (en) | 1990-04-02 | 1990-04-02 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03286539A true JPH03286539A (en) | 1991-12-17 |
Family
ID=13947556
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8860990A Pending JPH03286539A (en) | 1990-04-02 | 1990-04-02 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03286539A (en) |
-
1990
- 1990-04-02 JP JP8860990A patent/JPH03286539A/en active Pending
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