JPH03285483A - Scanning line number converting device - Google Patents

Abstract

PURPOSE:To execute the thin-out processing and interpolation processing of picture data by using a common circuit by sending out interpolation data, which is supplied to an output control circuit at the timing of a reference clock, as transforming picture data at the timing of inputting an output clock signal. CONSTITUTION:Until shift control signals S31 and S32 are inputted, picture data DA-DE held in a shift register 35 are successively read out at the timing of a reference clock CKREF, and interpolation data AD composed by weighting the picture data DA-DE with coefficient data CA-CE is read out at the timing of an output clock CKOUT as transforming picture data DATAOUT from an output control circuit 39. Thus, the number of scanning lines can be transformed by the thin-out processing and interpolation processing of the picture data DATAIN while using the common circuit.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B. Overview of the invention C. Conventional technology (Figures 8 to 10) D. What the invention attempts to solve! l! Means for solving the EIK problem (Figures 1 to 3) F effects (Figures 4 to 7) G example (G1) Pre-processing and post-processing of luminance signals and color signals (Figures 1 and 7) (Figure 2) (G2) Configuration of line number conversion filter 23.23X (Figure 3) (G3) Line number thinning processing (Figures 4 and 5) (G4
) Line number interpolation processing (Figures 6 and 7) (G5) Effects of the embodiment (G6) Other embodiments H Effects of the invention A Field of industrial application The present invention relates to a scanning line number conversion device, for example, The present invention is suitable for transmitting and receiving image data between television transmission systems having different numbers of lines.

B. Summary of the Invention The present invention provides a scanning line number conversion device in which the shift register and output control circuit are controlled based on a reference clock, thereby thinning out sequentially input image data using the same circuit. The converted image data can be converted into converted image data having a different number of scanning lines through processing or interpolation processing.

C. Conventional technology Conventionally, in video telephone systems and conference telephone systems, relatively severe limitations on transmission capacity have been achieved by highly efficient encoding of video signals consisting of moving a video into intra-frame encoded data and inter-frame encoded data. A video signal transmission system has been proposed in which a moving image signal is transmitted through a certain transmission path (Japanese Patent Laid-Open No. 1183/1983).

In other words, this video signal transmission system is, for example, shown in FIG.
As shown in A), time t=t, , ti, t,...
Each image PCI, PO2, which constitutes a video in ...
When trying to transmit PO2..., the transmission efficiency can be improved by compressing the image data to be transmitted, taking advantage of the fact that the video signal has a large autocorrelation over time. It performs processing to enhance the image quality, and intra-frame encoding processing is performed on the image PCI, PO2, PO2...
For example, the pixel data of each image PCI, PO2, PO2, etc. is compressed by comparing it with a predetermined reference value to find the difference between the pixel data in the same frame. A compressed amount of image data is transmitted using the autocorrelation of .

In addition, as shown in FIG. 8(B), the interframe encoding process sequentially processes the adjacent images
2... Find image data PC12, PO23... consisting of the difference in pixel data between them, and calculate this at time t.
``' t The initial image PCI in r is transmitted together with the image data subjected to intra-frame encoding processing.

In this way, the images PCI, PO2, PO2, etc. can be encoded with high efficiency into digital data with a much smaller amount of data than in the case of transmitting all the image data, and can be sent to the transmission path. .

Such video signal encoding processing is executed in the image data generation device 1 having the configuration shown in FIG.

The image data encoding bag f1 processes the input video signal VDIN in the preprocessing circuit 2 to perform processing such as one field drop processing and one field line thinning processing, and then converts the luminance signal and chroma signal into 16 pixels (horizontally )
A transmission unit block (this is called a macroblock) consisting of data for X16N elements (in the vertical direction) is converted into input image data Sll formed by sequentially arranging time series, and the image data code Kitai W! Supply to 3.

The image data encoding circuit 3 generates interframe encoded data by receiving the predicted current frame data 312 formed in the predictive encoding circuit 4 and calculates the difference between the predicted current frame data 312 and the input image data Sll, and converts the data into interframe encoding mode. ), or by calculating the difference between input image data Sll and reference value data, intra-frame encoded data is formed (this is called intra-frame encoding mode), and this is used as difference data S13 in a transform encoding circuit. Supply to 5.

The transform encoding circuit 5 is constituted by a discrete cosine transform circuit, and sends out quantized image data S15 by supplying transform encoded data S14, which is obtained by orthogonally transforming the difference data 513 and encoding it with high efficiency, to the quantization circuit 6. let

The quantized image data S obtained from the quantization circuit 6 in this way
15 is subjected to high-efficiency encoding processing again in the retransformation encoding circuit 7 including a variable length encoding circuit, and then supplied to the transmission buffer memory 8 as transmission image data S16.

In addition, the quantized image data S15 is subjected to inverse quantization and inverse transform encoding processing in the predictive encoding circuit 4, so that it is decoded into difference data, and then the pre-prediction frame data is corrected using the difference data. In addition to saving new pre-prediction frame data, input image data S
By motion-compensating the pre-prediction frame data stored in the predictive encoding circuit 4 using motion detection data formed based on ll, predictive current frame data can be formed and supplied to the image data encoding circuit 3. done,
As a result, the difference between the input image data Sll of the frame to be currently transmitted (that is, the current frame) and the predicted current frame data S12 is obtained as difference data S13.

In the configuration of FIG. 9, when transmitting the moving image described above with reference to FIG. 8, first, the time point 1-1 of FIG. 8(A). When the image data of the image PCI is given as the input image data Sll, the image data encoding circuit 3 enters the intra-frame encoding mode and converts this into the intra-frame encoded difference data S13 to the transform encoding circuit 5. As a result, the transmission image data S16 is supplied to the transmission buffer memory 8 via the quantization circuit 6 and the re-conversion encoding circuit 7.

At the same time, the quantized image data S15 obtained at the output end of the quantization circuit 6 is subjected to predictive encoding processing in the predictive encoding circuit 4, so that the pre-prediction data representing the transmission image data 316 sent to the transmission buffer memory 8 is Frame data is held in the previous frame memory, and subsequently, when input image data Sll representing image PC2 is supplied to image data encoding circuit 3 at time 1-1t, motion compensation is applied to predicted current frame data S12, and image data The signal is supplied to the encoding circuit 3.

Thus, time point 1=1. Image data encoding circuit 3
supplies the inter-frame encoded difference data S13 to the conversion encoding circuit 5, thereby supplying the difference data representing the change in the image between the frames to the transmission buffer memory 8 as transmission image data S16, By supplying the quantized image data S15 to the predictive encoding circuit 4, pre-prediction frame data is formed and stored in the predictive encoding circuit 4.

The same operation is repeated thereafter, and while the image data encoding circuit 3 executes interframe encoding processing, only the difference data representing the change in the image between the previous frame and the current frame is stored in the transmission buffer memory. 8 will be sent out sequentially.

The transmission buffer memory 8 stores the transmission image data S16 sent out in this way, and sequentially transfers the accumulated transmission image data SI6 to the transmission data D□ at a predetermined data transmission rate determined by the transmission capacity of the transmission path 9. . , and transmit it to the transmission line 9.

At the same time, the transmission buffer memory 8 detects the amount of remaining data and feeds back the remaining amount data S17 that changes according to the amount of remaining data to the quantization circuit 6, and performs a quantization step according to the remaining amount data S17. By controlling the size and adjusting the amount of data generated as the transmission image data S16, it is possible to maintain an appropriate amount of remaining data in the transmission buffer memory 8 (an amount of data that does not cause overflow or underflow). It is done like this.

Incidentally, when the remaining amount of data in the transmission buffer memory 8 increases to the allowable upper limit, by increasing the step size of the quantization step 5TPS (FIG. 10) of the quantization circuit 6 using the remaining amount data 517, By performing coarse quantization in the quantization circuit 6, the transmitted image data 5
16 data amount is reduced.

On the contrary, when the remaining amount of data in the transmission buffer memory 8 decreases to the allowable lower limit value, the remaining amount data S17 controls the step size of the quantization step 5TPS of the quantization circuit 6 to a small value. As a result, the quantization circuit 6
By performing fine quantization in the transmission image data S16, the amount of data generated for the transmission image data S16 is increased.

On the other hand, the image data decoding device 10 transfers the transmission data transmitted via the transmission line 9 to the transmission buffer memory 1.
Take it to 1 and accumulate it one by one.

The transmission buffer memory 11 sends the stored transmission data at a predetermined transmission rate to the reconversion inverse encoding circuit 12, which is a variable length inverse encoding circuit, as received image data S18. 518 is given to the dequantization circuit 13 as entertainment transform encoded image data S19 and dequantized to dequantized data S20, and then subjected to discrete inverse transform processing in the transform inverse encoder circuit 14 to become decoded image data 321. Decrypted.

This post-quantized image data 521 is post-processed in the post-processing circuit 15 and then sent out as an output video signal VDoot.

D Problems to be Solved by the Invention The image data generated by the image data encoding device 1 having the configuration shown in FIG. , when transmitting data to a remote location, or when communicating between areas using television systems with different numbers of scanning lines, the format of the transmission data D CI F (commo
It has been agreed internationally (CCITT recommendation) that the format should be converted to an intermedi dte format (CCITT recommendation).

If you do this, for example, you can access PA from an NTSC area.
From an area using L system to an area using PAL system, or vice versa, from an area using N
When transmitting the transmission data generation amount H5 to an area using the TSC system, the number of scanning lines is changed from the NTSC system to the CIF at the transmitter (i.e. encoder) in the NTSC system area.
The receiving device (i.e. decoder)
, the CIF system is converted to the NTSC system, and in the same way, the number of scanning lines is converted from the PAL system to the CIF system at the PAL system local transmitter, and the CIF system is converted to the PAL system at the receiver. For example, transmission data D? that has been highly efficiently encoded between regions using the NTSC method and between regions using the PAL method. LAN
! can communicate.

Generally, the scanning line number conversion method for television signals is as follows:
JP-A-61-140289 and JP-A-59-16
Although the methods disclosed in Japanese Patent No. 784 have been proposed, none of them can be directly applied to the case where image data is subjected to vibration processing on a macroblock-by-macroblock basis as in the case of high-efficiency encoding processing.

The present invention has been made in consideration of the above points, and we would like to propose a scanning line number conversion device that has the simplest possible configuration and is capable of converting the number of scanning lines in a manner that does not make image deterioration noticeable. That is.

Means for Solving Ellal In order to solve this problem, in the present invention, sequentially input image data D A T A I N is converted into converted image data D A having a different number of scanning lines from the image data D A T A r N. In the scanning line number conversion devices 23 and 23X that convert the image data DATA I to T Aoav, the image data DATA I is input at a timing that is an integral multiple of the reference clock CK□.
Shift control signal S3 supplied with N at the relevant timing]
and shift register 35 to be shifted based on S32.
and interpolated data A obtained by weighting the image data DATA and N read out from the shift register 35 for each input of the reference clock CKIEF, as the reference clock CK*tr.
The output clock signal C input at a timing that is an integer multiple of
Converted image data based on Kouy
ut, and the shift register 35 with the shift control signals S31 and S32, and the output control circuit 39 with the output clock signal CKoay.
A timing control circuit 40 is provided to send out converted image data DAT having a different number of scanning lines by thinning or interpolating the sequentially inputted image data DAT A+s.
Aout is sent.

The image data D1 to D1 held in the shift register 35 until the F-action shift control signals 331 and S32 are input.
DI is read out sequentially at the timing of the reference clock CK*tr, and the image data D, ~DE are converted into coefficient data C1~C.
The control circuit 3 outputs the interpolated data A weighted by 7.
By reading the converted image data DAT Aout from 9 at the timing of the output clock CKout, the number of scanning lines can be converted by thinning processing and interpolation processing of the image data D AT A I N using a common circuit. It can be executed by

G Embodiment (G1) Pre-processing and post-processing of luminance signals and chrominance signals Regarding the following drawings, the present invention is applied to image data decoding consisting of a pre-processing circuit 2 of an image data encoding device 1 consisting of an encoder and a decoder as shown in FIG. As the post-processing circuit 15 of the device 10, the NTS
The input video signal DIll of the C format is converted into the input image data S11 of the CIF format, and the decoded northwest image data S21 of the CIF format is converted to the output video signal VD0 of the NTSC format.
This will be described in detail as an example applied when converting to υi.

In this embodiment, the pre-processing circuit 2 and the post-processing circuit 15 are:
Luminance signal processing circuit 16 shown in FIG. 1 and FIG. 2, respectively.
and a color signal processing circuit 16X, and are configured to execute scanning line number conversion processing in line number conversion filters 23 and 23X, respectively.

The luminance signal processing circuit 16 (FIG. 1) receives the input video signal VD.
The luminance signal S22 separated as a component signal from +s (FIG. 9) is converted into an analog/digital conversion circuit 17.
After converting the luminance data signal S23 into a luminance data signal S23, it is written into the NTSC frame memory 20 through the prefilter 18 and the CI F/QCIF conversion circuit 19, and the NTSC
The NTSC luminance data signal S24 read from the C frame memory 20 by a clock having an NTSC system clock frequency (this is called an NTSC clock) is applied to the line number conversion filter 23 via the switching circuit 22 of the scanning line number conversion circuit 21. The CIF brightness data signal S25 is converted into a CIF brightness data signal S25, and this CIF brightness data signal S25 is sent to the switching circuit 24.
A clock having a clock frequency of the CIF system (this is called a CIF clock) is written into the CIF frame memory 25 via the CIF frame memory 25, and this is sent out as a line number converted luminance data signal S26.

In addition to this, the luminance signal processing circuit 16 also processes decoded image data S21 obtained from the conversion and inverse encoding circuit 14 (FIG. 9).
CIF the received luminance data signal S27 obtained based on
CIF received in the frame memory 25 and read out from the relevant cIF frame memory 25 by the CIF clock.
The luminance data signal S28 is given to the line number conversion filter 23 via the switching circuit 24 to convert it into the NTSC luminance data signal S2.
This NTSC 1i degree data signal 329 is sent to the NTSC frame memory 20 via the switching circuit 22.
Write by SC clock.

The data stored in this NTSC frame memory 20 is NTSC.
CTF/QCIF conversion circuit 26, frame interpolation circuit 27, post filter 28
, and is sent out as a received luminance signal S30 through the digital/analog conversion circuit 29 in sequence.

Here, the NTSC frame memory 20 and the CIF frame memory 25 are respectively a pair of frame memories 20A and 20A.
0B, 25A, and 25B, and by reading the brightness data of one frame that arrives sequentially in the NTSC frame memory 20 and the CIF frame memory 25 alternately, while reading the data to one frame memory. This is done so that incoming data is not lost.

The color signal processing circuit 16X (Fig. 2) receives the input video signal V.
The color difference signals S22χ1 and 522X2 separated as component signals from D + N are converted into color difference data R in analog/digital conversion circuits 17x1 and 17X2.
-Y, B-Y, and then synthesized in the multiplexer circuit 30 and converted into a color data signal 523X, followed by a prefilter 18X, a vertical line thinning circuit 31,
After writing to the NTSC frame memory 20X sequentially through the F/QCIF conversion circuit 19X, the data is written to the NTSC frame memory 20X in the same manner as in the case of the luminance signal processing circuit 16.
The NTSC color data signal 524X read out from the NTSC clock using the NTSC clock is applied to the line number conversion filter 23X via the switching circuit 22X of the scanning line number conversion circuit 21X.
The CIF color data signal 525X is converted into an IF color data signal 525X, written into the CIF frame memory 25X via the switching circuit 24X using the CIF clock, and sent out as the line number converted color data signal 526X.

In addition, the color signal processing circuit 16X processes decoded image data 521 obtained from the conversion and inverse encoding circuit 14 (FIG. 9)
The received color data signal 527X obtained based on CIF
The CIF color data signal 528X received by the frame memory 25X and read out from the CIF frame memory 25 by the CIF clock is applied to the line number conversion filter 23X via the switching circuit 24X to generate the NTSC color data signal 528X.
9X, and this NTSC color data signal 529X is written into the NTSC frame memory 20X via the switching circuit 22X using the NTSC clock.

The data stored in this NTSC frame memory 20X is NT
CIF/QCI F read by SC clock
The conversion circuit 26χ, the frame interpolation circuit 27x, and the post filter 28X are sequentially inputted to the demultiplexer circuit 32, and then separated into color difference data R-Y and B-Y, and then sent through the digital/analog conversion surface 1129X1.29X2. The received color signal is transmitted as a received color signal 530X1.530X2.

Here, the NTSC frame memory 20X and the CIF frame memory 25X are each a pair of frame memories 20X.
A, 20
Frame memory 20X and CIF frame memory 25X
By alternately reading color data into one frame memory, it is possible to prevent data that arrives from being lost while reading color data to one frame memory.

Furthermore, the CIF/QCIF conversion circuits 19 and 19X (Figures 1 and 2) transmit brightness data and color data as they are in the IF format mode (normal transmission mode); QCI F format mode (
In the special transmission mode (transmission at a resolution of 1/4), the luminance data signal S23 and the color data signal 523X are thinned out to 1/2 in the V direction and the H direction, respectively.

(G2) Structure of the line number conversion filter 23.23X The line number conversion filters 23 and 23X, as shown in FIG.
It has a shift register 35 consisting of 5C, 135D and 35E, and inputs an image data signal D to its input stage shift circuit 35A.
The timing of shifting the shift register 35 is controlled by receiving shift enable signals 531 and 332 to the enable terminals of shift circuits 35A and 35B to 35E in each stage, respectively. ing.

That is, the shift register 35 receives the shift enable signal 5.
31 and S32 are logic "1", each time each clock of the reference clock signal CK□7 is input, the image data DA, DI to D1 stored in the shift circuit 1g35A, 35B to 35E of each stage is On the other hand, when the shift enable signals S31 and S32 are logic "0", the image data D, , D, -DE are not shifted and continue to be held even if the clock of the reference clock signal CK*tr is input. At the same time, the shift circuits 35A, 35B~ of each stage are activated at the clock timing of the reference clock signal CKl[F.
Image data D, D, ~DE stored in 35E
is sent to the next stage.

Incidentally, in the case of this embodiment, the period T□1 of the clock pulse of the reference clock signal CKxzy is equal to the period rr of the NTSC clock signal CKNTSC, (
173 (hereinafter referred to as the NTSC clock period) (FIG. 4 (A)) and 115 of the period T of the CIF clock signal CKCIF (hereinafter referred to as the CIF clock period)
(FIG. 4(C)).

The image data D, -D sent out from the shift circuits 35A-35E at the timing when the clock of the reference clock signal GK□ is input is the coefficient data C1 sent out from the coefficient circuits 37A-37E in the multiplication circuits 36A-36H, respectively. ~CE is multiplied, and the multiplied data M1 to M are sequentially added in addition circuits 38A to 38D and sent out as output interpolation data A and ~AD, and thus the output interpolation data Am of the final stage addition circuit 38D is used for output control. circuit 3
9.

Here, the coefficient circuits 37A to 37E have a ROM configuration, and the weights of the coefficient data C1 to C0 can be switched and set during thinning processing and interpolation processing by a coefficient control signal S33 specifying an address. -5/
256, Cwa”17/256, Cc-100/2
56, C, -80/256, and CE=54/256, which are sequentially set at the clock timing of the reference clock signal CKIEF so that the sum of the numerical values in the numerator becomes the numerical value in the denominator, that is, 256.

The output control circuit 39 converts the output interpolated data A supplied from the adder circuit 38D into line number converted image data D A T A when the output clock signals CKo and llt given from the timing control circuit 40 are logic rlJ.
On the other hand, when the logic is "0", it is not sent.

The timing control circuit 40 receives the reference clock signal CK IE.
, an address signal S supplied from a sequence circuit 41 that generates an address at the timing of the rising edge of the clock.
34, thereby converting the NTSC image data signal V D I N to C I N as described below.
Convert the line number conversion image data DATA, □ of the F method, or convert the image signal V D t )l of the CIF method to NTS
The image data is converted into line number converted image data DATAOヮ of the C method.

(G3) The line number thinning processing timing control circuit 40 converts the NTSC method ○ method 0-image data signal IN into CJF method line number conversion image data D.
When converting to A T A out, the clock signal CK, □ of the reference clock signal CK□ (Fig. 4 (B)
) at the timing of every 3 pulses (i.e. 3T□
,) shift enable signals S31 and S32 are supplied to shift circuits 35A and 35B to 35E.

As a result, for example, the reference clock signal CKIIEF shown in FIG.
. . ., the time point t3 when every third pulse occurs. (i
o, Lx, t6...), pixels for five lines (Ll, Lt, Ls, L4, L
S), (Lx, Lx, L4, Ls, La), (L
pixel data of s, L-, Ls, Lm, Lt) is held in the shift register 35 while being sequentially shifted by the five stages of shift circuits 35A to 35E (FIG. 4(A)). is being done.

At the same time, the timing control plane NI40 controls the clock signal CK*tr (fourth clock signal) of the reference clock signal CKIEF.
Output clock signals CK, .

As a result, the generation time t of the reference clock signal CK++tr
o, LI% tt, ts, old... Occurrence point of every 5 pulses 1-Sn (to, Ls, t+...
), 5 lines of pixel data (Lt, Lx, Ls
,L, ,LS), (L, ,L, ,L, ,L,,L
.

), (L, ,Ls ,L,,L,,L,),(L, ,
L'+, Lm, Ll, Lt. )... Multiplication circuits 36A to 36E and addition circuits 38A to 38
Output interpolated data A obtained by performing product-sum calculation in D.

is the line number converted image data D A from the output control circuit 39
The pixel data of each line of the CIF frame N, , Nt , Ns , is output as T Aout, and is thus stored in the CIF frame memory 25 as shown in FIG. 5(B).
N-... is written.

Incidentally, the CIF pixel data N1, N, obtained at this time
, N, , N4... is calculated by performing a product-sum operation to obtain N,=C,・L, +C,・Lx 10cC・L.

+C1・Lm +Ct −Ls ・・・・・・ (1) Nt =Ca ・Lm +CI ・Ls +
Cc -La+C9・L, +C,・L.

...... (2) N3-Cs -L, +Ci -Ls +Cc -L6
+Ctr-L? +CI ・Lm ...... (3) N, -C, ・Lm +c, ・L? 10c, L.

+C9・L, +C,・Lll+ ...... (4) Multiplying the coefficient data C1 to C1 by the five lines of NTSC pixel data held in the shift circuits 35A, 35B to 35E. Interpolated pixel data is obtained by weighting and adding.

In the configuration of FIG. 3, the period in which the shift enable signals 331 and S32 given to the shift circuits 35A to 35E are in the shift enable state is the NTSC clock signal CK.
, asc, it is possible to take in image data of the number of lines of the NTSC frame standard into the shift register 35.

In addition to this, since the period of the output clock signal CKOLIT is selected to be the period of the CIF clock CKCIF signal, CIF@raw data N8, Nz, which can be obtained as line number converted image data DATAour,
The number of lines of the CIF frame constituted by Ns... matches the CIF frame standard.

Thus, according to the configuration shown in FIG. 3, the number of lines in an NTSC frame can be converted to the number of lines in a CIF frame.

In this embodiment, the timing control circuit 40 generates a shift enable signal that controls the shift of the shift circuit 35A when the leading image data (or end image data) of the image data signal DATA is input to the input stage shift circuit 35A. S31 is controlled separately from the shift enable signal S32 that controls the shifts of the shift circuits 35B to 35B, and is set to logic "0".
” By holding the first image data (or the last image data) in the shift circuit 35A, the first image data (or the last image data) is sequentially transferred to the shift circuit 35B.
~35E to compensate for the lack of image data that occurs when the first image data is input (or when the last image data is sent), thereby preventing image quality deterioration at the beginning and end of the image data. It is done like this.

(G4) The line number interpolation processing timing control circuit 40 converts the CIF system image data signal VDIN into the NTSC system line number conversion image data D.
When converting to ATAOゎ, the reference clock signal C
KIIEF clock signal CK□.

(Figure 6 (B)), at the timing of every 5 pulses (
That is, with a period of 5T□2) shift enable signal S3
1, S32 is supplied to shift circuits 35A, 35B to 35E.

As a result, for example, the reference clock signal CKIEF shown in FIG.
. . ., the occurrence time point t2 of every 5 pulses. (to
, ts, t+o--), five lines of pixels (P, Pt P, P, P.

), (p, Ps P= Ps Pi ), (P, P, P
.

Pi Pt )...... pixel data is sequentially transferred to the shift register 35 for five stages! l35A-35E
is held while being shifted (Fig. 6(A)).

At the same time, the timing control circuit 40 controls the clock signal CK□F of the reference clock signal CK□ (FIG. 6(B)).
) at the timing of every 3 pulses (i.e. 3T*
tv period)) is supplied to the output control circuit 39.

As a result, the reference clock signal CK1□ is generated at the point in time to
, tr, tz, ts..., the generation time ts-s (to, ts, ti =
), 5 lines of pixel data (P, P, P, P.) are held in the shift circuits 35A to 35H.

P, ), (P+ Pg Pg Pg Ps ), (P
tP.

P4Ps Pa ), (P, P, P, Ps P,), (
Ps P, Ps P, P, ), (Pa Pi Pa
A multiplication circuit 36A based on P'rP, )...
~36E and the adder circuits 38A~38D, the output interpolated data Afl obtained by the product-sum operation is sent to the output control circuit 39.
is output as line number converted image data DATAout, and is thus stored in the CIF frame memory 25 as shown in FIG.
), the pixel data of each line of the NTSC frame is R,, R, R,, R,, R,, R, ---.
is written.

Incidentally, the NTSC pixel data R3, R1,
Rs, Ra...... are calculated as R1''CMI・P, 10C□・P, +CC,・P by performing a product-sum operation.

+C11・Pg +C□・P.

...... (5) Rt =Cat'PI +CI! Pt+Cct
'P30 CDz-P a 10 CE!・Ps...
・・ (6) Rs-Cas-Pz ±Cmx-Ps +Cc2・
Pa+ Ctr s・PS +CE3・P.

・・・・・・ (7) Ra-Ca4・Pg +Cia + Ps + C
C4・Pa+C94・Ps+Ct4・R6 ...... (8) Rs = Cm5'Ps +C Pa +C
cs ′P s+ Cll5 ′P 6 +c! S.H.
Pg... (9) Rh -Cab -Pa +Cmh ・Ps
+Ccb・P.

+C□・P? +Cth・P.

...... (10) As shown, coefficient data C1-C! It is obtained as interpolated pixel data by weighting by multiplying and then adding.

Here, the coefficient data CA I' = CE l, CaS ~
CtS, CA & ~Cts-... is (time L @
, L 6% L II! """) Shift times a35A~
Of the 5 lines of pixel data held in 35H, the pixel data with the smaller line number is weighted, and the coefficient data Cat~Cwt, C□
~CE4, ...... is time c t x , t q ,
...) The pixel data with the larger line number is weighted, and the NTSC pixel data R
, and Rz, Rz and R-1Rh and R, ---
constitute mutually different pixel data for common input image data DATAIN.

In the configuration shown in FIG. 3, the period in which the shift enable signals S31 and S32 given to the shift circuits 35A to 35E are in the shift enable state is selected to correspond to the period of the CIF clock signal, thereby making it possible to meet the CIF frame standard. The number of lines of image data can be taken into the shift register 35.

In addition to this, the period of the output clock signal CKouy is NT
The period of the SC clock signal CKNTSC is selected (by line number conversion image data DATA
NTSCiii raw data R that can be obtained as ut
,, NTS composed of Ra%R3...
The number of lines of the C frame will match the NTSC frame standard.

Thus, according to the configuration shown in FIG. 3, the number of lines in a CIF frame can be converted to the number of lines in an NTSC frame.

(G5) Effects of the Embodiment According to the above configuration, the shift of the shift register 35 is controlled at the timing of the input image data DATAIN, and the output interpolated data supplied at the timing of the reference clock CKurr. A, output control circuit 3
9 as converted image data DAT Aouy at the timing of the output clock signal CKO[I7, it is possible to thin out NTSC format image data and convert it to CIF format image data.
IF format image data can be converted to NTSC format image data by interpolation processing.

(G6) Other embodiments (1) In the above embodiment, the image data signal DA
A five-stage shift circuit 35 in which T A I N is cascade-connected.
Although the case where data thinning processing and interpolation processing are executed via A to 35E has been described, the present invention is not limited to this.
The number of stages of the shift register can be set variously.

(2) In the above embodiment, the coefficient circuits 37A to 37
Although the case has been described in which the weight of the coefficient data Cm""C sent from E is changed at the timing of the reference clock signal CK, the present invention is not limited to this, and the weight may be changed every few clocks. good.

(3) In the above embodiment, the reference clock signal CK
*The clock period T'ity of tr is 1/3 times the NTSC clock period T, , and the CIF clock period T.

Although the case has been described in which the clock cycle is set to 115 times the NTSC clock cycle T, the present invention is not limited to this, and the clock cycle may be set to 1/n times the NTSC clock cycle T and 1/- times the CIF clock cycle T.

(4) In the above embodiment, the line number conversion circuit 23
．． 23X in time division, image data signal DATA
, N has been described, but the present invention is not limited to this, and can be used as a decimation processing circuit alone or as an interpolation processing circuit alone.

(5) In the above embodiment, the NTSC system image data signal D is changed to the CIF system converted image data signal V.
When converting to Doat and CIF format image data V
NTSC format converted image data signal VDou from D, .
Although the case of converting to y has been described, the present invention is not limited to this, and can be applied to cases where image data having a wide range of different numbers of scanning lines is transferred.

H Effects of the Invention As described above, according to the present invention, the shift register is shift-controlled based on the timing at which image data is input to the shift register, and the interpolated data supplied to the output control circuit at the timing of the reference clock is controlled. By sending the converted image data at the timing when the output clock signal is input, it is possible to execute the thinning process and the interpolation process of the image data using a common circuit, reducing the circuit size and making it more flexible. realizable.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of the luminance signal processing section;
Figure 3 is a block diagram showing the configuration of the color signal processing section, Figure 3 is a block diagram showing the configuration of the line number conversion filter, Figure 4 is a time chart explaining the operation of the line number conversion filter, and Figure 5 is the line number conversion filter. A route map for explaining the number thinning process, Figure 6 is a time chart for explaining the line number interpolation process, Figure 7 is a route map for explaining the line number interpolation process, and Figure 8 is a high efficiency encoding process. 9 is a block diagram showing a conventional image data encoding device,
FIG. 10 is a characteristic curve diagram for explaining the quantization step. 23.23X...Line number conversion filter, 35
...Shift register, 35A to 35E...
...Shift circuit, 36A-36E...Multiplication circuit, 37A-37E-...Coefficient circuit, 38A-38
D... Addition circuit, 39... Output control circuit, 40... Timing control circuit, 41...
...Sequence circuit, S31. S32...Shift enable signal, S33...Coefficient control signal, CK I N...Reference clock signal, CKo
oy...Output clock signal. Agent Megumi Tanabe Line 51 Processing Figure 5 Line Okemadokori Figure 7

Claims (1)

[Scope of Claim] In a scanning line number conversion device that converts sequentially inputted image data into converted image data having a different number of scanning lines from the image data and sends the converted image data, the image is inputted at a timing that is an integral multiple of a reference clock. a shift register that shifts data based on a shift control signal supplied at the timing; and a shift register that shifts data based on a shift control signal supplied at the timing, and interpolated data obtained by weighting the image data read from the shift register every time the reference clock is input. an output control circuit that sends out converted image data based on an output clock signal that is input at an integer multiple of timing; and an output control circuit that supplies the shift control signal to the shift register and sends the output clock signal to the output control circuit. 1. A scanning line number conversion device, comprising a timing control circuit, and performing thinning processing or interpolation processing on the sequentially inputted image data to send out converted image data having a different number of scanning lines.