JPH03283669A - field effect transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and in particular to the structure of a field effect transistor incorporated in an integrated circuit or as a standalone device.

[Conventional technology]

Conventional field effect transistor (hereinafter abbreviated as FET)
has a structure shown, for example, in the plan view of FIG. 5(a) and the AA cross-sectional view of FIG. 5(b). In this example, a gate electrode 17 is formed on the surface of a P-type silicon substrate 11 with a gate oxide film 13 interposed therebetween. Source and drain layers 20 and 21 are formed.

[Problem to be solved by the invention]

In order to miniaturize element dimensions and increase stacking.

For FETs, conventional planar structures benefit from reducing their channel width. However, since the driving ability of an FET depends mainly on the channel width, it is difficult to achieve a high TOE product without reducing the driving ability.

An object of the present invention is to eliminate the above-mentioned drawbacks and provide an FET with a novel structure that is not a planar structure.

[Means to solve the problem]

The first undeveloped field effect transistor (FET) uses only the side wall of a recess formed in a predetermined region of a semiconductor substrate as a channel, and the source/drain diffusion layer extends at least from the substrate surface in the depth direction of the recess. It has a structure in which it is formed in a range in contact with the bottom surface of the recess.

[Effect]

In the FET of the present invention, the channel is formed in the side wall of the recess, so the channel width is determined by the depth of the recess.

Therefore, the width of the channel seen in the projection plane can be narrowed, and the actual channel width can be increased. This makes it possible to achieve both miniaturization and maintenance of driving capability.

〔Example〕

An embodiment of the present invention will be described below with reference to a drawing. FIGS. 1(a) to 1(C) show a first embodiment of the present invention, and FIG. 1(a) is a plan view.

FIG. 1(b) is a longitudinal sectional view taken along the line A-A in FIG. 1(a).
Figure (C) is a BB vertical cross-sectional view.

The silicon substrate 11 is made by growing a P− silicon layer 11B on a P+ silicon substrate 11A.
A recess reaching 1A is formed, and a gate electrode 17 is formed on the side wall of this recess with a gate oxide film 13 interposed therebetween. 20.degree. 21 is an N0 type source/drain layer. Used for either source or drain. 18 is II-
'? An oxide film within the tfB is formed during the manufacturing process, and finally the recess is filled with an insulating film 22 and the surface is covered. This structure is a three-dimensional structure in which the channel width is determined by the depth of the sidewalls, and the channel width can be increased even if the two-dimensional dimensions remain the same. Therefore, it is possible to achieve both miniaturization of dimensions and securing of driving capability.

Next, the manufacturing process of the first embodiment is shown in FIGS.
j) will be explained in order. (a)-(d) are AA sectional views. First, as shown in FIG. 2(a), a field oxide film 1 for element isolation is formed on the P-silicon layer iin.
2 is grown to 8000 to 100 OOA by selective oxidation method. On the area where the element is to be formed, there is a relatively thin layer of oxidation #&! of 20OA to 100OA. 26 and further, e.g.
An oxide film 14 is deposited to a thickness of 500 to 5000 Å using the VD method. Then, a resist pattern 15 is formed by a normal photolithography process.As shown in FIG. 2(b), an oxide film 26 is formed using this resist pattern 15 as a mask.
After etching the P- silicon layer 11B using the unetched oxide film as a mask,
Etching is performed by one reactive ion etching process until the substrate 11A is reached, thereby forming a recess 16. Then, the surface of the substrate including the sidewalls of the recesses 16 is thermally oxidized to form gate oxide l113 on the sidewalls of the recesses fl16. Note that channel doped layers 24 and 25 may be formed in order to control the threshold voltage of the transistor. 2. As shown in FIG.
7' of 2000 to 8000A is formed by vapor phase growth,
Further, an oxide film 18 is deposited to fill the recess 16.

Subsequently, as shown in FIG. 2(d), the oxide film 18 is etched back so that the oxide 1 pattern 18 remains only in the recess 16.
Conditions are also set so that the surface of the substrate in the recessed region is approximately flat. Then, Fig. 2(e) and Fig. 2(f)
As shown in FIG. 2, a resist pattern 19 for the gate step is formed by ordinary photolithography. 21st
54(e) t, the plan view, ffg21N (f) is B
2(j) are sectional views taken along the line B-B. This resist pattern 19
The polycrystalline silicon film 17' is selectively etched using the mask as shown in FIG. 2(g). This etching has 1
For example, a combination of anisotropic reactive ion etching and isotropic etching is performed, and then, as shown in Figure 2 (h), the oxide film 13 on the side surface of the recess from which the polycrystalline silicon has been removed is treated with diluted hydrofluoric acid solution. As shown in FIG. 2(i), source/drain diffusion layers 20 and 21 are formed. In this case, source/drain diffusion layers may be formed by ion implantation or by diffusion from impurity-doped spin-on glass.
As shown in FIG. 2, a buffer oxide film 14' is formed on the side surface of the recess. Furthermore, as shown in FIG. 2(j), an insulating film 22 is formed in the recess and on the surface of the substrate, and a wiring layer is then formed by normal steps (not shown).

Next, a second embodiment of the present invention will be described. In this example, the inside of the recess is filled with a phosphorus-doped polycrystalline silicon film between the gate electrodes, and FIG. 3 is a cross-sectional view of it, and A-
As shown in Figure 0, which shows cross-section A, a recess is formed on the silicon substrate 11, and gate oxide [13] is formed on the sidewall of this recess. Etching back of the oxide film 18 filling the recesses described in the first embodiment is unnecessary.

The process is simplified. Note that a P-type impurity layer 23 for stopping the channel is formed at the bottom of the recess.

Next, as a third example, SOI is used as a semiconductor substrate.
An example using a (silicon-on-insulator) substrate is shown in FIG. 4, and the cross-sectional direction is the AA direction in FIG. 1(a). An oxide film 27 is included in the semiconductor substrate, and a recess is formed up to this oxide film 27.

〔Effect of the invention〕

As explained above, one aspect of the present invention is to have a channel only on the side wall of a recess formed on a semiconductor substrate, and to extend a source and drain diffusion layer from the substrate surface to the bottom of the recess in the depth direction of the recess. By forming the field effect transistor in a region extending up to Since the value voltage is a single value, good current-voltage characteristics can be obtained.

[Brief explanation of drawings]

FIG. 1(a) is a plan view showing the first embodiment of the present invention, FIG. 1(b) is a cross-sectional view taken along line A-A in FIG. 1(a), and FIG.
C) is a cross-sectional view taken along line B-B in FIG. 1(a), and FIG. 2(a) to
(j) is a sectional view showing the manufacturing process of the first embodiment, FIG. 3 is a sectional view of the second embodiment of the present invention, and FIG. 4 is a sectional view of the third embodiment of the present invention.
FIG. 5(a) is a sectional view of the embodiment, FIG. 5(a) is a plan view of the conventional example, and FIG. 5(b) is a sectional view taken along line AA in FIG. 5(a). 11... Silicon substrate, 11A... P+ silicon substrate, 11B... P- silicon layer, 12... Field oxide film. 13...Gate oxide film. 17... Gate electrode, 17'... Polycrystalline silicon film, 18... Oxide film. 20.21... Source/drain diffusion layer. 22...Insulating film.

Claims (1)

[Claims] A structure in which only the side wall of a recess formed in a predetermined region of a semiconductor substrate is used as a channel, and a source/drain diffusion layer is formed in a range from the substrate surface to at least contact with the bottom surface of the recess in the depth direction of the recess. A field effect transistor characterized by: