JPH03283654A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the lowering of Vth in charge transfer MOSFET and to obtain a boosting potential efficiently by impressing a source potential on a P-type well and by making it work as a substrate bias lowering the threshold value of the MOSFET. CONSTITUTION:Erasure of data is executed by giving a boosting potential Vpp from a boosting circuit 4 to a P-type well PW1 of a memory array 1 part and a substrate. When data are written, on the other hand, a source potential Vcc is impressed on P-type wells PW2 and PW4 having charge transfer MOSFET formed therein, in boosting circuits 4 and 5, by a clock phi and inversion phi. This potential Vcc works as a substrate bias lowering the threshold value of the charge transfer MOSFET. Accordingly, the lowering of Vth in the charge transfer MOSFET is smaller than usual and the boosting potential Vpp or the like can be formed efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit device such as an EEFROM, and particularly relates to an improvement of a booster circuit unit integrally formed therein.

(Prior Art) An EEFROM using a memory cell having a MOS transistor structure having a charge storage layer and a control gate is known.

In the memory cell of this EEFROM, data is rewritten by transferring charges between the charge storage layer (floating gate) and the substrate using, for example, a tunnel current. When writing and erasing this data, the power supply voltage Vcc (
For example, a boosted potential of about 20V, which is higher than 5V), is required. That is, when electrons are injected into the floating gate of a selected memory cell, the control gate of the selected memory cell is set to Ov, and a high voltage of about 20 V is applied to the drain via the bit line. When electrons from the floating gate are released to the substrate, a high voltage with the opposite polarity is applied between the substrate and the control gate. Such high voltages are normally generated within the memory chip by installing a booster circuit inside the chip.

FIG. 4 shows an example of the configuration of a booster circuit section in such an EEFROM. This booster circuit includes a plurality of booster capacitors CI, C2, ...+C driven by a two-phase clock.
N and a charge transfer MOS transistor for sequentially transferring the charges accumulated in these capacitors.
+ m 22+ "' * " N2, and M for supplying the power supply voltage vee to the storage node of each capacitor.
OS transistor" 11+ m 21+..., mN
, consists of. All MOS transistors used here are n-channel, so this booster circuit is usually formed in a p-type well.

The p-type well is connected to VSS (ground potential).

FIG. 5 shows the waveform of the two-phase clock used to drive this booster circuit. This two-phase clock is generated using a ring oscillator.

In such a conventional booster circuit, a sufficiently high boosted potential Vl
) 9, there is a problem in that it becomes difficult to boost the voltage due to the substrate bias (back bias) effect. This will be explained below using a formula.

The boosted potential V91) obtained by the booster circuit in FIG. 4 is:
It is approximated by the following formula.

Vpp-VCC+NV φ-Σ V [old -v th.

-0 -2τ N1out/C Where, N is the number of boosting capacitors, v tht is the charge transfer MOS transistor m, 2. m22.・
・Threshold voltage of mN2, v tho is M for power supply
The threshold voltage of the OS transistor ml, τ is the width of the clock, Vφ is the potential difference between the "H#" level and "L" level of the clock, summer.UT is the output stage MOS transistor mN
The current flowing through 2, C is the 8 breath of the boost capacitor.

The storage node potential of the boosting capacitor becomes higher as it goes to the later stages, and the increase in the storage node potential acts equivalently as a substrate bias for the charge transfer MOS transistor in that portion. Due to this substrate bias effect, MOS
Since the threshold voltage of the transistor becomes high, as is clear from the above equation, the threshold f111! of the transfer MOS transistor is increased. The potential drop corresponding to the i pressure V tht increases accordingly. Therefore, when attempting to obtain a sufficiently high boosted potential vpp, the boosting efficiency deteriorates.

The above problems are not unique to EEFROMs, but also exist in other integrated circuits that require similar booster circuits.

(Problem to be Solved by the Invention) As described above, in the conventional booster circuit, when trying to obtain a high boosted potential, there is a problem in that the influence of the drop in vth due to the substrate bias effect in the charge transfer MOS transistor increases. Ta.

An object of the present invention is to provide a semiconductor integrated circuit device having a booster circuit that solves such problems.

[Structure of the invention]

(Means for Solving the Problems) The present invention is a semiconductor integrated circuit device having a booster circuit, wherein the booster circuit includes a gate and a gate in a second conductivity type well of a first conductivity type semiconductor substrate.
A plurality of charge transfer MO8 transistors of the first conductive channel connected in series with a common drain, and a plurality of booster transistors each having one end connected to the connection node of these MOS transistors and the other end driven by a two-phase clock. means for applying a well potential to the capacitor and the second conductivity type well to serve as a substrate bias that equivalently lowers the threshold value of the charge transfer MOS transistor;
It is characterized by having the following.

(Function) In the booster circuit according to the present invention, the second conductivity type well in which the charge transfer MOS transistor is formed has a substrate bias having a polarity that alleviates the increase in the threshold voltage of the charge transfer MOS transistor. A well potential is given. For example, when the second conductivity type well is p-type, the same power supply potential Vce as that of the n-type substrate is applied as the well potential. As a result, Vt in the charge transfer MOS transistor
The influence of the drop in h is reduced, and the drop in the boosted potential is suppressed. That is, a high boosted potential can be effectively obtained. Further, in the booster circuit configuration of the present invention, when the charge storage node of the capacitor becomes lower than Vcc due to clock driving, charge is directly charged from the p-type well to this storage node. Therefore, there is no need for a MOS transistor that supplies power supply voltage VCC to the storage node as in the prior art. This is useful for high integration.

(Example) The present invention will be explained in detail below.

FIG. 1 shows the main part configuration of a NAND cell type EEPROM of one embodiment. The memory cell array 1 is formed within a p-type well PWr formed on an n-type silicon substrate. In the memory cell array 1, a plurality of memory cells Mll, M12゜, etc. having a MOS transistor structure in which a floating gate and a control gate are stacked are connected in series to form a NAND cell.
The drain and source sides of the cell each have a selection gate S.
11. It is connected to the bit line BLI and the source line via S12.

The control gates of the memory cells arranged in the row direction are the control gate lines CGI, CG2 . ... are commonly connected. A column decoder 2 for selecting bit lines and a row decoder 3 for selecting word lines are provided around the memory cell array 1. 20V for rewriting data in memory cells
A first boosted potential Vpp of approximately IOV and a second boosted potential VN of approximately IOV lower than this are required. Boosting circuits 4 and 5 generate these boosted potentials V9p and VM, respectively.

The booster circuit 4 that obtains Vpp includes an n-channel, E-type MOS transistor m11+ for transferring one current to the first p-type well PW2 and the second p-type well PW1, respectively.
21+...1m1 and boost capacitor CI
It C21+ . . . +CNl is formed. Boost capacitor CIl+ C21+...
+CNl is configured, for example, by commonly connecting the sources and drains of D-type n-channel MOS transistors, using these connection nodes as input terminals for clocks φ and φ, and using the gate as a charge storage node. MOS for charge transfer
Transistor mll, m21. -.-, mNl are inserted between the storage nodes of adjacent capacitors with their gates and drains commonly connected. First p-type well PW
A power supply potential Vec is applied to the well potential 2 as a well potential, and a ground potential vSS is applied to the second p-type well PW.

Similarly, the booster circuit 5 that obtains VM also uses the first p-type well PW.
4 and the second p-type well PW4, respectively, M for charge transfer.
O8 transistor m 12. m22. ...mN2
and boost capacitor CI21 C221...C
It is configured to form N□. The power supply potential Vcc is applied to the first p-type well PW4, and the ground potential VSS is applied to the second p-type well PW. The clocks φ' and φ' of the booster circuit 5 are generated by a ring oscillator different from that of the booster circuit 4.

The output of the booster circuit 4 is amplitude-limited by a limiter circuit 6 and supplied to the row decoder 3, and is also sent to the p-type well PW in the memory cell array area via the well potential switching circuit 8.
It is further supplied to the n-type substrate via the substrate potential switching circuit 9.

The output of the booster circuit 5 is also amplitude-limited by the limiter circuit 7 and is supplied to the row decoder 3.

NAND cell type configured like this The data rewriting operation in EEFROM will be briefly explained.

Data erasure is performed using the p-type well PW in the first part of the memory cell array.
, and the substrate, all control gate lines CG and selection gate lines SG are set to Ov, and bit lines BL are separated from column decoder 2. As a result, electrons in the floating gates of all memory cells of the NAND cells are released to the p-type wells PW. At this time, clocks φ and φ from the ring oscillator enter the booster circuit 4, and the first boosted potential vpp is generated from the booster circuit 4.

This first boosted potential vpp is the well potential switching circuit 8
and is supplied to the p-type well PW1 and the substrate via the substrate potential switching circuit 9, respectively.

Data writing is, for example, writing to memory cells along the control gate line CG of the memory cell array 1.
A first boosted potential v is applied to the selected control gate line CG.
pp, control gate line CG on the bit line BL side from this,
A second boosted potential V is applied to CG2 and the selection gate line SG.
M is given, and the other control gate lines are Ov. And Ov on the bit line where data “1” is written, data “0”
A second boosted potential VM is applied to the bit line where .

The p-type well PW1 is set to Ov, and the substrate is set to Vcc. As a result, in the memory cell to which "1" is written, the bit line B
Ov transmitted from L to drain and 20V of control gate
A tunnel current flows and electrons are injected from the drain to the floating gate, and the tunnel current does not flow in a memory cell that performs 0° writing. During this writing, two types of clocks φ, φ and φ', φ' are generated. These drive the two booster circuits 4 and 5, and generate a first boosted potential vpp and a second boosted potential VM, respectively.The first boosted potential vpp is selected via the row decoder 3. the second boosted potential V
M is supplied via the row decoder 3 and the column decoder 2 to the bit line for writing "0" and the control gate line closer to the bit line than the selection control gate line.

In the above data rewriting operation, the booster circuits 4 and 5 that obtain the boosted potentials vpp and VM use the M for charge transfer.
A power supply potential Vce is applied to p-type wells PW2 and PW4 in which OS transistors are formed, and this power supply potential Vee acts as a substrate bias that lowers the threshold voltage of the charge transfer MOS transistor. Therefore, the Vih drop in the charge transfer MOS transistor is smaller than in the conventional case, and the boosted potential Vpl) and VM can be obtained efficiently.

FIG. 2 shows an embodiment in which the two booster circuits 4.5 in the embodiment of FIG. 1 are modified. In this embodiment, the p-type well PW2 on the charge transfer MOS transistor side of the booster circuit 4 in FIG. 1 and the p-type well PW4 on the charge transfer MOS transistor side of the booster circuit 5 in FIG. Well PW
Similarly, a p-type well PW for the capacitor of the booster circuit 4 and a p-type well P for the capacitor of the booster circuit 5 are summarized in 7.
W, are combined into one p-type well PWl. According to this embodiment, two booster circuits can be formed in a small area.

FIG. 3 shows an embodiment in which the present invention is applied to a booster circuit that obtains a negative boosted potential -vpp. In this case, step-up capacitors C, C2, .

Inside, a p-channel MOS transistor mp for charge transfer.
l, mp2, . . . are formed. While normally a ground potential Vss is applied to the p-type substrate and a power supply potential Vcc is applied to the n-type well NW, in this embodiment VSS is also applied to the n-type well NW.

As a result, as in the previous embodiment, a substrate bias that equivalently lowers the threshold voltage is applied to the charge transfer MO8 transistors mp, mp2, . -VpI) can be obtained.

In the embodiment, an embodiment has been described in which the present invention is applied to a NAND cell type EEPROM, but the present invention is not limited to an EEPROM, but is useful when applied to any integrated circuit that requires a similar boosted potential.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit device having an internal booster circuit that can efficiently obtain a boosted potential by suppressing the effect of vth drop of a MOS transistor. can.

[Brief explanation of drawings]

FIG. 1 shows a NAND cell type EEPRO according to an embodiment of the present invention.
FIG. 2 is a diagram showing the configuration of a booster circuit of another embodiment. FIG. 3 is a diagram showing the configuration of a booster circuit of another embodiment. FIG. 4 is a conventional booster circuit. FIG. 5 is a diagram showing the clock waveform used in the booster circuit. 1...Memory cell array, 2...Column decoder, 3.
... Row decoder, 4, 5... Boost circuit, 6.7...
Limiter circuit, 8... Well potential switching circuit, 9...
・Substrate potential switching circuit, P W2 , P Wa ,
P W7...first p-type well, P W3, P
Ws, P Wb...Second p-type well, mth to m Nl, m12 to m N2°°. Charge transfer n-channel MOS transistor, C1□~C
N2. C1□~CN2... Boost capacitor, NW,
...n-type well, mp, ~mpN...p for charge transfer
Channel MOS transistors, C1 to CN... boosting capacitors.

Claims (3)

[Claims] (1) A semiconductor integrated circuit device in which a booster circuit is integrally formed, wherein the booster circuit includes a gate and a gate in a second conductivity type well of a first conductivity type semiconductor substrate.
A plurality of charge transfer MOS transistors of a first conductive channel connected in series with a common drain, and a plurality of booster transistors each having one end connected to a connection node of these MOS transistors and the other end driven by a two-phase clock. A semiconductor integrated circuit device comprising: a capacitor; and means for applying a well potential to the second conductivity type well to serve as a substrate bias that equivalently lowers the threshold voltage of the charge transfer MOS transistor. (2) The boost capacitor is connected to the charge transfer MOS
2. The semiconductor integrated circuit device according to claim 1, comprising a D-type, second conductive channel MOS transistor formed in a second conductive type well different from the transistor. (3) A memory cell array in which a plurality of memory cells having a MOS transistor structure in which a charge storage layer and a control gate are stacked in a second conductivity type well of a first conductivity type semiconductor substrate is formed, and readout of this memory cell array. , a semiconductor integrated circuit device having a control circuit that controls writing and erasing, and a booster circuit that is formed in a second conductivity type well separate from the memory cell array area and generates a high voltage for writing or erasing. , the booster circuit includes: a plurality of charge transfer MOS transistors of connected first conductive channels connected in series with a common gate and drain in a first second conductive type well; boosting capacitors arranged in a second second conductivity type well formed separately from the conductivity type well, one end of which is connected to the connection node of the MOS transistor, and the other end of which is driven by a two-phase clock; and means for applying a well potential serving as a substrate bias that equivalently lowers the threshold value of the charge transfer MOS transistor to the first well of the second conductivity type. Device.