JPH0418709B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to semiconductor memory device technology and to technology that is particularly effective when applied to nonvolatile semiconductor memory devices, such as EEPROM (electrically erasable programmable nonvolatile memory device). The present invention relates to technology that is effective for use in semiconductor memory devices.

[Background technology]

The present invention has developed the following technology regarding non-volatile semiconductor memory device technology, particularly technology related to EEPROM.

In other words, the power consumption is reduced by converting the EEPROM peripheral circuit into a C-MOS, and for this purpose, an n-type semiconductor substrate is used.
A peripheral circuit of a C-MOS logic circuit is formed on this substrate, a p-type well is formed on the n-type semiconductor substrate, and an MNOS (metal-nitride-oxide-semiconductor) element is formed on this p-type well. In other words, it is used as a memory cell.

However, in this technology, in order to apply a negative erase voltage to the gate of the MNOS element used as a memory cell, the semiconductor substrate is raised to a high positive potential and a relatively high negative voltage is applied to the gate. In the normal EEPROM method, when the semiconductor substrate is raised to a high positive potential, the operating threshold of the C-MOS logic circuit formed on the substrate is disturbed, causing normal operation. The inventor of the present invention has clarified that this causes a problem in that it becomes impossible to secure.

Furthermore, the high voltage generation circuit for writing or erasing memory cells needs to have a certain degree of current supply capability, which makes it difficult to form the high voltage generation circuit within a semiconductor substrate. The inventor has also found that problems arise.

[Purpose of the invention]

An object of the present invention is to enable a high voltage for writing or erasing to be applied to a memory cell of a non-volatile semiconductor memory device such as an EEPROM while keeping the substrate potential constant. The peripheral circuit is C-
In addition to making it possible to convert into MOS,
The current supply capacity of the high voltage generation circuit for writing or erasing the data may be small.
This provides a nonvolatile semiconductor memory device technology that allows the high voltage generation circuit to be easily formed within a semiconductor substrate.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the voltage from the high voltage generation circuit is applied between the cell of the memory cell and the well in which the memory cell is formed, and the high voltage is indirectly applied to the memory cell via the capacitor. By doing this, it is possible to apply a high voltage for writing or erasing to a memory cell of a non-volatile semiconductor memory device such as an EEROM, while keeping the substrate potential fixed constant.
This allows the peripheral circuitry to be implemented as a C-MOS, and the current supply capacity of the high voltage generation circuit for writing or erasing data can be small, thereby making it possible to generate the high voltage. The purpose of this invention is to facilitate the formation of circuits within a semiconductor substrate.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In addition, the same or corresponding parts are indicated by the same reference numerals in the drawings.

First, the nonvolatile semiconductor memory device according to the embodiment of the present invention is an EEPROM that uses a C-MOS logic circuit in its peripheral circuit, and as shown in FIGS. The MNOS (metal-nitride-oxide-semiconductor) element formed in the well 12 is defined as a memory cell Qm. This memory cell Q
M is a type of n-channel MOS field effect transistor having an n ⁺ type source/drain region 14, and the insulating film between the gate G and the channel region is formed by a nitride film 18 and an oxide film 16. It is configured.

Then, when erasing, as shown in Figure 1a,
Connect well 12 to ground potential (or power supply potential +
Vcc) and a negative high voltage -Vpp on the gate G.
Apply. As a result, the charges stored in the gate G are discharged and erased.

Further, during writing, as shown in FIG. 1B, the gate G is connected to the ground potential (or the power supply potential +Vcc), and a negative high voltage -Vpp is applied to the well 12. As a result, the gate G is charged and writing is performed.

In this case, the n-type semiconductor substrate 10 is always fixed at the power supply potential. This n is type semiconductor substrate 1
0 and the p-type well 12 above, the pn
The junction ensures an electrically isolated state even if a high negative voltage -Vpp is applied to the p-type well 12 for writing. This n-type semiconductor substrate 10 includes the memory cell Qm and a C
- A peripheral circuit (not shown) is formed using a MOS logic circuit. This weekside circuit is operated by the power supply +Vcc applied to the board 10.

Next, as shown in FIG. 2, the memory cell Qm has its gate G connected to a gate line 30 that supplies voltage for writing or erasing, and its source and drain connected to a switch MOS field effect transistor. It is connected to write block line 34 and data line 36 via transistor Q3. The gate of the switch MOS field effect transistor Q3 is connected to the word line 32. Thereby, by selectively driving each of the lines 30 to 36, a specific memory cell Qm can be selected for erasing/writing or reading out the stored contents.

Here, FIG. 2 particularly shows the parts that erase the memory cell Qm, that is, the high voltage generation circuit 26 and the erase circuit 20 that apply the erase voltage -Vpp to the gate G of the memory cell Qm. It is something. The high voltage generating circuit 26 generates a negative high voltage from a power supply (+5V), and is formed all over the semiconductor substrate 10. The erasing circuit 20 is provided for each decode output of the X decoder 22, and includes a driver 24 that operates in response to the echo output of the X decoder 22, and a pair of MOS field effects that are driven to conduct in a complementary manner during erasing. Transistors Q1, Q2, the memory cell Qm is
The high voltage generating circuit 26 has a capacitor C which is alternately connected to the gate G of the high voltage generating circuit 26 and the high voltage generating circuit 26. Then, the output voltage -Vpp from the high voltage generation circuit 26 is indirectly applied to the gate G via the capacitor C to perform erasing.

Note that the high voltage generating circuit 26 is also used during writing.

In FIG. 2, when the decoded output of the X-decoder 22 becomes "L" (low level), the pair of MOS field effect transistors Q1 and Q2 are turned ON (conducting) and OFF (non-conducting) by the clock φ. Repeat alternately. Transistor Q1 is ON and Q2 is
During the OFF period, the high voltage generation circuit 26 is disconnected from the capacitor C, while the gate G of the memory cell Qm is connected to the capacitor C. This allows the storage cell
A part of the charge stored in the gate G of Qm is transferred to the capacitor C. 1 indicates the direction of charge movement at that time. Also, transistor Q1 is OFF and Q2 is ON.
During the period when the capacitor C is disconnected from the gate G, the capacitor C is connected to the high voltage generation circuit 26. As a result, the charge transferred from the gate G of the memory cell Qm to the capacitor C is absorbed by the high voltage generation circuit 26. 2 indicates the direction of charge movement at that time. By repeating these two actions,
The charge stored in the gate G is discharged and erased.

In the manner described above, the memory cell Qm can be erased without constantly flowing current from the high voltage generating circuit 26. As a result, erasing can be performed even if the current capacity of the high voltage generating circuit 26 is small, and at the same time, the high voltage generating circuit 26 can be easily formed within the reaction substrate. Further, since erasing or writing can be performed while the potential of the semiconductor substrate is fixed to the power supply potential +Vcc or the ground potential, it becomes possible to form a C-MOS logic circuit as a peripheral circuit.

〔effect〕

(1) Electrically programmable nonvolatile semiconductor memory whose memory cells are MNOS (metal-nitride-oxide-semiconductor) elements formed in p(n)-type wells in n(p)-type semiconductor substrates. The peripheral circuit of the device is C-MOS (complementary MOS).
Consists of logic circuits and the above MNOS
A high voltage generation circuit that applies a voltage for writing or erasing to the gate of an element, a pair of MOS field effect transistors that are driven to conduct in a complementary manner during writing or erasing, and this pair of MOS field effect transistors. Therefore, it has a capacitor that is alternately connected to the gate of the MNOS element and the high voltage generation circuit, and further applies the output voltage from the high voltage generation circuit between the well and the gate. By connecting one side to the ground potential or power supply potential, it is possible to apply a high voltage for writing or erasing to the memory cell while keeping the substrate potential constant. The effect is that the peripheral circuit can be made into a C-MOS.

(2) In addition, the current supply capacity of the high voltage generation circuit for writing or erasing the data need not be small, which makes it easier to form the high voltage generation circuit within the semiconductor substrate. This effect can be obtained.

Although the invention made by the present inventor has been specifically explained above based on examples, this invention is not limited to the above-mentioned examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, a p-type semiconductor substrate may be used as the semiconductor substrate.

[Application field]

The above explanation mainly describes the invention made by the present inventor and the field of application that is its background.
Although we have explained the case where it is applied to EEPROM technology, it is not limited to this, for example,
It can also be applied to non-volatile RAM and EPROM technologies.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the configuration of a memory cell used in a nonvolatile semiconductor memory device according to the present invention, and FIG. 2 is a diagram showing an eraser circuit portion of the nonvolatile semiconductor memory device according to the present invention. 10...n type semiconductor substrate, 12...p type well, 14...n ⁺ type source/drain region, 16
...Oxide film, 18...Nitride film, G...Gate electrode, 20...Erasing circuit, 22...X decoder, 2
4...Driver, 30...Gate line, 32...Word line, 34...Write block line, 36...Data line, -Vpp...Negative high voltage, 26...High voltage generation circuit, +Vcc... ...Operating power supply, Qm...MNOS element (memory cell), Q1, Q2, Q3...MOS field effect transistor, φ...clock.

Claims (1)

[Claims] 1. An electrically programmable storage device whose memory cell is an MNOS (metal-nitride-oxide-semiconductor) element formed in a p(n)-type well in an n(p)-type semiconductor substrate. The device is a non-volatile semiconductor memory device in which the peripheral circuit is composed of a C-MOS (complementary MOS) logic circuit, and a high voltage generation circuit that applies a voltage for writing or erasing to the gate of the MNOS element; a pair of MOS field effect transistors that are driven to conduct in a complementary manner during programming or erasing, and a capacitor that is alternately connected to the gate of the MNOS element and the high voltage generation circuit by the pair of MOS field effect transistors. and is further configured to apply an output voltage from the high voltage generation circuit between the well and the gate, and connect one of them to a ground potential or a power supply potential. Non-volatile semiconductor memory device. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the semiconductor substrate is fixed at a power supply potential.