JPH03283534A - Micro-miniaturization of compound semiconductor - Google Patents

Abstract

PURPOSE:To form a side wall perpendicular to a thin compound semiconductor film by forming a striped mask on a compound semiconductor substrate so that an etching side wall is formed in the reversed mesa shape and exposing the mask in the environment obtained by applying the gas of group VII only in the predetermined pressure and then executing selective etching. CONSTITUTION:The patterning is executed to a SiO2 film 12 in the form of stripe in the reversed mesa direction of a substrate and thereafter a window is opened to the region where etching is desired. Next, ion sputtering is conducted for a minute with acceleration voltage of 400V and microwave power of 200W under the environment of argon gas pressure of 6X10<-4>Torr. In this case, when the substrate 11 is heated up to the predetermined temperature, natural oxide film at the surface of substrate 11 can be removed. Thereafter, the substrate 11 is heated up to 240 deg.C, chlorine gas pressure is set to 2X10<-4>Torr and gas etching is executed for 30 minutes. Thereby, the shape of etching side wall of the substrate 11 for laser thus obtained becomes almost perpendicular.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a) a method of etching a compound semiconductor substrate or a compound semiconductor thin film formed thereon;
In particular, the present invention relates to a method for microfabrication of compound semiconductors for forming vertical etched sidewalls.

(Prior Art) In recent years, various devices using compound semiconductors have been developed. In the production of such devices, for example, semiconductor laser end faces, gate side walls of field effect transistors,
It is necessary to vertically etch the compound semiconductor substrate or the compound semiconductor thin film thereon in grooves and the like for isolating two or more elements. At present, for this type of etching, dry etching techniques such as plasma-based etching, chemical ion etching (RIE), reactive beam etching (RIBE), etc. are used for microfabrication purposes.

However, this type of etching method has the following problems. That is, the depth that can be etched is determined by the etching selectivity with respect to the mask, so in order to form deep grooves, it is necessary to use a mask material with a high selectivity or to make the etching mask thick. Mask materials with a high selection ratio are generally difficult to peel off after etching, and at present there is no mask material that is effective for etching compound semiconductors. Furthermore, if the mask is made thicker than necessary, defects may occur in the compound semiconductor thin film due to stress caused by the difference in thermal expansion between the mask and the compound semiconductor.

In addition, if dry etching is used in the middle or at the end of a device process that has undergone a complex process, it will not only be possible to etch not only the area to be etched due to ion bombardment, but also other parts, such as electrodes and Schottky oxide films where interface control is difficult. This also caused damage to the device, leading to deterioration of the device characteristics. In order to prevent this, it has been considered to protect parts that should not be damaged with a passivation film, but this extremely reduces the degree of freedom in the device process and complicates it, resulting in a decrease in product yield.

(Problem to be Solved by the Invention) Conventionally, when etching a compound semiconductor substrate or a compound semiconductor thin film thereon, a dry etching technique using plasma is used to form a pattern with vertical sidewalls. However, there was a problem of damage caused by ion bombardment.

The present invention has been made in consideration of the above-mentioned circumstances, and its purpose is to enable etching to be performed at a relatively low temperature compared to the device fabrication process without damage during processing, and to enable etching to be carried out on a compound semiconductor substrate or on the substrate. It is an object of the present invention to provide a method for microfabrication of a compound semiconductor that can form vertical sidewalls in a compound semiconductor thin film.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the present invention selectively etches a compound semiconductor substrate or a compound semiconductor thin film formed on the substrate to form a material having vertical wall surfaces. In a compound semiconductor microfabrication method for forming a pattern, a striped or striped opening is formed on a compound semiconductor substrate or a compound semiconductor thin film thereon so that the etched sidewall becomes an inverted mesa shape when wet etching is performed. Then, the compound semiconductor substrate is heated to a predetermined temperature and exposed to an atmosphere in which Group 1 gas is applied at a desired pressure, thereby selectively etching the compound semiconductor substrate or the compound semiconductor thin film thereon. It is characterized by

The present invention also provides a compound semiconductor microfabrication method that includes:
After forming an etching mask on a compound semiconductor substrate that is deviated from the (100) plane by 0 to 3 degrees or on a compound semiconductor thin film formed on the substrate, this mask is etched within a range of ±5 degrees with respect to the [0113 direction. Patterning is performed in a stripe shape along the direction (reverse mesa direction), and then the natural oxide film attached to the desired etching area after patterning is removed, and then, following this natural oxide film removal process, the compound semiconductor substrate is It is characterized by etching the compound semiconductor substrate or the compound semiconductor thin film thereon with side etching from a mask by heating it to a desired temperature and exposing it to an atmosphere in which group 1 gas is applied at a desired pressure.

(Operation) Generally, when attempting to obtain an end face perpendicular to the forward mesa direction (the stripe direction in which a forward mesa is formed when etching is performed using a stripe mask), as typified by bromine-based wet etching, The cross-sectional shape taken parallel to the forward mesa direction has a unique shape as shown in FIG. However, when etching is performed in a gas phase as in the present invention, for example, when GaAs is etched with chlorine gas, etching progresses as Ga chloride and As chloride produced by reaction with chlorine gas evaporate. Here, if the substrate temperature is higher than the temperature at which the generated chloride evaporates, etching from the bottom and etching from the sides will occur simultaneously, and the corners as shown in FIG. 9 will disappear due to evaporation, resulting in the end faces becoming vertical. That is, when the substrate temperature is low, corners are formed, and when the substrate temperature is high, the corners are rounded and become vertical. It was also found that as the temperature rose further, the sides began to sag. Therefore, by optimizing the chlorine pressure and substrate temperature, vertical sidewalls will be obtained.

As described above, according to the present invention, a compound semiconductor substrate or a compound semiconductor thin film thereon can be selectively etched without ion bombardment, and vertical sidewalls can be formed. That is, vertical sidewalls can be formed without processing damage. Furthermore, the selectivity of the etching mask may be small, as long as the Group 1 gas and the etching mask do not react and disappear before etching to a desired depth. To this extent, the material of the etching mask can be selected from a wide range, and for example, it is also possible to use resist, gold, or other electrode materials as they are as the etching mask. Furthermore, if a step of removing the natural oxide film is performed before etching, good reproducibility and controllability of the etching depth can be maintained. If this step of removing the natural oxide film is omitted, there will be variations in the depth of subsequent etching, and there is a risk that the etched surface will not be flat.

Note that although the present invention is limited to sidewall formation perpendicular to the forward mesa direction, no problem will occur if the direction of the element is adjusted to match the present invention. In addition, the substrate heating is from 100℃ to 4℃, which is lower than the temperature of processes such as electrode alloying.
It is sufficient to carry out the process at 00° C., and there will be no thermal influence on the device.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a sectional view showing a step of forming a vertical end face of a semiconductor laser according to a first embodiment of the present invention.

First, as shown in Fig. 1(a), an electrode process is applied to a laser test plate 11 having a GaA IAs/ a As double heterostructure, and a SiO □ film (mask) is placed on it.
2 by atmospheric pressure chemical vapor phase method. Subsequently, as shown in FIG. 1(b), the 5in2 film 12 is patterned in stripes in the reverse mesa direction of the substrate to form a window in the area desired to be etched. Here, the reverse mesa direction is
This is the stripe direction in which an inverted mesa shape is formed when selectively etching is performed by wet etching using a stripe mask, and if the substrate surface is (100), [
011] direction, then 6 x 1 of argon gas
Ion sputtering is performed at an acceleration voltage of 400 V and a microwave of 200 W for 1 minute in an atmosphere of 0--5 to 1×10 −4 Torr. Figure 1(e) represents this state,
In the figure, 13 indicates an argon ion. At this time, if the substrate 11 is heated to a predetermined temperature, the natural oxide film on the surface of the substrate 11 can be removed. After this, board 1
1 to 240℃ and chlorine gas pressure to 2X 10--
Set to 5 to 1 x 10-4 Torr and perform gas etching (vapor phase etching) for 30 minutes. FIG. 1(d) shows this state, and 14 in the figure indicates chlorine gas. Note that if the substrate 11 is heated during ion sputtering,
It is not necessarily necessary to heat the substrate 11 during this gas etching process.

The shape of the etched sidewall of the laser substrate 11 thus obtained is approximately vertical as shown in FIG. 1(d). This is because in the temperature range used in the etching process, the rate of evaporation of aluminum and gallium chloride is not the limiting factor, but chlorine gas and G
aAs.

This is because the reaction rate with GaAlAs or AlAs is rate-limiting. Further, the etching depth depends on the groove width, and is the same as long as the groove width is 10 μm or more, and in this case, the etching depth was 2.5 μm. Side etching is seen inside the etching mask 5i (h film 12, and the side etching amount is 1.5 on each side.
.mu.m Next, a method for forming a vertical end face of a semiconductor laser according to a second embodiment of the present invention will be described. As an etching substrate, n
A first-order diffraction grating (period: 2500) was formed in the reverse mesa direction on a 1nP substrate by electron beam exposure and dry etching, and an InGaAsP optical guide layer (composition: 1.3 μm in wavelength) was formed on it. .2μm5InGaAs
The P active layer (composition is 1.55 μm in terms of wavelength) is 0.1 μm.
m, p-type 1nP cladding layer of 1 μm, p-type InGaAs
A P contact layer grown to a thickness of 0.5 μm was used.

As in the first example, 1,000 5IO2 films were formed on an InP substrate by atmospheric pressure chemical vapor deposition, and the 5in2 films were patterned as shown in Figure 1(b) to form windows in the desired etching areas. Open. Then 6 x 1 of argon gas
Ion sputtering is performed at an acceleration voltage of 400 V and a microwave of 200 W for 1 minute in an atmosphere of 0 -5 to 1 x 10 -4 Torr. After this, the substrate was heated to 370°C and the chlorine gas pressure was increased to 4 x 10"-5 to 1 x 10-4 Torr.
Set the temperature to r and perform gas etching for 30 minutes. In this temperature range, the rate is not determined by the evaporation of indium or gallium chloride, but by the reaction between the chlorine gas and 1nP or 1nGaAsP.

Also in this case, a vertical laser end face was obtained. Under these conditions, the etching depth was 4.2 μm.

In addition, in order to integrate a photodetector on the monitor side of the laser, a laser/photodetector was fabricated by forming a groove in a direction inclined by 5 degrees from the direction perpendicular to the stripes in the active layer. The reason why it is tilted by 5 degrees is that the light emitted from the laser is reflected by the surface of the light receiving element and does not affect the characteristics of the laser. The groove separating the laser and receiver can be created at the same time as forming the end face of the laser.

Further, under the conditions of the above experiment, a vertical side wall was obtained with the angle of inclination in the range of 0 to ±5 degrees. Furthermore, the substrate surface is (1
00) is the most desirable, but vertical sidewalls were obtained even with 0-3 degrees off.

Both the first and second embodiments were able to produce lasers that were completely comparable to those of the arm-opening laser in terms of optical output-current characteristics, voltage-current characteristics, @fractional efficiency, and other characteristics.

Next, a third embodiment method in which the present invention is used to control the active layer width of a laser will be described with reference to FIGS. 2 and 3. As an etching substrate, a first-order diffraction grating (period: 2,500) is formed in the forward mesa direction on an n-type 1nP buffer layer 22 on an n-type 1nP substrate 21, and an n-type InGaAsP optical guide layer 23 is formed on it. (The composition is 1.
3 μm) is 0.2 μm, and the InGaAsP active layer 24 (composition is 1.55 μm in terms of wavelength) is 0.1 μm sp type 1n.
The P cladding layer 25 was grown to a thickness of 111 m, and the p-type 1nGaAsP contact layer 26 was grown to a thickness of 0.5 μrn. As a method for forming a diffraction grating in the forward mesa direction, it is possible to use a combination of two-beam interference exposure method and wet etching, instead of using electron beam exposure method. Furthermore, since the side walls of the diffraction grating do not need to be vertical, the microfabrication technique of the present invention may be applied directly to the forward mesa direction. Since the oscillation wavelength of the laser sensitively affects the width of the active layer, it is necessary to form this width with good controllability.

Therefore, according to the present invention, after the contact layer 26 is grown as shown in FIG. 2(a), the active layer 26 is grown as shown in FIG. 2(b).
Vertical mesa etching was performed on the active layer 24 deeper than position 4, and then a semi-insulating InP layer 28 was buried as shown in FIG. 4(C).

Instead of this semi-insulating InP layer 28, p-1nP and n-1nP may be buried so that the pn junction is reverse biased. Also, the structure is not limited to this, as shown in Figure 3 (a
) to (d), the light guide layer 23 has a diffraction grating formed thereon.
A 0.5 μm terrace with the width of the active layer is formed on the wafer on which a p-1nP layer 25' is grown to a thickness of 0.1 μm, and a semi-insulating I
An nP layer 29 is selectively grown on the etched portion, and then a cladding layer 25. The contact layer 26 may be grown in this order.

The fabrication method for the first structure is shown in FIG.

That is, 5i is formed on the p-1nGaAsP contact layer 26.
200 N2 films 27 were formed by atmospheric pressure chemical vapor phase method.
Next, the 5in2 film 27 is patterned to open a window in the area desired to be etched. The SiO2 width of the mesa part is 4μ
It was set as m. Since etching is not performed using plasma, the selection ratio between the substrate 21 and the mask 27 does not need to be large, and the thickness of the mask can be reduced in order to improve pattern accuracy.

After that, 6 X 10--5~1 of argon gas
In an atmosphere of ×10-4 Torr, acceleration voltage 400V,
Ion sputtering is performed using microwaves of 200 W for 1 minute. After this, the substrate was heated to 370°C, and the chlorine gas pressure was set to 4 x 10-5 to 1 x 10-4 Torr.
Gas etching for 5 minutes.

In this temperature range, the rate is not determined by the evaporation of indium or gallium chloride, but by the reaction between the chlorine gas and InP or InGaAsP.

Therefore, as in the previous example, a vertical laser end face was obtained. Under these conditions, the etching depth was 2 μm. Further, side etching from both sides of the SiO2 mask was 1 μm each, resulting in an active layer width of 2 μm. A surface with no processing damage appeared on the mesa sidewall, and no new impurity levels were generated at the interface when it was filled with semi-insulating 1nP. This can also be seen from the fact that the leakage current is small based on the current-voltage constant of 11!1. Furthermore, the variation in the oscillation threshold supercurrent of the laser fabricated in this way is within 10%, the variation in the oscillation wavelength is ±10 for 1.55 μm, and the width of the active layer is ±0 for 2 μm. .1 μm.

For the structure shown in Figure 3, the etching material is Ga on average.
The etching conditions were changed because it contains a lot of . 0.1 μm p-1nP layer 25° grown on the optical guide layer 23
A 5-in2 film 27 is placed on top of the 200
After forming a figure, patterning 5i02fi27 is performed to open a window in the area desired for etching. Mesa part SI
02 width was 2.5 μm. Thereafter, ion sputtering is performed for 1 minute in the same manner as before. Next, the board 21 is 24
Heat to 0℃ and increase the chlorine gas pressure to 4×10 −5 to 1×1
Set the temperature to 0-4 Torr and perform gas etching for 5 minutes.

In this temperature range, the rate is not determined by the evaporation of indium or gallium chloride, but by the reaction between the chlorine gas and InP or InGaAsP, and a vertical laser end face was obtained. Further, under these conditions, the etching depth was 0.6 μm, the side etching from both sides of the 5lO2 mask was 0.2 μm, and the active layer width was 2.1 μm.

Next, the etched side part is filled with a semi-insulating InP layer 29, and after removing the mask, a p-InP cladding layer 25 is filled.
, p-1nGaAsP:1 intact layer 26, respectively.
．． It grew to 9 μm and 0.5 μm. At the buried interface, a surface with no processing damage appeared, and no new impurity levels were generated at the interface when buried with semi-insulating 1nP.

This can also be confirmed by the fact that the leakage current is small by current-voltage measurement. It can be seen that the variations in threshold current and oscillation wavelength are small, and the width of the active layer is controlled.

When embedding is performed using a 5in2 mask that is in an overhang state due to side etching in the above two embodiments, swelling at the mask edge can be prevented and a flat surface can be obtained, leading to an improvement in laser yield.

Here - GaAs with chlorine gas as an example.

Etching of 1nP and 1nGaAsP substrates will be described in detail. First, basic data when etching a GaAs substrate will be shown. Figure 4 shows that after performing the same ion sputtering as in the above example, the chlorine pressure was 2 x 10.
This is the temperature dependence of the etching rate of a GaAs substrate under conditions of -5 to 1 x 10-4 Torr. Further, the numbers in parentheses in the figure indicate the angle θ between the etching side wall and the mask, as shown in FIG.

When the etching temperature is low, the vapor pressure of gallium chloride and arsenic chloride is low, making it difficult for side etching to occur.
It tends to become a reverse taper type.

As the temperature rises, the vapor pressure of gallium chloride and arsenic chloride increases, so the amount of side etching increases. As a result, substantially vertical side surfaces were obtained at around 250°C. Furthermore, when the substrate temperature reaches 250° C. or higher, the sidewall shape becomes dependent on the chlorine pressure.

Figure 6 shows that when the substrate temperature is set at 280°C, after performing the same ion sputtering as in the above example, the chlorine gas pressure is changed from I x 1O-5Torr to I x 1O-3Torr.
The graph shows the change in etching rate and the angle formed between the side wall and the top surface of the substrate when the etching speed is changed to rr. When the chlorine pressure is less than I x 10 -5 to 1 x 10 -4 Torr, the side wall surface becomes gentle. In this temperature range, the vapor pressures of gallium chloride and arsenic chloride are sufficiently high, so that etching proceeds due to the chemical reaction between chlorine and gallium arsenide. The higher the chlorine pressure, the more side etching occurred on the sidewall. When the substrate temperature was lower than 200° C., the sidewall shape hardly changed due to the chlorine pressure. Increasing the chlorine pressure increases the etching rate and allows the formation of deep grooves, but side etching of the side walls also progresses, so there is a trade-off between controllability of groove width and groove depth.

What can be said here is that increasing the substrate temperature enables vertical etching to a high pressure, and decreasing the substrate temperature enables vertical etching to a low pressure. According to experiments conducted by the present inventors, vertical etching was possible at a substrate temperature of 200°C up to a chlorine pressure of I x 1O-5 Torr, and at a substrate temperature of 300°C up to a pressure of I x 1O-jTorr. FIG. 8 shows the experimental results of etching GaAs while varying the substrate temperature and chlorine gas pressure. Mark O in the figure indicates that the etched side wall is approximately vertical (θ-85~
95 degrees), and the X marks are other points.

Next, basic data when etching an InP substrate will be described. FIG. 4 shows the etching temperature dependence when a 1nP substrate was etched under the same conditions as before. Under these conditions, no vertical sidewalls could be obtained even if the temperature was changed. However, if the chlorine gas pressure is 4 x 10--5 to 1 x 10-4
There was a substrate temperature at which vertical sidewalls could be obtained when lowered to about Torr. When the etching temperature is low, the vapor pressure of indium chloride and phosphorus chloride is low, and side etching is difficult to occur, making it easy to form a reverse taper type. As the temperature rises, the vapor pressure of indium chloride and phosphorus chloride increases, so the amount of side etching increases. As a result,
Vertical sidewalls were obtained at a substrate temperature of 350"C. However, in this case, the chlorine pressure was changed from 4 x 10-5 to 1 x 10-4 Torr.
Vertical side walls could not be obtained unless the thickness was lowered to a certain degree.

FIG. 7 shows that when the substrate temperature was heated to 370°C, after performing the same ion sputtering as in the above example, the chlorine gas pressure was changed from [X 1O-5 Torr to Ix 10-5~
This figure shows the change in etching rate and the angle formed between the side wall and the top surface of the substrate when the etching speed is changed up to 1×10 −4 Torr. In this temperature range, the vapor pressures of indium chloride and phosphorus chloride are sufficiently high, so that etching proceeds due to the chemical reaction between chlorine and indium phosphorus. The higher the chlorine pressure, the more side etching occurred on the sidewall. FIG. 8 shows experimental results in which InP was etched while varying the substrate temperature and chlorine gas pressure. The O mark in the figure indicates the point where the etched side wall is approximately vertical (θ-85 to 95 degrees).
The X marks are other points. Although vertical sidewalls can be obtained even if the substrate temperature exceeds 400° C., it is desirable that the substrate temperature be 400° C. or lower in order not to affect the device fabrication process.

If the substrate to be etched is InGaAsP, As
Since the vapor pressures of , P, and Ga chlorides are sufficiently higher than that of In chloride, the etching rate is determined by the In content, which has a low -1 vapor pressure. The optimum etching conditions for forming vertical sidewalls for InGaAsP are determined by the proportion of In in the Group II group, and are as follows. As for InP, as mentioned above, the substrate temperature is 350-400°C and the chlorine pressure I
X 10-' ~ I X 10--5 ~ 1x10-4T
orr, when the In ratio is 70% (1.3 μm composition when lattice matched to InP), the substrate temperature is 300-37
Chlorine pressure I x 10"" ~ I x 10-- at 0°C
5 to 1 x 10-4 Torr, when the In ratio is 60% (
1.55 μm composition for lattice matching to InP) Substrate temperature 280-380°C, chlorine pressure 1 x IO1-I
10--5 to 1 x 10-4 Torr% I n ratio is 5
At 0% (in the case of InGaAs lattice matched to InP)
Chlorine pressure I x 10-' at substrate temperature 250-350°C
~I X 10-' TO "". Also, as already mentioned, in the case of GaAs, the optimal conditions are a substrate temperature of 200 to 300° C. and a chlorine pressure of I X 10-' to I X 1O-3 Torr.

Note that the present invention is not limited to the embodiments described above. In the example, A is used as a method for removing the natural oxide film.
Although plasma etching of r is described, the present invention is not limited to this.

Other types of He, N2, etc. may be used, or 10
Baking at 100℃ may be performed in a high vacuum of 10-6 Torr or higher.However, if the degree of vacuum is poor (10-6 Torr or higher
The oxide film cannot be removed even if the substrate is heated to 350°C (of the order of r). In addition, the etching gas is not limited to chlorine; if it is a gas containing Group Ⅰ gases, such as Br, 1, etc., it is possible to obtain a vertical end surface by appropriately selecting the substrate temperature and gas pressure. be.

The present invention can also be applied to elements other than lasers that have vertical end faces, such as isolation devices and gate side walls of electronic devices.

In addition, the material system is InP/Ga1nAsP.

Other GaAs/GaA IAs series, 1n^1^S/
InGaAs system, InGaAIP/GaAs
The present invention can be applied to systems with lattice distortion, such as the l n P /Ga As system, with appropriate modifications. In addition, various modifications can be made without departing from the gist of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the step of forming a vertical end face of a laser according to the method of the first embodiment of the present invention, and FIGS.
4 is a process cross-sectional view showing a method of controlling the active layer width of a laser according to an embodiment of the present invention, FIG. 4 is a characteristic diagram showing the substrate temperature dependence of the etching rate and sidewall shape in thermal etching of a GaAs substrate, and FIG. 5 is a diagram showing the etching shape. 6 is a characteristic diagram showing the chlorine pressure dependence of the etching rate and sidewall shape in thermal etching of a GaAs substrate, and FIG. 7 is a characteristic diagram showing the chlorine pressure dependence of the etching rate and sidewall shape in thermal etching of an InP substrate. The characteristic diagram shown in Fig. 8 is Ga
As. A characteristic diagram showing the angular dependence of InP on temperature and pressure, and FIG. 9 is a perspective view showing a general etched shape by bromine-based etching. 11...Laser substrate, 12...5in2 mask, 21--n-1n P substrate, 22--n-1n P layer, 23-=n-1n GaAsP light guide layer, 24-=n-1n GaAsP active layer,
25...p-1nP cladding layer, 26--p-1nGaAsP:] contact layer, 27...Si02 mask, 28...semi-insulating 1nP buried layer

Claims (4)

[Claims] (1) For a compound semiconductor substrate or a compound semiconductor thin film formed on the substrate, a striped mask or a mask having striped openings is formed in a direction such that the etched sidewall becomes an inverted mesa shape when wet etching is performed. and then selectively etching the compound semiconductor substrate or the compound semiconductor thin film thereon by heating the compound semiconductor substrate to a predetermined temperature and exposing it to an atmosphere to which Group VII gas is applied at a desired pressure. A method for microfabrication of a compound semiconductor, comprising the steps of: (2) A step of forming an etching mask on a compound semiconductor substrate whose substrate surface is deviated from the (100) plane by 0 to 3 degrees, or on a compound semiconductor thin film formed on the substrate, and moving the etching mask in the [011] direction. a step of patterning in a stripe shape along a direction within a range of ±5 degrees, a step of removing a natural oxide film adhering to the area desired to be etched after patterning in this step, and a step of removing this natural oxide film. Subsequently, the compound semiconductor substrate is heated to a desired temperature and exposed to an atmosphere in which Group VII gas is applied at a desired pressure to side-etch the compound semiconductor substrate or the compound semiconductor thin film thereon from the mask. A method for microfabrication of a compound semiconductor, comprising the step of etching with. (3) InP is used as the compound semiconductor substrate or the compound semiconductor thin film thereon, chlorine gas is used as the Group VII gas, and the substrate temperature is set at 350 to 400°C.
, the pressure of the Group VII gas is 1×10^-^5~1×
2. The method for microfabrication of a compound semiconductor according to claim 1, wherein the pressure is set at 10^-^4 Torr. (4) GaAs is used as the compound semiconductor substrate or the compound semiconductor thin film thereon, chlorine gas is used as the Group VII gas, and the substrate temperature is set at 200 to 300.
℃, the pressure of the group VII gas is 1×10^-^5~1
2. The method for microfabrication of a compound semiconductor according to claim 1, wherein the pressure is set to x10^-^3 Torr.