JPH03280623A - Data signal decoder - Google Patents

Abstract

PURPOSE:To decode plural kinds of coding data different in transmission speed with simple constitution by providing a means inputting a 1st coding data or a 2nd coding data and generating a clock signal in compliance with the 2nd transmission rate and a means decoding the data synchronously with the clock signal. CONSTITUTION:The decoder is provided with a clock signal generating means (PLL circuit) 2 receiving a 1st coding data sent at a 1st transmission rate or a 2nd coding data sent at a 2nd transmission rate faster than the 1st transmission rate and generating a clock signal in compliance with the 2nd transmission rate. Moreover, a decoding means (decoding circuit) 1 decoding the 1st coding data or the 2nd coding data synchronously with the clock signal generated by the clock signal generating means 2 is provided. Thus, the coded data different in transmission rate is decoded with simple and inexpensive constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data signal decoding device for decoding a data signal.

[Prior Art] Conventionally, when transmitting a data signal or recording it on a recording medium and reproducing it, it has been necessary to transmit the data signal so that the data signal can be accurately transmitted or recorded and reproduced on the transmission path. After encoding, it was transmitted or recorded.

As the above-mentioned encoding method, there is, for example, MFM encoding method 7.

The MFM encoding method converts data words representing "1" to "0".
1”, and the data word representing °゛0 is changed to “10” if the previous data word represents “0”.
If the immediately preceding data word represents "1", it is converted to "00".

[Problems to be Solved by the Invention] By the way, when restoring a data signal transmitted or recorded by the MFM encoding method as described above, P L is used to form a clock signal synchronized with the supplied encoded data. L (P
(Locked Loop) circuit is required.

Furthermore, in recent years, the transmission speed of encoded data has been increased due to wider bandwidth of transmission systems, improved performance of recording media, etc., and it has become possible to transmit, record and reproduce more information.

However, when considering a device that restores encoded data transmitted or recorded using multiple types of transmission formats with different transmission speeds to the original data signal, the above-mentioned PLL circuit and decoding circuit are used for each transmission. There was a problem in that it had to be prepared for each style, resulting in a complicated configuration and high cost.

The present invention has been tried to solve the above-mentioned problems, and it is an object of the present invention to provide a data signal decoding device with a simple configuration and low cost.

[Means for Solving the Problem] The data signal decoding device of the present invention transmits first encoded data at a first transmission rate, or a second transmission rate higher than the first transmission rate. a clock signal forming means for inputting second encoded data transmitted at a second transmission rate and forming a clock signal conforming to a second transmission rate; and decoding means for decoding in synchronization with the clock signal formed by the forming means.

[Operation] With the above-described configuration, encoded data having different transmission rates can be decoded with a simple and low-cost configuration.

[Example code] Hereinafter, the present invention will be explained using examples of the present invention.

In addition, in this embodiment, in order to simplify the explanation, M is used as the encoding method.
The FM encoding method is used, and the transmission format includes a standard transmission mode and a double-density transmission mode having a transmission rate twice that of the standard mode. A data signal decoding device for restoring MFM encoded data transmitted in the mode or double-density transmission mode to the original data signal will be described.

First, FIG. 2 shows the correspondence between code words and decoded words in this embodiment.

Encoded data [xl X2 X3 X4
], if the encoded data transmitted in the standard transmission mode is [LX3], the pattern indicated by the arrow in the figure is the decoded data [Y] in the standard transmission mode.

In addition, encoded data transmitted in double-density transmission mode [
XI X2

As shown in the figure, by making the decoded data [Y] in the standard transmission mode and the decoded data [Y2] in the double-density transmission mode the same, a PLL circuit and a decoding circuit are provided for each transmission mode as described later. Encoded data provided by each transmission mode can be decoded by a single PLL circuit and decoding circuit without any problems.

FIG. 1 is a diagram showing a schematic configuration of a data signal decoding device that decodes encoded data into decoded data based on the correspondence table shown in FIG. 2 described above.

In FIG. 1, encoded data supplied from a transmission line or a playback device (not shown) is supplied to a decoding circuit 1, a PLL circuit 2,
is supplied to

The PLL circuit 2 performs a double-density transmission mode regardless of whether the input encoded data is encoded data transmitted based on the standard transmission mode or encoded data transmitted based on the double-density transmission mode. A clock pulse based on the data is formed and supplied to the decoding circuit 1.

Note that a reset pulse is supplied to the decoding circuit 1 from a system controller (not shown) at the start of the decoding operation.

FIG. 3 is a diagram showing a specific example of the configuration of the decoding circuit 1 shown in FIG. 1.

In FIG. 3, input encoded data is supplied to the data input terminal of flip-flop 3, clock pulses output from PLL circuit 2 are supplied to clock input terminals CK of flip-flops 31 to 36, and A reset pulse supplied from the illustrated system controller is supplied to reset input terminals R of flip-flops 35 and 36.

The flip-flop 31 operates according to the clock pulse input from the clock input terminal CK, and the signal output from the Q terminal of the flip-flop 31 is output from the ant gate 39.
．． 41 and 42 as well as the flip-flop 32 at the next stage, and the signal output from the page terminal is supplied to the AND gate 40.

Hereinafter, the flip-flops 32 to 34 similarly operate according to the clock pulse, and the Q of the flip-flops 32 to 34 is
The signals output from the AND gates 38 and 42 are supplied to any of the AND gates 38 to 42 as shown in the figure.
The output of the AND gates 39 to 42 is supplied to the data input terminal of the flip-flop 44, and the output of the AND gates 39 to 42 is supplied to the OR gate 4.
3 to the data input terminal of the flip-flop 45.

On the other hand, the flip-flops 35 and 36 and the exclusive OR gate 37 decode the data clock from the clock pulse supplied from the PLL circuit 2, and the signal output from the page terminal of the flip-flop 36 is output as the decoded data clock. It is also supplied to the clock input terminal CK of flip-flops 44 and 45.

The flip-flops 44 and 45 operate according to the decoded data clock output from the flip-flop 36, and the Q terminal of the flip-flop 44 outputs decoded data [Y1] in the double-density transmission mode. From the terminal, decoded data [Y2] in double-density transmission mode or decoded data [Y2] in standard transmission mode is sent.
] is output.

As described above, the data signal decoding apparatus shown in FIGS. 1 and 3 uses a single PLL circuit and decoding circuit to decode 1 bit each time 4-bit encoded data is input in the standard transmission mode. data is 2 when in double-density transmission mode.
Bit decoded data is output.

In addition, although this embodiment has been described using an example of a device that decodes data encoded by the MFM encoding method, the present invention is not limited to this, and the present invention can be applied to data encoded by other encoding methods. It is also applicable to devices that decode .

[Effects of the Invention] As explained above, according to the present invention, it is possible to provide a data signal decoding device with a simple configuration and low cost.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a schematic configuration of a data signal decoding device as an embodiment of the present invention. FIG. 2 is a diagram showing the correspondence between code words and decoded words in one embodiment of the present invention. FIG. 3 is a diagram showing a specific example of the configuration of the decoding circuit shown in FIG. 1. 1...Decoding circuit 2...PLL circuits 31 to 36, 44.45...Flip-flop 37.
・・Exclusive or Gate 38-42・Ant Gate 43・Agate

Claims (1)

[Claims] First encoded data transmitted at a first transmission rate,
Alternatively, input the second encoded data transmitted at a second transmission rate higher than the first transmission rate, and
a clock signal forming means for forming a clock signal in accordance with a transmission rate of; and a decoding device for decoding the first encoded data or the second encoded data in synchronization with the clock signal formed by the clock signal forming means. A data signal decoding device characterized by comprising means.