JPH03280428A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH03280428A
JPH03280428A JP7990290A JP7990290A JPH03280428A JP H03280428 A JPH03280428 A JP H03280428A JP 7990290 A JP7990290 A JP 7990290A JP 7990290 A JP7990290 A JP 7990290A JP H03280428 A JPH03280428 A JP H03280428A
Authority
JP
Japan
Prior art keywords
silicon nitride
mask
oxide film
silicon
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7990290A
Other languages
Japanese (ja)
Inventor
Takao Tanaka
隆夫 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7990290A priority Critical patent/JPH03280428A/en
Publication of JPH03280428A publication Critical patent/JPH03280428A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To avoid the occurrence of a bird's beak for enhancing the integration by a method wherein, during the formation process of an element isolation region by selective oxidation, a mask is formed not to make a silicon oxide film 2 lie between the end of a thermal resistant mask film and a silicon substrate. CONSTITUTION:A thermal oxide film 2 is formed on a silicon substrate 1 and then a photoresist mask 3a having opening parts along the edge of an element isolating region is pattern-formed to form nitrogen ion implanted regions 4 which are heat treated, after removing the silicon thermal oxide film 2, to be converted into local silicon nitride films 5a. Next, after burying the thin oxide film 2 at the peripheral part of the silicon nitride films 5a on the silicon substrate 1, the silicon nitride film 5 is thermal-oxidized and then deposited. Later, a silicon nitride film mask 5b pattern-formed by the conventional process using a photo resist mask 3b is pressure-oxidized, an element isolating region 6 is formed and then the silicon nitride film 5b and the thin oxide film 2 are removed to expose an element formation region 7.

Description

【発明の詳細な説明】 【産業上の利用分野] 本発明は、半導体装置の製造方法に関し、特に選択熱酸
化法を用いた素子分離領域の形成方法に関する。 [従来の技術1 第3図 fat〜fdlは従来の半導体装置における素
子分離領域の形成工程図である。すなわち、シリコン基
板lの上に50nlIl程度の厚さの熱酸化膜2を生成
した後、シリコン窒化膜5(Sx3N41を気相成長法
で厚さ1100n程度堆積し〔第3図(at参照]、つ
ぎに、シリコン窒化膜マスク5bをホトレジスト・マス
ク3bを介してパターン形成し[第3図fb)参照] 
ついで、シリコン窒化膜がもつ耐熱性を利用した加圧熱
酸化を行い素子分離領域6を形成するものである【第3
図[C) 参照〕。ここで、不要となったシリコン窒化
膜マスク5bを除去すれば、素子形成領域7を得るこ、
とができる[第3図(dl参照]。 [発明が解決しようとする課題] しかしながら、上述した従来の素子分離領域の形成方法
は、シリコン窒化膜5を堆積するに先立って基板内の結
晶欠陥を防ぐ目的で熱酸化膜2を形成する必要があるた
め、加圧酸化工程でシリコン窒化膜のマスクの端部下に
厚い酸化膜が入り込みバーズビーク10を発生する欠点
がある。このバーズビーク10の領域は、素子分離領域
7を縮小する無駄な面積でしかないので、素子の集積度
を低下させる。 本発明の目的は、上記の情況に鑑み、バーズピークの形
成を低減し得る選択的熱酸化法による素子分離領域の形
成工程を備えた半導体装置の製造方法を提供することで
ある。 [課題を解決するための手段] 本発明によれば、半導体装置の製造方法は、選択酸化に
よる素子分離領域の形成工程において、前記選択酸化で
用いる耐熱性マスク膜の端部とシリコン基板との間にシ
リコン酸化膜を介在せしめないようマスク形成を行うこ
と含んで構成される。 [作  用  ] 本発明によれば、素子分離領域を加圧酸化形成する際、
耐熱性マスク膜の端部には、この下側に入り込む熱酸化
膜が介在していないので、素子分離領域の端部に無駄な
面積を生じるバズビークの生成を低減することができる
。 [実施例〕 次に、本発明について図面を参昭して説明する。 第1図 (a)〜(h)は本発明の一実施例を示す素子
分離領域の形成工程図である。本実施例によれば、第1
図fa)のように、従来と同じくまずシリコン基板I上
に厚さ50nmの熱酸化膜2を生成する。つぎに、第1
図fbl に示すように、形成すべき素子分離領域の端
縁に沿って帯状の開口部をもつホトレジスト・マスク3
aをパターン形成して[第1図+bl参照]、基板1内
に窒素(N2)を深さ50r+m、 6度1O18〜1
019CIn−3となるようにイオン注入し窒素イオン
注入領域4を形成する[第1図(Cl 参照]。ついで
、マスクとして使用したシリコン熱酸化11! 2を除
去した後、900〜1100℃の温度の熱処理を行い窒
素イオン注入領域4を局所的なシリコン窒化膜(313
N4)  5 aに変換する[第1図tdl 参り召1
゜つぎに、熱酸化を行いシリコン基板1上にシリコン窒
化膜5aの周辺を厚さ50nmの薄い酸化膜2で埋めた
後、さらに気相成長法によりシリコン窒化1]fffS
zJ4)  5を堆積する〔第1図(e)参昭1゜以下
は従来法と同じく、第】図iflのように、ホトレジス
ト・マスク3bを用いてシリコン窒化膜マスク5bをパ
ターン形成して加圧酸化を行い、素子分離領域6を形成
する〔第1図fg) ?’照〕。あとは不要となったマ
スクのシリコン窒化M5bと薄い酸化膜2を除去して素
子形成領域7を露出させる[第1図fh) を照〕。 本実施例から明らかなように、本発明によれば、シリコ
ン窒化膜マスクの周端部からバーズビークの形成要因と
なるシリコン熱酸化膜が除去されるので、バーズビーク
の形成は低減される。 第2図 (a)〜(flは本発明の他の実施例を示す素
子分離領域の形成工程図である。本実施例によれば、シ
リコン基板lの表面にはプラズマCVD法による窒化シ
リコン酸化膜(SiONl 8が従来の如くシリコン熱
酸化膜2を介することなく、150nmの厚さに直接堆
積される。このときプラズマダメージ層9がシリコン基
板lの面上に生ずる[第2図ia) 参照1゜この窒化
シリコン酸化膜(SiONl 8をホトレジスト・マス
ク3bを用いてパターニングして耐熱性のマスク8bを
形成し[第2図fbl参昭1、ついで従来と同様、この
マスク8bを用いた加圧酸化法により素子絶縁領域6を
形成する[第2図(cl参昭]。つぎに、不要となった
マスク8bを除去して素子形成領域7を露出させ[第2
図(dl参照j、更にこの表層を厚さ50nm程度酸化
して、プラズマダメージ層9を取り除く [第2図fe
)堅昭]。あとは、この素子形成領域7上から薄い酸化
膜2を除去すれば全工程は終了する。 本実施例では、バーズビークの形成要因となるシリコン
熱酸化膜をiii、を熱性マスク下に最初から形成して
いないので、バーズビークの形成を有効に阻止すること
ができる。また、面j熱性マスク材に低温成長(約30
0℃)のプラズマCVD法による窒化シリコン酸化11
Q fsiON)を用いたのは、シリコン基板との熱膨
張係数差によるストレスを少なくするためである。すな
わち、プラズマCVD法によるシリコン窒化11Q(S
+3N+1と比較しても生じるストレスは約旨と小さい
ので作業の信頼性を向上できる効果がある。 [発明の効果1 以上詳細に説明したように、本発明によれば、選択的に
加圧酸化するシリコン窒化膜などの耐熱性マスクの端部
とシリコン基板との間には加圧酸化の際、マスク股下へ
入り込む酸化膜が除去され、これが存在しないようにマ
スク膜が堆積されるので、バーズビークの発生を抑えて
集積度を向上できる効果がある。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an element isolation region using a selective thermal oxidation method. [Prior Art 1] FIG. 3 fat to fdl are process diagrams for forming element isolation regions in a conventional semiconductor device. That is, after a thermal oxide film 2 with a thickness of about 50nIl is formed on a silicon substrate l, a silicon nitride film 5 (Sx3N41) is deposited with a thickness of about 1100n by a vapor phase growth method [see Fig. 3 (at)]. Next, a silicon nitride film mask 5b is patterned through a photoresist mask 3b [see FIG. 3 fb)]
Next, the element isolation region 6 is formed by performing pressure thermal oxidation utilizing the heat resistance of the silicon nitride film.
See figure [C]]. Here, by removing the silicon nitride film mask 5b which is no longer needed, the element formation region 7 can be obtained.
[See Figure 3 (dl)] [Problems to be Solved by the Invention] However, in the conventional method for forming an element isolation region described above, prior to depositing the silicon nitride film 5, crystal defects in the substrate are removed. Since it is necessary to form a thermal oxide film 2 for the purpose of preventing this, there is a drawback that a thick oxide film gets under the edge of the silicon nitride film mask during the pressure oxidation process, creating a bird's beak 10.The area of this bird's beak 10 is , it is only a wasted area for reducing the element isolation region 7, which reduces the degree of integration of the element.In view of the above circumstances, an object of the present invention is to provide a selective thermal oxidation method that can reduce the formation of bird's peaks. An object of the present invention is to provide a method for manufacturing a semiconductor device including a step of forming an isolation region. [Means for Solving the Problems] According to the present invention, a method for manufacturing a semiconductor device includes forming an isolation region by selective oxidation. The formation step includes forming a mask so that no silicon oxide film is interposed between the end of the heat-resistant mask film used in the selective oxidation and the silicon substrate. [Function] According to the present invention For example, when forming an element isolation region by pressure oxidation,
Since there is no thermal oxide film intervening at the end of the heat-resistant mask film, which penetrates underneath, it is possible to reduce the generation of buzz beaks that cause wasted area at the end of the element isolation region. [Example] Next, the present invention will be explained with reference to the drawings. FIGS. 1(a) to 1(h) are process diagrams for forming element isolation regions showing one embodiment of the present invention. According to this embodiment, the first
As shown in FIG. fa), a thermal oxide film 2 having a thickness of 50 nm is first formed on a silicon substrate I as in the conventional method. Next, the first
As shown in Figure fbl, a photoresist mask 3 with band-shaped openings along the edge of the element isolation region to be formed
A is patterned [see Figure 1 + BL], and nitrogen (N2) is applied in the substrate 1 to a depth of 50 r + m, 6 degrees 1O18~1
Nitrogen ion implantation region 4 is formed by ion implantation to form 019CIn-3 [see Figure 1 (Cl)].Next, after removing silicon thermal oxidation 11!2 used as a mask, the silicon ion implantation region 4 is heated at a temperature of 900 to 1100°C. The nitrogen ion implantation region 4 is covered with a local silicon nitride film (313
N4) 5 Convert to a [Figure 1 tdl Prayer 1
゜Next, after performing thermal oxidation and filling the periphery of the silicon nitride film 5a on the silicon substrate 1 with a thin oxide film 2 with a thickness of 50 nm, silicon nitride 1]fffS is further formed by vapor phase growth.
zJ4) Deposit 5 [see Fig. 1(e) 1゜The following steps are the same as the conventional method; as shown in Fig. Perform pressure oxidation to form element isolation regions 6 (FIG. 1fg)? 'Shine]. After that, the silicon nitride M5b and thin oxide film 2 of the mask which are no longer needed are removed to expose the element formation region 7 [see FIG. 1 fh]. As is clear from this embodiment, according to the present invention, the silicon thermal oxide film that causes the formation of bird's beaks is removed from the peripheral edge of the silicon nitride film mask, so the formation of bird's beaks is reduced. FIG. 2 (a) to (fl are process diagrams for forming element isolation regions showing other embodiments of the present invention. According to this embodiment, silicon nitride oxide is formed on the surface of the silicon substrate l by plasma CVD. A film (SiONl 8) is directly deposited to a thickness of 150 nm without intervening a silicon thermal oxide film 2 as in the conventional method. At this time, a plasma damaged layer 9 is formed on the surface of the silicon substrate l [see Fig. 2 ia). 1. This silicon nitride oxide film (SiONl 8) was patterned using a photoresist mask 3b to form a heat-resistant mask 8b [see Fig. The element insulating region 6 is formed by a pressure oxidation method [see FIG.
Figure (see dl j) Further, this surface layer is oxidized to a thickness of about 50 nm to remove the plasma damage layer 9 [Figure 2 f
) Kenaki]. After that, the entire process is completed by removing the thin oxide film 2 from above the element forming region 7. In this embodiment, since the silicon thermal oxide film iii, which is a factor in the formation of bird's beak, is not formed from the beginning under a thermal mask, the formation of bird's beak can be effectively prevented. In addition, low-temperature growth (approximately 30%
Silicon nitride oxidation by plasma CVD method at 0°C) 11
Q fsiON) was used to reduce stress due to the difference in thermal expansion coefficient with the silicon substrate. That is, silicon nitride 11Q (S
Even when compared to +3N+1, the stress generated is about as small as that, so it has the effect of improving work reliability. [Effects of the Invention 1] As explained in detail above, according to the present invention, there is a gap between the edge of a heat-resistant mask such as a silicon nitride film that is selectively oxidized under pressure and the silicon substrate during oxidation under pressure. Since the oxide film that enters the crotch of the mask is removed and the mask film is deposited so as not to exist, it is possible to suppress the occurrence of bird's beak and improve the degree of integration.

【図面の簡単な説明】[Brief explanation of drawings]

第1図 (a)〜(h)は本発明の一実施例を示す素子
分離領域の形成工程図、第2図 (a)〜fflは本発
明の他の実施例を示す素子分離領域の形成工程図、第3
図 (al〜fd)は従来の半導体装置における素子分
離領域の形成工程図である。 1−・シリコン基板、 2・・・シリコン熱酸化膜、 3.3a、3b−・・ホトレジスト・マスク、4・・・
窒素イオン注入領域、 5.5a−・−シリコン窒化膜、 5b・・−シリコン窒化膜マスク、 6・・・素子分離領域、 7・・・素子形成領域、 8−・−窒化シリコン酸化膜(SiONl、8b・・・
窒化シリコン酸化膜マスク、9・・・プラズマダメージ
層、 10−・−バーズビーク。 特 許 出 願 人 日本電気株式会社
Fig. 1 (a) to (h) are process diagrams for forming an element isolation region showing one embodiment of the present invention, and Fig. 2 (a) to ffl are forming process diagrams of an element isolation region showing another embodiment of the present invention. Process diagram, 3rd
Figures (al to fd) are process diagrams for forming element isolation regions in conventional semiconductor devices. 1- Silicon substrate, 2 Silicon thermal oxide film, 3.3a, 3b- Photoresist mask, 4...
Nitrogen ion implantation region, 5.5a--Silicon nitride film, 5b--Silicon nitride film mask, 6--Element isolation region, 7--Element formation region, 8--Silicon nitride film (SiONl) , 8b...
Silicon nitride oxide film mask, 9... plasma damage layer, 10-...bird's beak. Patent applicant NEC Corporation

Claims (1)

【特許請求の範囲】[Claims]  選択酸化による素子分離領域の形成工程において、前
記選択酸化で用いる耐熱性マスク膜の端部とシリコン基
板との間にシリコン酸化膜を介在せしめないようマスク
形成を行うことを特徴とする半導体装置の製造方法。
A semiconductor device characterized in that, in the step of forming an element isolation region by selective oxidation, the mask is formed so that no silicon oxide film is interposed between the end of the heat-resistant mask film used in the selective oxidation and the silicon substrate. Production method.
JP7990290A 1990-03-28 1990-03-28 Manufacture of semiconductor device Pending JPH03280428A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7990290A JPH03280428A (en) 1990-03-28 1990-03-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7990290A JPH03280428A (en) 1990-03-28 1990-03-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03280428A true JPH03280428A (en) 1991-12-11

Family

ID=13703216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7990290A Pending JPH03280428A (en) 1990-03-28 1990-03-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03280428A (en)

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