JPH03278021A - Drive control circuit - Google Patents

Abstract

PURPOSE:To automatically correct a change in the output performance, especially DC level, of a liquid crystal cell driving circuit due to a temperature change, a secular change or the dispersion of elements by inserting reference level information into a blanking period. CONSTITUTION:A reference signal inserting part 10 inserts a certain determined reference level into the prestage of an area allotted to driving circuits 22-1 to 22-N including a part of horizontal blanking period of a video signal. The forefront stages of shift registers included in the circuits 22-1 to 22-N are detected by a timing generating circuit connected independently of respective circuits 22-1 to 22-N. Since respective circuits 22-1 to 22-N have holding circuits in their input stages, the DC component of each signal can be corrected by a DC shifting circuit (clamp circuit) on the input stage in accordance with a voltage level to be a difference from a reference level outputted from an output stage. Consequently, a change in the I/O characteristics, especially an output DC level, of the liquid crystal driving circuit due to temperature drift, a secular change, the dispersion of each element itself, etc., can be automatically corrected.

Description

[Detailed description of the invention]

[Industrial Application Field 1] The present invention relates to a drive control circuit. More specifically, the present invention relates to a drive control circuit for a liquid crystal display device, which is suitable for application to, for example, a liquid crystal projection display device. 1 Summary of the Invention 1 The present invention provides a method for blocking image signals in order to automatically correct changes in the input/output characteristics of a liquid crystal drive circuit, especially the output DC level, due to temperature drift, aging, variations in the elements themselves, etc. A reference level is stored during the ranking period, and the output DC level is made to follow the reference level. ] Prior Art l As is known in the art, an integrated driving circuit is connected to each cell in order to control the light transmittance of a liquid crystal display element. In order to maintain the output characteristics of this drive circuit constant, it is necessary to improve the external environmental conditions in response to environmental changes (for example,
forced air cooling using a fan). Further, the characteristics of each liquid crystal cell and the drive circuit itself are also sufficiently adjusted before shipping. [Problems to be Solved by the Invention] However, as the output of the drive circuit, that is, the drive output for controlling the brightness (light transmittance) of the liquid crystal cell, gradually fluctuates in level with aging, it is difficult to This has the disadvantage that a clear image display cannot be obtained. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a drive control circuit configured such that the output of a liquid crystal cell drive circuit can always maintain a predetermined level.

[Means for Solving the Problems j] A drive control circuit for a liquid crystal display device according to the present invention includes an insertion means for inserting information representing a reference level value into a blanking period of an input image signal, and an output of the insertion means. an analog shift register connected to the side and formed by cascading a plurality of drive circuits for driving the liquid crystal cells; a holding means for extracting and holding the reference level value included in the image signal; and the drive circuit. calculation means for calculating the difference between the level value in the blanking period of the image signal shifted by and the reference level value held by the holding means; and an input of the drive circuit in response to the output of the calculation means and level control means for variably controlling the level. [Function 1] According to the present invention, the predetermined level of the liquid crystal cell drive circuit is monitored based on the reference level information inserted into the blanking period of the image signal, and feedback control is performed so that the predetermined level maintains the reference level. It can be performed. Specifically, a reference signal insertion section inserts a certain reference level at the front stage of the region assigned to the drive circuit, which includes a part of the horizontal blanking period of the video signal. Then, a separately provided timing generation circuit detects the first stage of the shift register in each drive circuit (the terminal to which the earliest data is output in terms of time). LCD cell drive circuit. The input stage has a hold circuit to hold the reference level, and the difference voltage level from the reference level output from the output stage (first stage or cascade connected element) is used to control the input stage DC shift circuit (clamp). circuit) to correct the DC component of the signal. Note that the driving circuit for the liquid crystal cell may have a direct current or parallel-connected configuration. [Example 1] Hereinafter, the present invention will be explained in detail based on an example. FIG. 1 is a block diagram showing one embodiment of the present invention. This figure shows a circuit that processes the R signal among the RG-8 signals, and similar circuits are required for other G and B signals. In FIG. 1, 2 is an input terminal for an image signal. In this embodiment, the configuration is such that an R signal is input, but other luminance signals, color difference signals, etc. may be used. In addition, when displaying high-definition signals, MU
The SE signal is decoded into an R-G-B signal and supplied to this input terminal 2. 4 is an A/D converter, 6 is a digital signal processing (DSP)
) Department. 8 is a circuit that generates a reference level to be inserted into the blanking period of the image signal. IO is an insertion section for inserting reference level information into the blanking period (point A shown on the left side of FIG. 1). 12 is a D/A converter. Here, the A/D converter 4 at the input stage is a function that is normally required for digital processing when correcting a signal with a filter or the like before applying it to a display device for the purpose of improving image quality. This correction signal processing is unnecessary in systems that do not require it. In addition, these correction signal processing units are integrated into a DSP (DIGIT
This block is called the ALSIGNAL PROCESSING) unit 6, and is used to perform parallel placement processing due to the operating speed limit of the drive circuit. Further, in this figure, the reference signal insertion section 1O is configured to perform digital processing, but this processing can essentially be realized by either digital or analog processing. As a matter of course,
The D/A converter 12 is unnecessary if the DSP unit 6 is omitted, and is also omitted if the input to the drive circuit unit 22 described later is digital. A control section for driving each liquid crystal cell is connected downstream of the pre-processing section described above. Here, 14 is a buffer circuit, 16 is a hold circuit that samples and holds the reference level (the level at point A shown on the left side of FIG. 1) inserted into the blanking period of the image signal, and 18 is a differential amplifier. 20 is a clamp circuit FET for holding the input side DC level of the liquid crystal cell drive circuit 20-1 at a predetermined value (e+-ei). 22-1 to 22-N are liquid crystal cell drive circuits which output an analog voltage (transmittance control voltage) for driving the liquid crystal cell and also function as an analog shift register. A hold circuit 1 is connected to the non-inverting input terminal of the differential amplifier described above.
The reference level e, (A
In addition, the level e2 corresponding to the blanking period of the delay signal sent from the shift output terminal of the drive circuit 20-1 is input to the other inverting input terminal.
is input. Therefore, (e+-ex) is output to the output terminal of the differential amplifier 18. This output (e+-ea) is FE
Since the source potential of T20 is set to (e+-ex),
The output side DC level of the drive circuit 22-1 can be controlled to be maintained at a constant value. Specifically, when the output DC level of the drive circuit 22-1 decreases due to aging etc., e2 decreases, so the output level (e+-ex) of the differential amplifier 18 increases, and as a result, As a result, the input side DC level of the drive circuit 22-1 is raised, and ultimately the output side DC level of the drive circuit 22-1 is held at a predetermined value. 30 is a timing signal generation unit, which generates a timing signal TA for triggering the reference level insertion unit IO;
Timing signal T for triggering hold circuit 16
,, Outputs a timing signal for causing the FET 20 to perform a clamping operation. In this way, a certain reference level is inserted into the horizontal blanking period, and the video signal including this is sent to the drive circuit 22.
Enter -1. Then, a timing signal T corresponding to the reference level is output from the timing signal generator 30 and synchronized, and at the same time, the timing signal T corresponding to the reference level is output by the hold circuit 16 for a period until this voltage level is shifted and output from the drive circuit 22-1. Hold. Next, the held level e1 and the output level e1 of the drive circuit are input to the differential amplifier 18, and the difference component (e+-ex) is
Output. By using this difference component voltage level as, for example, the source potential of a field effect transistor, the DC potential of the drive circuit input section is controlled and offset components due to characteristic fluctuations of the drive circuit are removed. The subsequent drive circuit 22-N also operates in the same manner. Note that the drive circuit may be of a cascade-connected type or of a parallel-connected type. Effects of the Invention As explained above, according to the present invention, since the reference level information is inserted into the blanking period, the output performance of the liquid crystal cell drive circuit can be affected by temperature changes, aging changes, and element variations. Changes in DC level can be automatically compensated for. In addition, not only can image quality be ensured by correcting temperature changes and secular changes, but also variations in the drive circuit (- integrated circuit for boat fishing) itself can be automatically corrected, making adjustments at the time of product shipment. No longer needed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 2... Image signal input terminal, 4... A/D converter, 6... Digital signal processing section, 8... Reference level generator, IO... Reference level insertion section, 12... D/
A converter, 14... Buffer circuit, 16... Hold circuit, 18... Differential amplifier, 20... FET. 22-1 to 22-N...Liquid crystal cell drive circuit.

Claims (1)

[Claims] 1) Insertion means for inserting information representing a reference level value into the blanking period of an input image signal; and a drive circuit connected to the output side of the insertion means for driving a liquid crystal cell. an analog shift register consisting of a plurality of cascade-connected analog shift registers; a holding means for extracting and holding the reference level value included in the image signal; and a level value during the blanking period of the image signal shifted by the drive circuit; , further comprising: calculation means for calculating a difference from the reference level value held by the holding means; and level control means for variably controlling the input level of the drive circuit in response to the output of the calculation means. Features a drive control circuit.