JP3190426B2 - Video signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus, and more particularly to a TFT (Thin Film Transistor).
The present invention relates to a video signal processing device suitable for supplying a video signal to a liquid crystal display device.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a conventionally used video signal processing device for a TFT liquid crystal display device. The pedestal level of the video signal applied to the input terminal 1 becomes a voltage V _BR ′ determined by the brightness control voltage V _BR by the clamp circuit 2. Gate pulse B ₁ applied to the clamp circuit 2 is supplied in synchronization with the video signal to the back porch portion of the video signal. The output signal A and the gate pulse B ₁ of the clamp circuit 2 of FIG. 4 (a), shown in (b).

The output signal A of the clamp circuit 2 is input to a polarity inverting / amplifying circuit 3, where the polarity is inverted in response to an inversion control signal C that switches between high and low every horizontal cycle, and the polarity is inverted. It is amplified by 15 dB. This is because the polarity of the video signal input to the TFT liquid crystal display device is preferably inverted every horizontal cycle in view of the life of the liquid crystal display device, and the amplitude from the black level to the white level is 3.5 V to 4.5.
This is because about V is required. The output signal D of the polarity inversion / amplification circuit 3 and the inversion control signal C are shown in FIGS.
Shown in

The output signal D of the polarity inverting / amplifying circuit 3 is led to an output terminal 5 via a buffer 4 and output to a TFT liquid crystal display (not shown). In this buffer 4, the detection circuit 6 so that the DC voltage of the output is V _C,
A loop circuit including a V _C voltage source 7 and an error amplifier 8 is provided, and is controlled by the loop circuit. This is TF
This is because the DC component of the video signal applied to the T liquid crystal display device is always set to a constant value (V _C ), and is necessary to ensure the reliability of the liquid crystal display device. The above devices are required for R, G and B, respectively, for a color TFT liquid crystal display device.

[0005]

In the above-mentioned conventional apparatus, the video signal input from the input terminal 1 is clamped to a pedestal level, and is then supplied to the amplifier circuit by about 15 dB.
Amplified. In order to drive the color TFT liquid crystal display device, the signal processing device shown in FIG. 3 is necessary for each of R, G, and B. When a difference occurs in the pedestal clap level among R, G, and B, This is amplified by the amplifying circuit, and the output terminal has a non-negligible difference among R, G, and B, which causes a problem such as a wrong white balance of the TFT liquid crystal display device. For example, when a difference of 20 mV occurs between the pedestal levels among R, G, and B, 11
A difference of about 0 mV occurs. In practice, it is expected that some difference will occur in the gain of the amplifier circuit, and the difference may be further increased.

[0006] With the advent of liquid crystal projectors and the enlargement of the screen of a video display device using a TFT liquid crystal display device, the demand for reducing the difference between R, G, and B for the video signal processing device has increased. In view of the above, an object of the present invention is to provide a video signal processing device having a small difference in pedestal level between R, G, and B output signals.

[0007]

According to the present invention, there is provided a DC voltage inserting means for inserting a DC voltage corresponding to a brightness control voltage during a blanking period of a video signal. Polarity inverting / amplifying means for inverting and amplifying the polarity of the video signal in which the DC voltage is inserted during the blanking period every horizontal cycle by an inversion control signal, and inserting the video signal into the output signal of the polarity inverting / amplifying means. a DC voltage, and clamping means for each clamping during conjunction with reversed when the non-inverted to the inversion control signal, a clamp voltage by the clamp means and a clamping voltage generating means for generating in conjunction with the inverted control signal R was , G, B movies
The brightness control voltage is provided in each of the image signal processing systems.
And the clamp voltage to the R, G, B video signal processing system
They are given in common.

[0008]

[0009]

With the above arrangement, the input video signal is supplied with a DC voltage according to the brightness control voltage during the blanking period by the DC voltage insertion means, and then the polarity is inverted every horizontal cycle by the polarity inversion / amplification means. Is inverted, and is amplified so that the amplitude from the black level to the white level becomes a predetermined value. Thereafter, the pedestal level is clamped by a clamp voltage whose polarity is inverted every horizontal cycle by a clamp circuit, and a video signal for driving the liquid crystal display device is derived. In the case of color display, the same signal processing is performed by the circuit having the same configuration for each of the R, G, and B video signals.

[0010]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1, portions corresponding to those of the conventional example shown in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 1, reference numeral 10 denotes a DC voltage generation circuit that derives a control voltage V _BR ′ corresponding to the bright control voltage V _BR , and reference numeral 9 denotes a video signal A of FIG. This is a switching circuit that switches to the control voltage V _BR ′ from the DC voltage generation circuit 10 by the gate pulse B ₂ shown in FIG.

[0011] 12 to V _{B '1} inverted signal of the video signal F shown in FIG. 2 (e) which is inverted every one horizontal period by the inverting control signal C shown in FIG. 2 (f), also a non-inverted signal a clamping voltage generating circuit constituted by an operational amplifier or the like for generating the 'clamp voltage V _B for clamping the _{2' 1,} V _{B '2} V _B, 2 11 which is derived from the polarity inversion-amplifying circuit 3
The inversion control signal C showing the video signal F in FIG. 2 (f) shown in (e), the period of the gate pulse B ₁ shown in FIG. 2 (b), the clamp voltage V _{B '1} from the clamping voltage generating circuit 12 , V _B ' ₂ .

Next, the operation of FIG. 1 will be described. The video signal applied to the input terminal 1 is clamped by the clamp circuit 2 so that the pedestal level becomes _VA . Further, the gate pulse B ₁ represents given in synchronization with the back porch portion of the video signal. The video signal A and the gate pulse B ₁ output from the clamp circuit 2 FIG. 2 (a), the shown (b).

[0013] In the next switch circuit 9, the period during which the gate pulse B ₂ is turned on is switched to the voltage V _BR 'from DC voltage generating circuit 10 for generating in response to the bright control voltage V _BR. The gate pulse B ₂ is synchronized with the video signal, the on period from the gate pulse B ₁ toward the back porch portion of the horizontal sync portion given long. The output signal E of the switching circuit 9, and FIG. 2 (c) of the gate pulse B _2, shown in (d).

The video signal E derived from the switch circuit 9
In the polarity inversion / amplification circuit 3, the polarity is inverted according to the inversion control signal C shown in FIG.
It is amplified and becomes a video signal F as shown in FIG.
In the video signal F, the voltage V _BR ′ of the part inserted by the switch circuit 9 is clamped to the clamp voltage V _B ′ in the next clamp circuit 11. At this time, the inversion control signal C is input to the clamp circuit 11, and the inversion / non-inversion signal is clamped every horizontal cycle.

Meanwhile, the clamp voltage V _B 'also V _B for each one horizontal period in response to the inverted control signal' ₁ and V _{B '2} is switched.
Therefore, as shown in FIG. 2 (g), the inverted video signal G is clamped to V _B ′ ₁ and the non-inverted signal is clamped to V _B ′ ₂ for each horizontal cycle. In this embodiment, when generating the clamp voltage V _B ′, the operational amplifier 1
Although the clamp voltage generating circuit using the circuit No. 2 is used, the present invention is not limited to this.

FIG. 2 output from the clamp circuit 11
The inverted video signal G shown in (g) is controlled by a loop including the buffer 4, the detection circuit 6, the _VO voltage generation source 7, and the error amplifier 8 so that its DC voltage becomes V _C , as in the conventional example, and the output terminal. 5 is output.

In this embodiment, since the clamp circuit 11 performs clamping after the polarity inversion / amplification circuit 3, even if a difference occurs in the clamp level, the difference is not amplified. When driving a color TFT liquid crystal display device, the difference in pedestal level between R, G, and B of the output signal can be reduced by making the clamping voltage common to R, G, and B. For example, even if a difference of 20 mV occurs in the pedestal level in the clamp circuit 11, the difference in the pedestal level of the output remains at 20 mV and is not amplified.

[0018]

Since the present invention is the above configuration, it is possible to reduce variations of the pedestal level Rutotomo
In addition, video signal processing with a small difference in pedestal level among the R, G, and B output signals can be performed, and a deviation in white balance can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of the present invention.

FIG. 3 is a configuration diagram of a conventional technique.

FIG. 4 is an operation explanatory diagram of a conventional technique.

[Explanation of symbols]

 3 polarity inversion / amplification circuit 9 switch circuit 10 DC voltage generation circuit 11 clamp circuit 12 clamp voltage generation circuit

Claims (1)

(57) [Claims] 1. A DC voltage inserting means for inserting a DC voltage according to a bright control voltage during a blanking period of a video signal, and inversion control of the video signal having a DC voltage inserted during the blanking period by the DC voltage inserting means. A polarity inverting / amplifying means for inverting and amplifying the polarity every one horizontal cycle by a signal, and a DC voltage inserted in an output signal of the polarity inverting / amplifying means when inverting in conjunction with the inversion control signal. the non-inverting and clamping means for each clamp when, R a clamping voltage generating means for the clamp voltage by the clamp means generating in conjunction with the inverted control signal, G, each image B
Provided in each signal processing system,
The clamp voltage is common to the R, G, and B video signal processing systems.
Video signal processing apparatus is characterized in that as given in passing.