JP2571973B2 - Drive control circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a drive control circuit.

More specifically, the present invention relates to a drive control circuit of a liquid crystal display device, which is preferably applied to, for example, a liquid crystal projection display device.

[Summary of the Invention] The present invention provides a method for automatically correcting a change in input / output characteristics of a liquid crystal drive circuit, particularly a change in an output DC level due to a temperature drift, an aging change, and a variation of an element itself. The reference level is stored during the ranking period, and the output DC level is to follow the reference level.

[Prior Art] As is conventionally known, an integrated drive circuit is connected to each cell in order to control the light transmittance of a liquid crystal display element.

In order to maintain the output characteristics of the drive circuit constant, external environmental conditions are improved in response to environmental changes (for example, forced air cooling is performed using a fan).

In addition, the characteristics of each liquid crystal cell and the drive circuit itself are sufficiently adjusted at the time of shipment.

[Problems to be Solved by the Invention] However, since the output of the driving circuit, that is, the driving output for controlling the luminance (light transmittance) of the liquid crystal cell, gradually changes with time, there is a gradual change in the level of the output. There is a disadvantage that it is impossible to obtain a proper image display.

Accordingly, an object of the present invention is to provide a drive control circuit configured so that the output of a drive circuit of a liquid crystal cell can always maintain a predetermined level.

[Means for Solving the Problems] A drive control circuit of a liquid crystal display device according to the present invention includes an insertion unit for inserting information representing a reference level value during a blanking period of an input image signal, and an output of the insertion unit. An analog shift register connected in a row and connected in cascade with a plurality of drive circuits for driving a liquid crystal cell; holding means for extracting and holding the reference level value included in an image signal; and the drive circuit Calculating means for calculating a difference between the level value of the image signal shifted by the blanking period and the reference level value held by the holding means, and an input to the drive circuit in response to an output of the calculating means. Level control means for variably controlling the level.

[Operation] According to the present invention, based on the reference level information inserted during the blanking period of the image signal, the predetermined level of the liquid crystal cell drive circuit is monitored, and the feedback control is performed so that the predetermined level maintains the reference level. It can be carried out.

Specifically, the reference signal insertion unit inserts a predetermined reference level at a stage preceding the area covered by the drive circuit including a part of the horizontal blanking period of the video signal.
Then, the foremost stage (terminal to which the temporally earliest data is output) of the shift register in each drive circuit is detected by a separately provided timing generation circuit. The drive circuit of the liquid crystal cell has a hold circuit in the input stage to hold the reference level, and uses the voltage level of the difference from the reference level output from the output stage (the foremost stage or the cascade connection element) to input the signal. The DC component of the signal is corrected by the DC shift circuit (clamp circuit) of the stage.

It should be noted that the driving circuit of the liquid crystal cell does not have to be a DC or parallel connected configuration.

EXAMPLES Hereinafter, the present invention will be described in detail based on examples.

FIG. 1 is a block diagram showing one embodiment of the present invention.
This figure is a circuit for processing the R signal among the R, G, and B signals, and the same circuit is required for the other G and B signals.

In FIG. 1, reference numeral 2 denotes an input terminal for an image signal. In this embodiment, the configuration is such that the R signal is input.
Other luminance signals or color difference signals may be used. When displaying HDTV signals, the MU
The SE signal is decoded into an RGB signal and supplied to the input terminal 2.

Reference numeral 4 denotes an A / D converter, and reference numeral 6 denotes a digital signal processing (DSP) unit. A circuit 8 generates a reference level to be inserted during a blanking period of an image signal. Reference numeral 10 denotes an insertion unit for inserting reference level information in the blanking period (point A shown on the left side of FIG. 1). 12 is
It is a D / A converter.

Here, the A / D converter 4 at the input stage is a function that is usually required for digital processing when a signal is corrected by a filter or the like before being applied to a display device for the purpose of improving image quality or the like. This is unnecessary in a system that does not require this correction signal processing. In addition, these correction signal processing units
This is called a (DIGITAL SIGNAL PROCESSING) section 6, and this block is used to perform parallel arrangement processing due to the limitation of the operation speed of the drive circuit. Furthermore, in this figure, the reference signal insertion section
Although 10 is configured to be performed by digital processing, this processing can be realized by essentially any type of digital or analog processing. As a matter of course, the D / A converter 12 is unnecessary if the DSP unit 6 is omitted. In addition, the D / A converter 12 is omitted when the input of the drive circuit unit 22 described later is digital.

A control unit for driving each liquid crystal cell is connected to a stage subsequent to the preprocessing unit described above. Here, 14 is a buffer circuit, 16 is a hold circuit that samples and holds the reference level (the level at point A shown on the left side of FIG. 1) inserted during the blanking period of the image signal, 18 is a differential amplifier,
Reference numeral 20 denotes a clamp circuit FET for holding the input-side DC level of the liquid crystal cell drive circuit 20-1 at a predetermined value (e ₁ -e ₂ ).
Reference numerals 22-1 to 22-N denote liquid crystal cell driving circuits which output an analog voltage (a transmittance control voltage) for driving the liquid crystal cell and also function as an analog shift register.

A hold circuit is provided at the non-inverting input terminal of the differential amplifier described above.
The reference level e ₁ (the level inserted at point A) held by 16 and the other inverting input terminal of the delay signal sent from the shift output terminal of the drive circuit 20-1 are used for the blanking. level e ₂ corresponding to the period is inputted.

Therefore, (e ₁ -e ₂ ) is output to the output terminal of the differential amplifier 18. Since the output (e ₁ -e ₂ ) sets the source potential of the FET ₂₀ to (e ₁ -e ₂ ), the output DC level of the drive circuit 22-1 can be controlled to be maintained at a constant value.

Since Specifically, if the output side DC level of the drive circuit 22-1 due to aging or the like has been decreased to decrease the e _2,
The output level (e ₁ -e ₂ ) of the differential amplifier 18 increases, and as a result, the input DC level of the drive circuit 22-1 is boosted, and finally the output DC level of the drive circuit 22-1 is increased. It will be kept at a predetermined value.

Reference numeral 30 denotes a timing signal generator, which includes a timing signal T _A for triggering the reference level insertion unit 10, a timing signal T _B for triggering the hold circuit 16, and a FET 20.
And outputs a timing signal for causing the clamp operation to be performed.

Thus, a certain reference level is inserted in the horizontal blanking period, and the video signal including the reference level is supplied to the drive circuit 22.
Enter -1. Then, it outputs a timing signal T _B corresponding to the reference level from the timing signal generator 30, at the same time synchronization, this voltage level driving circuit 22
The data is held by the hold circuit 16 during a period from −1 to the shift output.

Next, the held level e ₁ and the output level of the drive circuit
e ₁ is input to the differential amplifier 18 and the difference component (e ₁ -e ₂ ) is output. By using this difference component voltage level as, for example, the source potential of the field effect transistor, the DC potential of the drive circuit input section is controlled, and the offset component due to the characteristic fluctuation of the drive circuit is removed.

The driving circuit 22-N at the subsequent stage operates similarly. The drive circuit may be of a cascade connection type or of a parallel connection type.

[Effects of the Invention] As described above, according to the present invention, since the reference level information is inserted during the blanking period, the output performance of the liquid crystal cell drive circuit, particularly the DC The change in level can be automatically corrected.

In addition, not only can image quality be ensured by compensating for changes in temperature and aging, but also variations in drive circuits (generally integrated circuits) can be automatically corrected.
No adjustment at the time of product shipment is required.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 2 ... image signal input terminal, 4 ... A / D converter, 6
…… Digital signal processing section, 8 …… Reference level generator, 10 …… Reference level insertion section, 12 …… D / A converter, 14 …… Buffer circuit, 16 …… Hold circuit,
18: Differential amplifier, 20: FET, 22-1 to 22-N: Liquid crystal cell drive circuit.

Continuation of the front page (72) Inventor Takashi Nirazawa 4-15-3 Nishi-Shinjuku, Shinjuku-ku, Tokyo Sanseido Shinjuku Building 4th Floor Advanced Imaging Technology Laboratory Co., Ltd. (56) References JP-A-1-281497 (JP, A) JP-A-1-177112 (JP, A) JP-A-1-144299 (JP, A) JP-A-64-29899 (JP, A)

Claims (1)

(57) [Claims] 1. An insertion means for inserting information representing a reference level value during a blanking period of an input image signal, and a plurality of driving circuits connected to an output side of the insertion means for driving a liquid crystal cell. An analog shift register connected in cascade only, holding means for extracting and holding the reference level value included in the image signal, and a level value in a blanking period of the image signal shifted by the driving circuit; And a level control means for variably controlling an input level of the driving circuit in response to an output of the calculation means. Drive control circuit.