JPH03276235A - Microcomputer debugging device - Google Patents

Abstract

PURPOSE:To monitor the state of the data at a certain instant without breaking a subject microprocessor by using plural monitoring RAMs in order to hold the data in an optional instant. CONSTITUTION:When a microprocessor to be measured has an access to a set address E, a RAM 8 rewrites the data in an address different from an old address. Thus the higher ran addresses M of the RAM 8 are increased for each input of a trigger signal T, and the data writing area is updated. A built-in microprocessor B stops a write control signal K of the RAM 8 via a user operation or displays the data on an optional address of the RAM 8 on a CRT 10 by presetting a preset counter 12. Thus the instant data state of a trigger signal can be displayed on the CRT regardless of the order of the trigger signal.

Description

[Detailed description of the invention] It is related to.

[Summary of the Invention] Conventionally, as a debugging device for a microcomputer, there is a device that monitors RAM data in real time, and it is possible to check the contents of a plurality of words of RAM. but,
Since the monitor screen is continuously updated as long as the microcomputer is operating, it is often difficult to check the data at a certain moment.

This time, the RAM data can be monitored while the microcomputer is operating, and the contents of the RAM data at a certain moment can also be held.

[Conventional technology]

As a conventional technique, 2, for example, Japanese Patent Application Laid-open No. 55-43660 "
There is a microcomputer debugging device such as the one filed under "Microcomputer Debugging Device." It debugs the contents of the working memory of the microcomputer being debugged, and in real time.

This allows constant monitoring without sacrificing the progress speed of the program.

The configuration consists of a memory in which data is written at the timing of the microcomputer using the address bus, data bus, and control bus of the microcomputer to be debugged, and a memory address that is switched to continuous readout except during writing, and a constant read address. The memory is sequentially read out by a circuit that outputs the data, and the data is monitored (CR
It consists of a circuit shown in T).

[Problem to be solved by the invention]

Although the above-mentioned conventional technology has the effect of monitoring data in real time, it has the disadvantage that the state of data at a certain moment cannot be checked. The present invention aims to overcome these drawbacks.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a RAM for monitoring.
By using a plurality of , it is possible to hold data at any given moment (at the time of trigger).

FIG. 3 shows, as an example, a case where one RAM address is divided. Parts 0 to 255 of the RAM 8 in FIG. 3 are first rewritten at the timing of the target microcomputer and the data is monitored.

The next moment (assuming this is the point when the trigger signal arrives)
The write area of RAM8 is automatically set to 256 to 511.
If you do so, the state of the data at that moment remains in O~255. Moreover, by monitoring the areas 256 to 511, data can be monitored in real time. Second
The figure shows this situation over time. The instantaneous data of the first trigger signal remains in RAM8 O~255, and the instantaneous data of the second trigger signal remains in 256~255 of RAM8.
He will remain at 511. If there is no trigger signal, the contents of the unit area being written will be written sequentially.
You can read it and monitor it in real time.

[Effect]

As a result, the instantaneous data of the first trigger signal is held in 0 to 255 of the RAM 8, and the instantaneous data of the second trigger signal is held in 256 to 511. Thereafter, in the same manner, the state of data at each instant of the trigger signal is held a plurality of times.

A debugger can check the state of data at every instant by monitoring which part of the RAM.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In the figure, 1 is a buffer circuit that receives a signal A from a data bus of a microprocessor under test (not shown);
3 is an address setting circuit, 3 is a comparison circuit, 6 is a CRT controller, 7 is a selector for selecting the signal B of the address bus of the microprocessor under test (not shown) or the display address H, 8 is the RAM shown in FIG. 3, 9 10 is a CRT, 12 is a preset counter, and 13 is a microprocessor. The operation will be explained below.

The comparison circuit 3 compares the address setting circuit 2 and the upper address of the address bus B of the microprocessor under test,
When they match, a match signal G is output.

Here, the address information of the address setting circuit 2 can be set arbitrarily by the user. When the match signal G is output, the selector 7 selects the address bus B, and the address bus B signal comes to the lower address bus of the RAM 8. The buffer 1 is also enabled by the coincidence signal G, and the data bus A of the microprocessor under test is placed on the data line R of the RAM 8. Data is written into the RAM 8 by a read signal RDC or a write signal WRD from a microprocessor under test (not shown). At this time, the preset counter 12 indicates a certain value and specifies the upper address M of the RAM 8.

As described above, each time the microprocessor under test accesses the setting address E, data is written to the accessed address in the RAM 8. This operation can be thought of as accessing portions 0 to 255 of the RAM 8 in FIG. The microprocessor under test is set to address E.
When the RAM 8 is not being accessed, the selector 7 selects the display address H of the CRT controller 6.
The lower address L of is read out under the control of the CRT controller 6. The read data R is converted by the display control circuit 9 and displayed on the CRTIO.6 Next, the moment the trigger signal T is input, the preset counter 12 is incremented, and the upper address bus M of the RAM 8 is incremented by 1. Ru. this is.

This is because the address has changed to the part 256 to 511 in FIG. As a result, the data at the moment when the trigger signal T is input is held in O to 255 in FIG. 3. Let's return the explanation to Figure 1.

When the microprocessor under test accesses the set address E, the RAM 8 rewrites data to an address different from the previously rewritten address. As described above, each time the trigger signal T is input, the upper address M of the RAM 8 is incremented, and the data write area is updated. The built-in microprocessor B uses the RA by user operation.
By stopping the writing of M8 with a control signal and by presetting the preset counter 12, control is performed to display data at an arbitrary address in RAM8 on CRTIO.This allows the data state at the moment of the trigger signal can also be displayed on a CRT.

〔Effect of the invention〕

According to the present invention, it is possible to monitor the state of data at a certain moment without causing a break in the target microprocessor, which was previously impossible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention;
FIG. 2 is a conceptual diagram regarding the operation, trigger signal, and display of the microprocessor to be debugged according to the present invention. FIG. 3 shows a method of the present invention in which the address of RAM 8 is divided.
It is an example conceptual diagram. 1: buffer circuit, 2 near address circuit, 3: comparison circuit,
4: AND circuit, 5: NAND circuit, 6: CRT controller, 7: Selector, 8: RAM9: Display control circuit, lo: cRT, 11: NAND circuit, 12 nib reset counter, 13: Microprocessor, 14, 15
: Switch circuit, A: Microprocessor data bus under test, B: Microprocessor address bus under test, C
: Microprocessor under test read signal, D = Microprocessor under test write signal T: Trigger signal.

Claims (1)

[Claims] 1. A circuit that compares the address signal of the microcomputer to be debugged with an arbitrarily set address, a memory circuit having multiple areas that writes data at the address of the microcomputer to be measured when the addresses match, and A microcomputer debugging device having a circuit for specifying an arbitrary area of a memory, and means for sequentially changing the specified value of the circuit for specifying an arbitrary area of the memory using an external signal, and displaying data of the memory.