JP3167245B2 - Programmable controller operating state monitoring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller operation state monitoring device for monitoring the operation state of a programmable controller by displaying the operation state of the program in the order of execution of the program.

[0002]

2. Description of the Related Art In a work site, a factory, or the like, a logical value that can be represented by two values such as numerical information such as the number of products passing through an outlet of a belt conveyor, pressure, temperature, and whether or not a certain switch is turned on. Sequence control is performed in accordance with information and the like. This sequence control is accompanied by a change or modification of the specification. For this reason, a programmable controller (hereinafter, referred to as a PC) capable of executing sequence control according to a program input by a user and freely changing or creating the program is widely used for sequence control.

As a PC programming language, an illustration expression program is widely used. The illustration representation program is a program created by connecting graphic symbols such as relay symbols and logic symbols on a screen such as a display panel. The creation of a PC program is generally performed using a programming device (support tool).

FIG. 18 is a circuit block diagram showing a schematic configuration of a conventional programmable controller 100 and a support tool 110. Referring to FIG. 18, the creation of a program and the loading of a program from the support tool 110 to the PC 100 will be described. .

The creation of a program in the support tool 110 is generally performed in an interactive manner. That is, when the user performs a key operation on the keyboard 111, a graphic symbol is displayed on the display unit 112 in accordance with the key operation, and the user connects them with a line while looking at the graphic symbol displayed on the display unit 112. By doing so, a program is created. FIG. 19 is an explanatory diagram showing an example of a program based on the ladder diagram created in this way.

The PC 100 has a support tool I / F unit 10
2 is connected to the support tool 110. The ladder diagram (program) drawn on the display unit 112 of the support tool 110 is converted into an object code and transmitted to the PC 100 when a predetermined key is operated. And stored in the memory 103 here. As a result, the program loading is completed, and the CPU (CENTRAL PROCESSOR UNIT) 101 reads the program stored in the memory 103 for each address and executes the instruction stored at that address.

Here, the PC 100 generally has a data memory (not shown) for storing the operation results of the program,
An input / output memory (not shown) is provided for storing output data (usually an on / off instruction) to an external device connected to the PC 100 or input data therefrom (usually data indicating an on / off state). ing. Most of the execution of instructions is reading input data from an external device or outputting data to an external device, and these correspond to access to an input / output memory.

The support tool 110 has, in addition to the function for creating a program as described above, a monitor function for monitoring the operating state of the PC 100 such as the progress of sequence control and the internal logical state. Support tool with monitoring function (PC operation state monitoring device) 11
The monitoring of the PC 100 by 0 is generally performed as follows.

First, the PC operation state monitoring device 110 reads out a program stored as object code in the memory 103, disassembles it, converts it into a ladder diagram (specification description format) on the display unit 112, and converts it into a ladder diagram. indicate. Next, the input / output memory or the data is determined by the names of the graphic symbols of the contacts, coils, etc. (these correspond to input and output devices, respectively) used in the ladder diagram (which correspond to the operands of the program). Obtain an address (execution address) for reading data in the memory,
The data stored at the execution address is read. Further, the read data is displayed so as to be superimposed on the corresponding graphic symbol in the ladder diagram displayed on the display unit 112.

[0010]

However, FIG.
Has the following problems.

As described above, the conventional PC operating state monitoring apparatus 110 obtains an execution address based on the names of the contacts and coils referred to by the PC 100, and operates the input and output devices corresponding to the contacts and coils. Is monitored by reading data from the input / output memory, etc., indicating that the memory used as a temporary register
The content (this is referred to as a local memory) cannot be obtained (data of the operation result of the instruction), and the operating state of the PC 100 cannot be accurately monitored.

The above problem will be described with reference to FIG. FIG. 19 shows an example of a monitor display at the same time as an example of a program, and shows an operation state (ON or OFF) depending on the luminance of a graphic symbol. As shown in FIG. 19, the register R0 in the first row has the contacts A and B
Is substituted, and is displayed as a contact on the fourth line. Register R used in this manner
The data value (logical value) of 0 is stored in the local memory.

The local memory also stores numerical data such as a timer value and a count value. These are different from auxiliary ones such as the register R0.
Although access is possible because a dedicated area is allocated, the data value of the register R0 cannot be read because the area where the data is stored is allocated each time. Therefore, as shown in FIG. 19, although the contacts A and B are on (data value is 1), the register R0 is not on but off (data value is 0).
It has become. Although not specifically shown in FIG. 19, the same applies to the register R1.

If the PC operation state monitoring device 110 can read such data values of the registers R0 and R1 from the local memory, the above-mentioned problem can be avoided.
To do this, the address (area) of the local memory and
Since the correspondence with the type of data stored therein (corresponding to the register R0 or the like) must be notified to the PC operation state monitoring device 110, the processing of the CPU 101 becomes heavy, and the processing speed of the CPU 101 is significantly reduced. Will be. Further, data cannot be written to the local memory until the PC operation state monitoring device 110 reads data from the local memory.

The operation states of the input and output devices corresponding to the names of the contacts and coils used in the ladder diagram are determined by the CPU.
Since the calculation result of the CPU 101 is not obtained, the calculation result of the CPU 101 cannot be taken out in the order of execution, so that there is a problem that an accurate monitor display cannot be performed.

The PC 100 generally employs a serial processing method for sequentially executing a program stored in the memory 103 for each address. For this reason, if the operation state is not monitored in the execution order of the program, usually, an output device whose operation state is switched by executing the program,
It is impossible to monitor and display an accurate correspondence with an input device whose operation state is switched by a user or the like.

Further, the PC operation state monitoring device 110
Since the execution result is read out asynchronously with the execution of the instruction by the PU 101, the monitor display on the display unit 112 has no synchronization of the execution result. For example, the state at the time when the switch of the predetermined input device is turned on or off is displayed. There is also a problem that accurate monitor display cannot be performed.

The above-mentioned problems are caused by the display unit 112.
Also, when the monitor display is fixed and the operation state at that time is checked, the same occurs for the same reason. again,
The above problem will be described with reference to FIG. The contact D in the second row is turned on when the logical sum of the contact C and the register R1 becomes 1. As shown in FIG. 18, since the contact C is on, the contact D must be on at this time, but the contact D is off.

In the fourth and fifth rows, both the set coil and the reset coil of the coil E are turned on. Since these two are not turned on at the same time, it is apparent that an incorrect monitor display is clearly performed.

Such a problem often occurs particularly in a logic or the like in which the switching of the operating state at each contact changes quickly, and the problem becomes more serious. Conventionally, as an operation state of a program which can be displayed on a monitor in the order of execution of the program, see, for example,
No. 7718 discloses an “operating state monitoring method for a programmable controller”. However, P
The C operation state monitoring device monitors the operation state by sequentially storing the instruction code, input and output device numbers, and their operation state data output on the common bus in the trace memory, and thus monitors the operation state of the common bus. The problem is that the hardware becomes heavy because all the traces are required, and if the operation result of the instruction is stored in the local memory without passing through the common bus, the data stored in the local memory cannot be obtained. There is a problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has a simple hardware to monitor and display a PC operation state including an operation result stored in a local memory in the order of execution of instructions. It is an object to provide a monitoring device.

[0022]

The means of the present invention will be described with reference to the principle diagram shown in FIG. The PC operation state monitoring device 9 of the present invention is premised on monitoring the operation state of the programmable controller 3 including the execution unit 2 that reads out and executes the instructions of the program stored in the program memory 1 for each address.

The means of the PC operating state monitoring device 9 includes a condition designating means 4 for designating a monitoring condition when the execution means 2 executes the instruction of the program stored in the program memory 1 and a program memory for executing the program instruction. A comparing means for comparing information obtained by reading a program instruction from the program instruction with a monitoring condition designated by the condition designating means; a trace memory storing a result of execution of the program instruction by the execution means; Writing means 6 for writing the execution result of execution means 2 to trace memory 7 based on the comparison result of
A display unit 8 for reading and displaying the execution result written in the trace memory 7;

In the above-described configuration, the condition specifying means 4 includes an address range storing means 11 for storing an address range of the program memory 1 as a monitoring condition as shown in FIG. Storage means 1
It is desirable to compare the address range stored in the instruction unit 1 with the address at which the execution unit 2 has read the instruction from the program memory 1.

The condition specifying means 4 includes a task number storing means 12 for storing a task number of the program stored in the program memory 1 as a monitoring condition, and the comparing means 5 is stored in the task number storing means 12. It is desirable to compare the task number with the task number of the program being executed by the execution means 2.

The condition specifying means 4 includes a caller address storage means 13 for storing, as a monitoring condition, a caller address at which an instruction for calling a subroutine in the program memory 1 is stored. The comparing means 5 stores the caller address. Caller address stored in means 13 and execution means 2
It is desirable to compare with the caller address of the subroutine that is executing.

The writing means 6 in the above-described configuration
Is the program memory 1 from which the execution means 2 has read the instruction.
It is desirable to monitor the order of the addresses, and stop the writing to the trace memory 7 when the order of the addresses becomes inconsistent.

The writing means 6 monitors the order of the addresses in the program memory 7 from which the execution means 2 has read out the instruction, and when a loop occurs in the order of the addresses, writes the data to the trace memory 7 in the loop. It is desirable to make a loop corresponding to

[0029]

The PC operating state monitoring device 9 of the present invention specifies the monitoring area of the program memory 1 by the area specifying means 4,
The comparing means 5 compares the predetermined information read by the execution means 2 from the program memory 1 with the monitoring area designated by the area designating means 4, and the writing means 6 executes based on the comparison result of the comparing means 5. The execution (operation) result of the means 2 is written in the trace memory 7, and the execution result written in the trace memory 7 is displayed on the monitor 8 by the monitor. Thus, the execution results of the instructions by the execution means 2, including the execution results stored in the local memory, are displayed on the monitor in the order of execution of the instructions.

The condition specifying means 4 includes an address range storing means 11 for storing monitoring conditions, a task number storing means 12, and
And task number stored in the caller address storage means 13
Means 12, and while the least <br/> without the Bei also Eteori, conditional execution means 2 executes the appropriate instructions to the stored monitored condition specifying means 4 is provided with storage means the calling address storing unit 13 In this case, the execution result is stored in the trace memory 7. When the condition specifying unit 4 includes all the three storage units described above, the user can monitor and display the execution result of the execution unit 2 for only a desired part.

The writing means 6 monitors the order of the addresses in the program memory 7 from which the execution means 2 has read out the instruction, and stores any information in the trace memory 7 if the order of the addresses is inconsistent. When the storage of the execution result in the trace memory 7 is stopped and a loop occurs in the order of the addresses, the fact is stored in the trace memory 7 and the writing to the trace memory 7 is looped in accordance with the loop. Thereby, the program memory 1
The sequence of instructions of the program stored in the trace memory 7 matches the order of the execution results of the instructions by the execution means 2 stored in the trace memory 7, and the monitor display is performed in the execution order of the instructions regardless of the presence or absence of a program branch or loop. Can be done accurately.

[0032]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 3 shows a PC according to the present embodiment.
FIG. 2 is a circuit block diagram illustrating a schematic configuration of an operation state monitoring device. As shown in FIG. 3, the PC operation state monitoring apparatus according to the present embodiment is roughly divided into a PC 21 and a support tool 22 connected to the PC 21.

Referring to FIG. 3, first, the operation of a program creation and program loading will be described as an example. When the user operates a key provided on the keyboard 23, the control unit 24 determines the type of the operated key, writes the determined type of the key into the memory 25, and sends the determined key type to the display control unit 26. And outputs a predetermined control signal.

When the control signal is input from the control unit 24, the display control unit 26 displays the contents (graphic symbols and the like) written in the memory 25 on the display unit (CRT) 27. Thus, when a key operation is performed, a corresponding graphic symbol is displayed on the display unit 27, and the user creates a program in an interactive manner.

Storing the program displayed on the display unit 27 in the program memory 28 (loading the program)
Is performed by a predetermined key operation of the keyboard 23.
That is, when this key is operated, the control unit 24
5 is converted into an object code and output to the PC 21. One PC 21
Inputs the object code output from the support tool 22 via the support tool I / F unit 29 and stores it in the program memory 28. Thus, the program loading is completed.

Next, the operation for monitoring the operating state of the PC 21 will be described. The monitoring of the PC 21 according to the present embodiment is performed by designating three monitoring conditions of the address range of the program memory 28, the task number of the program, and the address (call source address) at which the instruction that called the subroutine is stored. The input for designating these monitoring conditions is performed by operating the keyboard 23, and the monitoring conditions input by this operation are output to the PC 21.

From the other PC 21, the program stored in the program memory 28 is output to the support tool 22. When the support tool 22 inputs the program, the control unit 24 disassembles and stores the disassembly in the memory 25, and the display control unit 26 displays the program stored in the memory 25 on the display unit 27. The step number (corresponding to the address of the program memory 28) and the task number are displayed together with the program displayed on the display unit 27. The various monitoring conditions described above are input by the user using the keyboard 23 while viewing them.

In this embodiment, the monitoring conditions input by the support tool 22 are as follows: the address range is specified by the upper limit value and the lower limit value of the address; the task number is specified by the task number assigned to each program; The caller address is specified by the address of the program memory 28 that called the subroutine. The upper limit value and the lower limit value of the address range are stored in the address range instruction register 30, the task number is stored in the task setting register 31, and the caller address is stored in the caller address setting register 32, respectively. Here, the address range instruction register 30 includes an upper limit value register 30a and a lower limit value register 30b. The upper limit value is stored in the upper limit value register 30a, and the lower limit value is stored in the lower limit value register 30b. .

The instruction execution unit 33 is provided in the program memory 28
And a CPU for reading and executing the instructions stored in the program for each address. Instruction reading from the program memory 28 is performed by outputting a count value of a program counter (not shown) to the program memory 28, and the read instruction is temporarily stored in the instruction register 34.

The count value of the program counter is also output to the comparator 35. The comparator 35 is an upper limit comparator 3
5a and a lower limit comparator 35b. The upper limit value comparator 35a receives the upper limit value from the upper limit value register 30a and the count value of the program counter from the instruction execution unit 33, compares them, and outputs 1 when the count value is smaller than the upper limit value. . One lower limit comparator 35b receives the lower limit from the lower limit instruction register 30b and the count value of the program counter from the instruction execution unit 33 and compares them. If the count value is larger than the lower limit, 1 is set. Output. Upper limit comparator 35a and lower limit 3
The comparison result of 5b is ANDed by the AND gate 36, and the AND is output from the AND gate 36 to the AND gate 37.

In this embodiment, one task number is 1
When the program is displayed on the display unit 27, the task number is displayed. As a result, the user can easily know the task number for performing the desired monitoring.

The task number specified by the user is stored in the task setting register 31, and the task number of the program that the instruction execution unit 33 is to execute now or from now on is stored in the task execution register 38 by the instruction execution unit 33.

The task number comparator 39 compares the task number stored in the task execution register 38 with the task number stored in the task setting register 31, and outputs the comparison result to the differentiating circuit 40 and the AND gate 37. I do. The task number comparator 39 outputs 1 when the task numbers stored in the task execution register 38 and the task setting register 31 match.

The differentiating circuit 40 outputs a pulse (1) only when the value output from the task number comparator 39 falls from 1 to 0, and the output is sent to a flip-flop (F / F) 41. Is entered. The output of the F / F 41 is set by inputting a pulse indicating a trace start instruction from the support tool 22 via the support tool I / F unit 29, and the output is reset by inputting a pulse from the differentiating circuit 40. Is what is done. This F /
The output of F41 is input to the support tool 22 via the AND gate 37 and the support tool I / F unit 29.

The call source address stored in the call source address setting register 32 is compared with the count value of the program counter output from the instruction execution unit 33 by the address comparator 42. The address comparator 42 outputs 1 to the F / F 43 when the two values match.

The F / F 43 outputs 1 from the address comparator 42.
Is output, the output is set, and the differentiation circuit 4
5 is reset by outputting a pulse. The differentiating circuit 45 is the same as the differentiating circuit 40, and outputs 1 only when the output input from the AND gate 36 falls from 1 to 0. The output of the F / F 43 is output to the AND gate 37.

The AND gate 37 is connected to the AND gate 36,
The logical product of the F / Fs 41 and 43 and the task number comparator 39 is obtained, and the result is output to the instruction register 34. The instruction register 34 includes an instruction part 34a for storing the instruction output from the program memory 28 and a code part 34b for storing the output value of the AND gate 37. All the contents stored in the instruction register 34 are stored in the instruction execution part. 33.

When these are input from the instruction register 34, the instruction execution unit 33 determines whether the data stored in the code unit 34b is 1 and executes the instruction stored in the instruction unit 34a. That is, when it is determined that 1 is stored in the code section 34b, the execution result of the instruction stored in the instruction section 34a at this time is output to the CPU bus, and the execution result is written in the trace memory 44.

The result of the execution of the instruction by the instruction execution unit 33 is output to a data memory and an input / output memory (not shown), and the external device connected to the PC 21 operates according to the data stored in the input / output memory. . This allows P
C21 performs sequence control.

While 1 is stored in the code section 34b as described above, the instruction execution section 33 performs the processing described later, so that the operation results of the instructions executed by the instruction execution section 33 are sequentially written. Here, as will be described in detail later, while 1 is stored in the code section 34b, the designated monitoring condition is satisfied. Further, since the operation result of the instruction execution unit 33 is written in the trace memory 44, the operation result stored in the local memory (not shown) is also stored in the trace memory 44.

Although the present embodiment includes the trace memory 44 for tracing the instruction execution unit 33, the operation result of the instruction execution unit 33 may be stored in the data memory instead of the trace memory 44. good. Further, the program memory 28 is used as a data memory and the trace memory 44.
May be used.

The above is the schematic operation in this embodiment.
Next, the operation will be described in more detail with reference to FIGS. FIG. 4 is a flowchart illustrating the essential processing operation of the instruction execution unit 33 according to the present embodiment. Here, it is assumed that only the program has been read from the address within the address range set in the address range setting register 30, and the processing operation will be described on the assumption that other monitoring conditions such as a task number are satisfied.

As shown in FIG. 4, when the instruction execution unit 33 executes the instruction stored in the instruction unit 34a (S1), next, whether the value stored in the code unit 34b is 1 or not, that is, when the trace request is It is determined whether there is (S2). If it is determined that there is no trace request, the processing for this instruction is completed here. Conversely, if it is determined that there is a trace request, the execution result (operation result) of the program is stored in the trace memory 44 (S3). Is completed. The processing is similarly executed for other instructions in this manner.

FIG. 5 is an explanatory diagram showing an example of the contents stored in the trace memory 44 by the above-described processing. Here, FIG. 5 shows a case where the example of the program shown in FIG. 19 is executed.

As shown in FIG. 5, the trace memory 44 sequentially stores the operation results of instructions as a set of a trace control unit and trace data. The trace control unit, which will be described later in detail, is for indicating when a program loop, branch, or the like has occurred. Therefore, nothing is written in the trace control unit at this time, and only the trace data that is the operation result of the instruction is written.

As described above, since the operation results of the instructions are sequentially stored in the trace memory 44 in the order of execution, the trace data stored in the trace memory 44 is read out.
By sequentially displaying the read trace data on the corresponding graphic symbol and displaying it, the result of the operation of the instruction of the instruction execution unit 33 is dynamically including the data stored in the local memory, that is, the data synchronization is satisfied. Then, the monitor display can be performed in the order in which the instructions are executed.

The instruction execution unit 33 is provided with the trace memory 4
4 because trace data is written in
Compared with the PC operation state monitoring device to which JP-A-7718 is applied, the execution result stored in the local memory can be reliably traced and only the CPU bus needs to be traced, so that the hardware configuration can be simplified. There is an effect that can be.

When the monitor display is performed, the control unit 24 reads the trace data stored in the trace memory 44, and stores the trace data in the memory 25 in which the graphic symbol corresponding to the read trace data is stored.
For example, display luminance data corresponding to the value of the trace data is stored. Thereby, the user can grasp the operation state of the graphic symbol based on the display luminance of the graphic symbol.

FIG. 6 is an explanatory diagram showing a tracing method of the first subroutine according to this embodiment. In FIG.
Two programs, a scan program (P-level program A) and an interrupt program B, call a subroutine S (to be traced).

In the case shown in FIG. 6, it is not possible to determine which program is calling the program only by specifying the address range of the subroutine S. Therefore, in the present embodiment, a task number is assigned to each program, and the case where tracing is performed by specifying the task number is specified.

As described above, the task setting register 31
Stores the task number designated by the user, and the task execution register 38 stores the task number to be executed now or from now on. Since the task number comparator 39 outputs 1 only while the task numbers stored in these registers match, the F / F 41 is not reset during this time and outputs 1. Therefore, when other specified conditions of the address range and the caller address are satisfied, tracing can be performed only while the task number comparator 39 is outputting 1.

In this embodiment, the task setting register 3
Although only one is provided, if it is desired to specify several programs that call the subroutine to be traced at the same time, a plurality of task setting registers 31 are provided, and the task number is stored in any of the task numbers stored in these task setting registers 31. The tracing may be performed when the task numbers stored in the execution register 38 match, or the task numbers may be sequentially stored in the task setting register 31 by the control unit 24. Further, in this embodiment, when the task number is not stored in the task setting register, the task number comparator 39 always outputs 1.
Therefore, tracing can be performed only by specifying the monitoring conditions of the address range and the caller address.

FIG. 7 is an explanatory diagram showing a tracing method of the second subroutine according to this embodiment. As shown, the subroutine S is called twice by the level program A, that is, at the addresses indicated by (a) and (b) within the same task number.

In the case of tracing the subroutine S in the case as shown in FIG. 7, simply by setting the address range of the subroutine S and the task number of the level program A, the trace is called from either (a) or (b). I do not know if it was. Therefore, by managing the caller of the subroutine, only the subroutine called at the specific location in the program of the set task number is traced.

The caller address setting register 32 in FIG. 3 stores a caller address of a subroutine in the program memory 28. Here, it is assumed that the task number stored in the task setting register 31 matches the task number stored in the task execution register 38, and the operation will be described.

The call source address stored in the call source address setting register 32 is compared with the count value of the program counter output from the instruction execution unit 33 by the address comparator 42. When the two values match, the address comparator 42 outputs 1 to the F / F 43. F / F
43 is set by inputting 1 from the address comparator 42, and its output is input to the AND gate 37.

When the address comparator 42 outputs 1, it means that the instruction execution unit 33 has executed the instruction stored at the call source address of the subroutine S. Will be executed.

While the instruction execution unit 33 is executing the processing of the subroutine S, the count value of the program counter is output to the address comparator 42, but the F / F 43 is still set. Therefore, while the instruction execution unit 33 is executing the processing of the subroutine S, the AND gate 3
The output of 7 is equal to the output of AND gate 36. That is, while the instruction in the trace range in the subroutine S is being executed, the output of the AND gate 36 is 1 according to the comparison result of the comparator 35. As a result, 1 is written to the code section 34b of the instruction register 34 while the instruction in the trace range in the subroutine S is being executed.
Is stored as trace data.

As described above, in this embodiment, by specifying the caller address, the subroutine processing can be traced according to the place where the subroutine is called.

When the processing of the trace range in the subroutine S is completed, the output of the AND gate 36 falls from 1 to 0. As a result, the next 0 is written into the code section 34b, and the F / F 43 is reset by outputting 1 from the differentiating circuit 45. When the processing of the subroutine S is completed, the next value of the caller address is set in the program counter, and the instruction stored at the address after this is executed.

In this embodiment, when 0 is stored in the caller address setting register 32, the address comparator 42 outputs 1. Therefore, the user only needs to call the source address setting register 3 when necessary.
2 stores the caller address.

Next, a tracing method when a program such as IF, THEN, and ELSE involves a branch will be described. In the program stored in the program memory 28, one instruction in the program (instruction group) is stored at one address. For this reason, the instruction sequence and the execution result (trace data) of the instruction are in a one-to-one correspondence. I can't figure it out. Therefore, in the present embodiment, the instruction execution unit 33 stores the fetch prohibition flag (code) indicating whether or not a branch (mismatch) has occurred in the trace memory 44 together with the trace data, and stops storing the trace data thereafter. It is something to do. This tracing method according to the present embodiment will be described with reference to FIGS.

FIG. 8 is an explanatory diagram showing an example of a program including a branch, and FIG. 9 is a flowchart showing this program. First, this program will be described with reference to FIGS.

In the example of the program shown in FIG. 8, when the value of the contact A is determined to be 1 as shown in FIG. 9 (S11), the logical product of the contact C and the contact D, which is a THEN process, is set to the value of the coil E (FIG. 9). S12) is executed. On the other hand, when it is determined that the value of the contact A is not 1 (S11), a process of setting the logical product of the contact F and the contact G to the value of the coil E, which is an ELSE process, is executed (S13). Things.

FIG. 10 is a simplified flowchart showing the trace processing in the THEN processing. In this process, first, it is determined whether or not to execute a THEN process (instruction) (S21).
The program counter is skipped in order to execute the THEN process (S22). If it is determined in step S21 that the THEN process is not to be performed, that is, if there is a skip (branch), the program counter is skipped to the count value indicating the ELSE process (S2).
3). When the skip of the program counter to the ELSE process is completed, it is determined whether or not there is a trace request next, that is, whether or not the value of the code part 34b is 1 (S24). (Flag) is set (S25), and if it is determined that there is no trace request, the capture prohibition code is not set.

When the capture prohibition code is set, the instruction execution unit 33 writes the capture prohibition flag in the trace control unit of the trace memory 44 and stops the subsequent writing of trace data to the trace memory 44.

FIG. 11 is a simplified flowchart showing the trace processing in the ELSE processing. In this process, first, it is determined whether or not to execute the ELSE process (instruction) (S31).
The program counter is skipped to execute this ELSE processing (S32).

If it is determined in step S31 that the ELSE process is not to be executed, that is, if there is a skip (branch), the program counter is skipped to a count value indicating the ENDIF process (S33). When the skip of the program counter to the ENDIF processing is completed, it is determined whether or not there is a trace request next, that is, whether or not the value of the code part 34b is 1 (S34). (Flag) is set (S
35) Conversely, if it is determined that there is no trace request, the capture prohibition code is not set.

FIG. 12 is an explanatory diagram showing an example of contents stored in the trace memory 44 when a program involving a branch is executed. The example of FIG. 12 illustrates a case where the capture of the trace data is stopped due to the skip of the ELSE process after the execution of the THEN process.

As shown in FIG. 12, the trace memory 44 stores only the execution results of successive instructions. Therefore, the operation state can be accurately monitored in a range where the operation result of the instruction is continuous.

Once the trace has been stopped, the control unit 24
Outputs a signal indicating a trace start instruction to the PC 21 again, and outputs a new monitoring condition when the monitoring condition is changed. As a result, the F / F 41 is set,
Tracing is performed according to the monitoring conditions stored in the various setting registers.

The trace data stored in the trace memory 44 simply stores data values of contacts, coils, and the like in the order in which the instruction execution unit 33 executes the instructions. Therefore, when the execution order of instructions changes due to branching, it is not possible to accurately grasp the correspondence between the graphic symbols and their data values. In this embodiment, the acquisition of the trace data is stopped for this reason.

However, this problem can be avoided by, for example, storing the count value of the program counter together with the trace data in the trace memory 44, while making the processing of the instruction execution unit 33 heavy. This method
It is easy to apply when the number of steps of the program is short or when the logic changes relatively slowly. At this time, the instruction execution unit 33 may write the operands corresponding to the names of the contacts, coils, and the like in the trace memory 44 together with the trace data instead of the count value.

Next, a tracing method for a program including a repetition of a group of instructions such as a loop process will be described. As described above, the sequence of instructions and its operation result usually correspond one-to-one, but the execution result of loop processing (only this expression is used for simplicity) is stored in the trace memory 28 as it is. Thus, the correspondence between the graphic symbol displayed on the display unit 27 and the calculation result corresponding to the graphic symbol does not correspond one-to-one. Therefore, in the present embodiment, the trace memory 44
In which the calculation result is stored.

FIG. 13 is an explanatory diagram showing an example of a program including a loop process, and FIG. 14 is a flowchart showing an example of the program. This program will be described first with reference to FIGS.

This program sets 10 to a flag C indicating the number of times this loop processing is executed at the beginning of the loop processing (loop start instruction: LOOP START) (S4).
1) Then, the value obtained by adding the values of the terminals A and B is substituted for the value of the terminal D (S42). When the assignment of the value to the terminal D is completed, the value of the flag C is decremented, and it is determined whether or not the value of the flag C at this time is 0 (S43). When it is determined that the value of the flag C is not 0, the process returns to step S42, and when it is determined that the value of the flag C is 0, the loop processing is ended here. When the loop process is completed, a process of assigning the value of the terminal D to the terminal E is executed as shown in FIG.

Next, the trace processing when the loop processing is executed will be described. FIG. 15 is a flowchart illustrating a trace process executed when the first instruction in the loop process is executed when the loop process is executed.

In this process, first, it is determined whether or not there is a trace request, that is, whether or not 1 is stored in the code part 34b of the instruction register 34 (S51). If it is determined that there is a trace request, a loop flag (code) indicating the beginning of the loop processing is set in the trace control unit of the trace memory 44 (S52). Is not set.

FIG. 16 is a flowchart showing a trace process executed when the last instruction (loop end instruction: LOOP END) in the loop process is executed. here,
The processing illustrated in FIG. 16 is a pair with the processing illustrated in FIG.

In this processing, first, it is determined whether or not the loop processing has been completed, that is, in FIG. 14, whether or not the processing has been repeated by the value initially set in the flag C (S61).
If it is determined that the loop processing has been completed, the program counter is skipped to a count value indicating the next instruction of this loop processing (S62).

If it is determined in step S61 that the loop processing has not been completed, the program counter is set (skipped) to a count value indicating the first instruction in this loop processing (S63), and whether or not there is a next trace request It is determined whether or not (S64). When it is determined that there is no trace request, the next instruction is executed as it is, and when it is determined that there is a trace request, the value of the write pointer indicating the address to be written in the trace memory 44 is set to the beginning of the loop processing in this loop processing. This is changed by setting the value of the position (address) where the indicated loop flag is written (S65).

FIG. 17 is an explanatory diagram showing an example of contents stored in the trace memory 44 by executing the above-described trace processing. As shown in FIG. 17, a loop flag indicating the beginning of the loop processing is written in the trace control unit of the address where the read data of the terminal A is stored as the trace data. The trace data is written from the address where is written in the trace control unit.

As described above, in this embodiment, while the loop processing is being executed, the operation result of the instruction in the loop processing is sequentially and repeatedly written from the address where the loop flag is written. Then, the operation result is written correspondingly. Accordingly, the correspondence between the trace data read from the trace memory 44 and the graphic symbols displayed on the display unit 27 matches, so that the operation results of the instruction execution unit 33 can be accurately displayed on the monitor in the order of instruction execution.

As shown in FIG. 3, the PC operation state monitoring device of this embodiment is composed of the PC 21 and the support tool 22, and the instruction execution unit 33 executes the instructions stored in the program memory 28. At the same time, the calculation result is written into the trace memory 44. However, if the operation result of the instruction execution unit 33, the count value of the program counter, and the like are output to the support tool 22 at any time, most of the components included in the PC 21 in FIG. Can also. Conversely, if the PC is provided with a display means such as a CRT, the present invention may be applied to the PC and the support tool may not be required.

[0095]

As described above, according to the present invention, the monitor area of the program memory is designated by the area designating means, the execution means reads out the instruction from the program memory, and the monitoring area designated by the area designating means. Is compared by the comparing means, and the writing means sequentially writes the calculation results of the execution means in the trace memory based on the comparison result of the comparing means, and the display means displays the calculation results written in the trace memory on the monitor. Therefore, all execution (operation) results can be displayed on the monitor in the order in which the execution means executed the instructions.

The condition designating means is a task number storing means 1 among an address range storing means for storing monitoring conditions, a task number storing means, and a caller address storing means.
2, and at least one of the caller address storage means 13
Also Bei Eteori, by storing a desired monitoring condition in the storage means with the condition specifying means, the result execution result of the execution means corresponding thereto to be stored in the trace memory, which executes the desired portion of the program You can only monitor.

The writing means monitors the order of the addresses in the program memory read by the execution means, and if an inconsistency occurs in the order of the addresses, stores the fact in the trace memory and executes the execution in the trace memory. If you stop storing results and a loop occurs in address order,
That fact is stored in the trace memory, and writing to the trace memory is looped in accordance with the loop. For this reason, the order of instructions stored in the program memory matches the order of execution results of the execution means stored in the trace memory, so that the monitor display can be accurately performed in the order of instruction execution regardless of the presence or absence of a program branch or loop. Can be done.

Further, since the writing unit writes the execution result of the execution unit into the trace memory, it is not necessary to trace the entire bus, and the hardware can be simplified.

[Brief description of the drawings]

FIG. 1 is a principle diagram showing a configuration of the present invention.

FIG. 2 is a principle diagram showing a configuration of a condition specifying means of the present invention.

FIG. 3 is a circuit block diagram illustrating a schematic configuration of a PC operation state management device according to the present embodiment.

FIG. 4 is a flowchart showing a brief processing operation of an instruction execution unit according to the embodiment.

FIG. 5 is an explanatory diagram showing an example of contents stored in a trace memory.

FIG. 6 is an explanatory diagram showing a tracing method of a first subroutine.

FIG. 7 is an explanatory diagram showing a tracing method of a second subroutine.

FIG. 8 is an explanatory diagram showing an example of a program including a branch.

FIG. 9 is a flowchart showing a program including a branch.

FIG. 10 is a flowchart showing a trace process in the THEN process.

FIG. 11 is a flowchart showing a trace process in the ELSE process.

FIG. 12 is an explanatory diagram showing an example of contents stored in a trace memory when a program including a branch is executed.

FIG. 13 is an explanatory diagram showing an example of a program including a loop process.

FIG. 14 is a flowchart showing a program including a loop process.

FIG. 15 is a flowchart illustrating a trace process executed when the first instruction of the loop process is executed.

FIG. 16 is a flowchart illustrating a trace process executed when the last instruction of the loop process is executed.

FIG. 17 is an explanatory diagram showing an example of contents stored in a trace memory when a program including a loop process is executed.

FIG. 18 is a circuit block diagram illustrating a schematic configuration of a PC and a support tool.

FIG. 19 is an explanatory diagram showing a program example based on a ladder diagram.

[Explanation of symbols]

 1, 28 program memory 2 execution means 3, 21 PC 4 condition specification means 5 comparison means 6 writing means 7, 44 trace memory 8 display means 9 PC operation state monitoring device 11 address range storage means 12 task number storage means 13 caller Address storage means 22 Support tool 23 Keyboard 24 Control unit 25 Memory 26 Display control unit 27 Display unit 30 Address range setting register 31 Task setting register 32 Caller address setting register 33 Instruction execution unit 34 Instruction register 35 Comparator 38 Task execution register 39 Task number comparator 42 Address comparator

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G05B 19/04-19/05

Claims (6)

(57) [Claims] There in claim 1] program memory programmable controller operation state monitoring apparatus for monitoring the operation status of the programmable controller which re Bei execution hands stage reads and executes each instruction at the address of the program stored in the <br/> e Te, the condition specifying means to specify the monitoring conditions when an instruction of the program memory a program stored in the execution hand stage is executed, the execution hands stage reads the instruction of the program memory or program from and comparing the hand stage information is compared with a more specified monitoring conditions in the condition specified hand stage was a trace memory that result the execution hand stage executes program instructions are stored, the comparison result of the comparing hand stepped said trace memory on the basis of
And Shokomite stage for writing execution results of the execution hand stage, anda display means to display the read execution results written in the trace memory, the condition specifying means, said program memory Stored
To store the task number of the program
Disk number storing means, wherein the comparing means stores the task number stored in the task number storing means.
Disk number and the type of program being executed by the execution means.
A programmable controller operating state monitoring device for comparing the operation state with a disk number . 2. A program stored in a program memory.
Execution means for reading and executing the
The operating state of the programmable controller
Programmable controller operation status monitoring device
Te, the instructions of the program stored in the program memory
A condition finger for specifying a monitoring condition for execution by the execution means;
Setting means, and the execution means stores a program from the program memory.
Specify the information from which the instruction has been read by the condition specifying means.
Comparing means for comparing with the monitored condition, and storing the result of executing the program instruction by the executing means.
The trace memory based on the comparison result of the comparing means.
Writing means for writing the execution result of the execution means to the memory, and reading the execution result written to the trace memory
Display means for displaying the data in the program memory.
Caller address where the instruction to call the subroutine is stored
Caller address storage means for storing
The comparison means is stored in the caller address storage means.
Caller address and subroutine executed by the execution means
You and comparing the caller address of routine
Programmer Lama Bull controller operating status monitoring device. 3. The method of claim 1, wherein the conditions specified hand stage, the program notes
Address range that stores the address range of
Comprising a circumference storage means, said comparing hand stage the execution hand stage and address range stored in the address range stored <br/> hand stage the flop
The programmable controller operation state monitoring device according to claim 1 or 2, wherein the operation is compared with an address at which an instruction is read from a program memory . 4. The method of claim 1, wherein the conditions specified hand stage, the program notes
It includes a calling address storage means to store call source address instructions stored calling the definitive to re subroutine as monitoring condition, call the comparison hand stage stored in the source address stored <br/> hand stepped out the call programmable controller operation state monitoring apparatus according to claim 1, wherein the comparing the caller address of the subroutine the execution hand stage and source address is running. Wherein said manual Comite stage, the execution hands stage monitors the sequence of addresses of said program memory read instruction, when a mismatch occurs in the order of the addresses, to the trace memory The programmable controller operating state monitoring device according to claim 1 or 2 , wherein writing of the data is stopped. Wherein said manual Comite stage, the execution hands stage monitors the sequence of addresses of said program memory read instruction, when the loop in the order of the addresses occur, to the trace memory 3. The operation state monitoring device according to claim 1 , wherein the writing is looped in correspondence with the loop.