JPH03274960A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To prevent a fixed pattern noise from being included in a read data by eliminating an excess charge included in the charge transferred by a 1st vertical shift register and outputting the transfer charge to a 2nd shift register. CONSTITUTION:A charge stored in each photosensor 11 is read sequentially by a 1st vertical shift register 13, transferred by the register 13 and inputted to a photodetector section output buffer 14. The charge inputted to the buffer 14 is inputted sequentially to a signal processing circuit 15. The excess charge of the charge inputted to the circuit 15 is sliced at a slice level and the excess charge included in the read charge is cut and inputted to a 2nd vertical shift register 16. When all the charges from the photodetector section are transferred to the register 16, the charge in the register 16 is transferred to an adder section shift register 18. Thus, high speed read is realized and inclusion of a fixed pattern noise in the read data is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state image sensor capable of expanding the dynamic range.

[Conventional technology]

In general, the subject that is converted into a video signal by a solid-state image sensor may have a brightness range that is wider than the dynamic range of the solid-state image sensor, and in such cases it is not possible to accurately restore the image of the subject. . For this purpose, it is necessary to expand the dynamic range of solid-state image sensors.

An example of a device for expanding the dynamic range of a solid-state image sensor is the one shown in Japanese Patent Application No. 83-201406. This works by reading out multiple images with different exposure times from a non-destructive readout type image sensor, storing them in multiple memories provided outside the image sensor, and then adding each image to expand the dynamic range. .

When such a method is applied to a normal CCD, it takes several frames of time to obtain one wide dynamic range image. For example, if you take an image by changing the exposure time five times, it will take five frames to obtain one wide dynamic range image, and it will take time to read the image out of the image sensor. There are drawbacks.

Therefore, as a method of adding together multiple images with different exposure times at a normal television rate, for example,
There is a driving method proposed in No. 591.

In this driving method, a driving pulse having the timing shown in FIG. 11 is applied to a transfer gate for reading charges accumulated in an image sensor. Pulse φ. The image sensor is reset by the pulse φ1, and the accumulated charge is transferred to the vertical shift register by the opening light of tl. Next, at the opening light of t2, the charges are transferred to the vertical shift register by pulse φ2, and the charges transferred by pulse φ and the charges transferred by pulse φ2 are added. Thereafter, the pulses φ,
After the last charge is transferred at and added in the vertical shift register, the added value is t. It is output to the outside of the element during this period.

[Problem to be solved by the invention]

However, with commonly used image sensors, when the light receiving part of the image sensor is irradiated with an excessive amount of light, saturation unevenness occurs and so-called fixed pattern noise appears, and this noise component is included in the added value. There is a problem that the image cannot be accurately restored.

In other words, as shown in Fig. 12, in the image sensor, the charges accumulated in the light receiving section are transferred to the vertical shift register via the transfer gate, but the charges saturated by the excessive amount of light during the exposure period are discharged to the overflow drain. be done. This prevents the effects of saturated charges. However, since the height of the overflow drain gate is uneven, the actual saturation value differs.

Therefore, for example, when driven with the drive pulse shown in FIG. 11, if there is a pixel that is saturated by exposure for a period of t1 to t, the added value added by the vertical shift register will be the fixed pattern noise component. will be included.

The present invention has been made in view of the above-mentioned circumstances, and is a solid-state device that can realize high-speed readout, reliably prevent fixed pattern noise from being included in the readout data, and restore images with high precision. The purpose is to provide an image sensor.

[Means to solve the problem]

In order to solve the above problems, the present invention has a plurality of photoelectric conversion elements arranged two-dimensionally, and transfers charges accumulated in each photoelectric conversion element arranged vertically among these plurality of photoelectric conversion elements. a first vertical shift register that temporarily stores charges transferred by the first vertical shift register for each pixel;
A readout means for reading out the charges sequentially stored in the second vertical shift register for each pixel, an addition means for adding up the charges read by the readout means for each pixel, and an addition obtained by the addition means. In a solid-state imaging device including a horizontal shift register that transfers a value to an output buffer, after removing excess charge included in the charge transferred by the first vertical shift register, the transferred charge is transferred to the second vertical shift register.
The configuration includes signal processing means for outputting to the vertical shift register.

[Effect]

In the present invention, by taking the above-described measures, charges accumulated in a plurality of photoelectric conversion elements are sequentially read out and sent to the signal processing means via the first vertical shift register, where, for example, excessive light amount is detected. If a fixed pattern noise component is included, excess charge consisting of the noise component is removed.

Therefore, the charge from which the noise component has been removed is transferred to the second vertical shift register and temporarily stored. The charges read out from the second vertical shift register by the reading means at different exposure times are added for each pixel by the adding means, thereby expanding the dynamic range. The video signal whose dynamic range has been expanded in this way is output from the output buffer.

〔Example〕

Examples of the present invention will be described below.

This embodiment is an example in which the present invention is applied to a solid-state imaging device having a frame interline transfer structure or a frame transfer structure, and a conceptual diagram of the embodiment is shown in FIG.

The solid-state image sensor 1 of this embodiment includes a light receiving section 2 in which charges are accumulated according to the amount of irradiated light, and the charges accumulated in this light receiving section 2 are sequentially read out and the accumulated charges are read out at different exposure times. a signal processing section 4 that outputs a value obtained by slicing fixed pattern noise when the light receiving section 2 is saturated with a slice level set in advance for cutting excess charge, and this signal processing circuit. 4, a storage section 5 that sequentially stores the output of the storage section 5, an addition section 6 that adds the charges read out from the storage section 5 at each exposure time, a horizontal shift register 7 to which the added value of the addition section 6 is input, and The main component is an output buffer 78 that outputs the charges transferred by the horizontal shift register 7 as a video signal.

FIG. 2 is a diagram showing a specific configuration of the embodiment.

A plurality of photosensors 11 arranged in a matrix,
A transfer gate 12 is provided for each of these photosensors 11 to which a readout drive pulse is applied, and a transfer gate 12 is provided along each transfer gate 12 of each of the photosensors 11 arranged in the vertical direction to read out data from the photosensor 11. The light receiving section 2 is constituted by a plurality of first vertical shift registers 13 that transfer the generated charges.

One end of each vertical shift register 13 is connected to the signal processing circuit 15 via a light receiving section output buffer 714 each consisting of a floating diffusion amplifier. The output side of each signal processing circuit 15 is connected to one end of a second vertical shift register 16. The second vertical shift register 16 is composed of a plurality of registers in which charges read out from each photosensor 11 are temporarily stored for each pixel.
Each register is connected to an adder register 18 via an accumulator transfer gate 17. Adder register 1
8 has a function of sequentially adding charges read out multiple times from each register of the second vertical shift register 16. One end of each adder register 18 is connected to a horizontal shift register 19, and the charges transferred by the horizontal shift register 19 are output from an output buffer 20.

The light receiving section output buffer 14 has a configuration shown in FIG. 3. A voltage is applied to each of the horizontal shift register electrodes 21, and the read charge is transferred from the electrode 21a located at the input end to the output side electrode 21c, and the charge is transferred to the floating diffusion FD via the output gate OG. lead to. The potential of this floating diffusion diffusion FD is reset to the same potential as that of the drain drain DD by a reset pulse applied to the reset gate RG. The period of the reset pulse is synchronized with the charge transfer period. The charges guided to the floating diffusion FD are output to the signal processing circuit 15 via the output buffer 23.

The signal processing circuit 15 has a configuration shown in FIG. The signal processing circuit 15 has an input terminal 24 to which the output of the light receiving section output buffer 14 is applied.

The input terminal 24 is a slice transistor 2 formed by connecting the collectors and emitters of two transistors to each other.
5 via a clamp capacitor C. A slicing level voltage is applied to the other base of the slicing transistor 25, which is a threshold when slicing excess charge. Further, a constant voltage Vcc is applied to the collectors connected to each other. The potential appearing at the emitter of the slice transistor 25 is
is output to the vertical shift register 16. Note that a clamp level is also set in the signal processing circuit 15. Therefore, a feedthrough clamp pulse shown in FIG. 5(b) is applied to the base of the clamp transistor 26, a clamp level voltage is applied to the emitter, and the collector is connected to the base of the slice transistor 25.

The adder register 18 has a sufficient capacity to store charges sequentially read out at different exposure times, its area is set larger than that of the second vertical shift register 16, and the applied voltage is also larger than that of the second vertical shift register 16. It is set to a large value. Furthermore, in order to increase the capacity of the adder register 18,
The impurity concentration of the silicon substrate constituting the adder register 18 is increased.

Next, the operation of this embodiment configured in this manner will be explained.

The charges accumulated in each photosensor 11 are sequentially read out to the vertical shift register 13 of node 1 by a read pulse applied to each light receiving section transfer gate 12, and transferred by the first vertical shift register 13 to the light receiving section output buffer. 14. The charges input to the light receiving unit output buffer 14 are output in synchronization with the charge transfer cycle and are sequentially input to the signal processing circuit 15. The signal input to the signal processing circuit 15 is processed by the clamp transistor 26 in accordance with the feed-through period of the input signal, as shown in FIGS. 5(a) and 5(b).
A feedthrough clamp pulse (b) is applied to the base of the clamp transistor 2, and the feedthrough level is set to the clamp transistor 2.
It is clamped to the clamp level set in 6. Such a ramp is performed each time a feedthrough level appears. The signal clamped in this manner is sliced at the slice level by the slice transistor 25 and then input to the second vertical shift register 16.

All charges from the light receiving section are transferred to the second vertical shift register 16.
When the charge is transferred to the storage section transfer gate 17, a driving pulse is applied to the storage section transfer gate 17, and the charge in the second vertical shift register 16 is transferred to the addition section shift register 18.

Here, in this embodiment, the storage section transfer gate 17
A drive pulse shown in FIG. 6 is applied to the drive pulse shown in FIG.

Note that t shown in FIG. indicates the exposure start time,
φ1 to φ indicate drive pulses for transferring the charges in the second vertical shift register 16 to the adder shift register 18. As a result, the second vertical shift register 16
The charges accumulated sequentially for each pixel in the pulses φ1 to φ
, and five images having different exposure times are transferred for each pixel (photo sensor) to each register of the adder register 18, and are added there. And pulse φ1
After reading out multiple images by applying ~φ, the charge is transferred from the adder register 18 to the horizontal shift register 19 using the period to, and the charge is transferred to the outside of the element via the output buffer 20. .

Note that the charge is transferred to the horizontal shift register 19 by the adder register 18. The charges transferred by the horizontal register 19 are outputted as a video signal via the output buffer 20.

Regarding the photoelectric conversion characteristics obtained by such operation, see Part 7.
This will be explained with reference to the figures. Note that the same figure shows the photoelectric conversion characteristics performed between time t and time t. f1 to f5 are photoelectric conversion characteristics corresponding to each exposure time t1 to t. Therefore, the charges obtained during each exposure time t1 to t are added for each pixel in the adder register 18, and converted into a photoelectric conversion characteristic such as F. This Fo
The characteristic may be a waveform approximated to a logarithm or may be approximated to a waveform of a square root.

Up to now, addition has been performed by changing the exposure time, but the addition operation may also be performed by keeping the exposure time constant. In other words,
Addition without changing the exposure time results in cumulative addition, which reduces random noise and expands the dynamic range as a result. For example, by performing cumulative addition four times, it is possible to achieve a dynamic range twice as wide as JT. When this driving method is used, although the wide dynamic range effect is small, the photoelectric conversion characteristic becomes linear, and the processing circuit after the output of the solid-state image sensor 1 is simplified.

As described above, according to this embodiment, the charges read out from the plurality of photosensors 11 are input to the signal processing circuit 15, where the clamp level is set, and the excess charges are sliced at the slice level by the slice transistor 25. Since the excess charges contained in the charges read out are cut, even if fixed pattern noise is included in the charges read out from each photosensor 11, the noise component can be cut.

In addition, since noise components are cut in this way, and multiple charges obtained by varying exposure times are added for each pixel in the adder register 18, the dynamic range can be expanded. .

As a result, it is possible to obtain a video signal that does not contain noise components and has an expanded dynamic range, and it is possible to obtain extremely high-precision images without being affected by the brightness of the subject. It is also possible to obtain images with an expanded dynamic range.

Furthermore, in the adder register 18 provided inside the element,
Since a plurality of images are added, the readout time can be significantly shortened compared to the case where a plurality of images are taken out from the element and then added.

Next, a modification of the above embodiment will be described.

In the above embodiment, a floating diffusion amplifier is used for the light receiving unit output buffer 14, but it can also be configured with one potential well.

FIG. 8 shows the structure of the light receiving section output buffer 14 and the corresponding signal processing circuit 15 when the light receiving section output buffer 14 is constructed of one potential well. In this modification, a floating drain 30 is provided between the light receiving section output buffer 14 and the signal processing circuit 15, and a sweeping drain 32 is connected to the floating drain 30 via a sweeping transfer gate 31.

FIG. 9 is a cross-sectional view taken along the line A--A shown in FIG. 8, and shows the potential state of the light receiving section output buffer 14. Note that the device is manufactured so that the depth P7o of the potential well is constant for each column.

With such a configuration, the slicing circuit for slicing excess charge can be made denser, and the device can be made smaller.

Further, as another modification, a floating gate amplifier may be used for the light receiving section output buffer 14.

Since the floating gate amplifier has excellent DC voltage stability and low noise, the clamp circuit of the signal processing circuit 15 can be omitted.

Therefore, the signal processing circuit 15 can be composed only of the slice circuit 40 as shown in FIG. That is, the charges applied to the transfer electrode 33 in the light receiving section output buffer 14 are transferred from the transfer electrodes 33 a to 33 c and guided to the floating gate 34 . This floating gate 3
A DC bias voltage is applied to the electrode 4 by the electrode 5.

The electrode 35 is connected to a slice circuit 40 of the signal processing circuit.

The slice circuit 40 includes three field effect transistors 41
, 42 and 43, the sources and drains of transistors 41 and 42 are connected to each other, the electrode 35 is connected to the gate of one transistor 41, and a voltage at a slice level is applied to the gate of the other transistor 42. . Further, a power supply is connected to the mutually connected drains of the transistors 41 and 42, and the source side is connected to the output terminal 4.
4 and another transistor 43 forming a constant current source.

Note that a bipolar transistor can be used instead of a field effect transistor, but since the CCD itself uses a field effect, using a field effect transistor is advantageous in terms of simplifying the manufacturing process.

Furthermore, although the above explanation takes as an example the case where the slice level is constant, it is also possible to change the slice level according to the exposure time. Therefore, when simplifying the drive circuit, fix the slice level and
Function F. When it is desired to increase the degree of freedom, it is desirable to make the slice level variable.

〔Effect of the invention〕

As detailed above, the present invention provides a solid-state image sensor that can realize high-speed readout, reliably prevent fixed pattern noise from being included in the readout data, and restore images with high precision. can.

[Brief explanation of drawings]

Fig. 1 is a conceptual diagram of an embodiment, Fig. 2 is a block diagram of a solid-state image sensor according to an embodiment, Fig. 3 is a block diagram of a light receiving section output buffer, Fig. 4 is a block diagram of a signal processing circuit, and Fig. 5 is a block diagram of a signal processing circuit. The figure is a diagram explaining the operation of the signal processing circuit, Figure 6 is a diagram showing the drive pulse applied to the storage transfer gate, Figure 7 is a diagram showing the photoelectric conversion characteristics according to each exposure time, and Figure 8 is a diagram showing the light reception. FIG. 9 is a cross-sectional view taken along the line A-A shown in FIG. 8, FIG. 10 is a diagram showing another modification, and FIG. A diagram showing drive pulses,
FIG. 12 is a diagram showing the potential of the image sensor. DESCRIPTION OF SYMBOLS 1... Solid-state image sensor, 2... Light receiving part, 3... Drive part, 4... Signal processing part, 5... Accumulating part, 6... Adding part, 7.19... Horizontal shift register, 8, 20・
...Output buffer 7.11...Photo sensor, 12...
- Transfer gate, 13... First vertical shift register, 14... Light receiving unit output buffer, 15... Signal processing circuit, 16... Second vertical shift register, 1
7...Storage section transfer gate,

Claims (1)

[Scope of Claims] A plurality of photoelectric conversion elements arranged two-dimensionally, and a first vertical transducer that transfers charges accumulated in each of the photoelectric conversion elements arranged vertically among the plurality of photoelectric conversion elements. a shift register; a second vertical shift register that temporarily stores charges transferred by the first vertical shift register for each pixel; and a second vertical shift register that temporarily stores charges transferred by the first vertical shift register for each pixel; A solid-state imaging device comprising: a readout means for reading out each pixel; an addition means for adding charges read by the readout means for each pixel; and a horizontal shift register for transferring the added value obtained by the addition means to an output buffer. A solid-state device, characterized in that the element is equipped with a signal processing means for removing excess charge contained in the charge transferred by the first vertical shift register and then outputting the transferred charge to the second vertical shift register. Image sensor.