JPH03274836A - Receiver for pseudo-random signal - Google Patents

Abstract

PURPOSE:To accurately distinguish the occurrence of a mere bit error from that of synchronizing step out to be judged by providing a synchronizing step-out detecting synchronous circuit having the same constitution as a measuring synchronous circuit and providing a bit pattern comparator in which the logical states of shift registers in two synchronous circuits can be compared in parallel. CONSTITUTION:After synchronism between a reception signal and a PN signal at a reception side generated by the shift register 11 and an EXOR gate 12 in the synchronous circuit 1 for measurement is established, the reception signal is compared with the output of the synchronous circuit 1 for measurement, and when a bit error is detected, the reception signal is read in the shift register 41 at the synchronizing step-out detecting synchronous circuit 4 having the same constitution as the measuring synchronous circuit 1. Then, the synchronism between the reception signal and the PN signal at the reception side generated at the synchronizing step-out detecting synchronous circuit 4 can be established. The logical states of the shift registers 11, 41 of the measuring synchronous circuit 1 and the synchronizing step-out detecting synchronous circuit 4 are compared with each other by the bit pattern comparator 7, and it is judged that it is the synchronizing the step out when even one bit error occurs in both logical states.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a signal receiving device that uses a pseudorandom signal to detect bit errors that occur during data transfer. The present invention relates to a pseudorandom signal receiving device that can quickly detect a pseudorandom signal.

Specifically, the receiving side is equipped with two pseudo-random signal generation circuits that generate signals with the same pattern as the pseudo-random signal pattern prepared on the transmitting side, and one of the pseudo-random signal generating circuits is used for bit error detection. , and the other is used to detect out-of-synchronization.

[Conventional technology]

When a pulse is transmitted on a digital communication line,
Pulses may disappear or unnecessary pulses may occur due to jitter or level fluctuations due to noise, crosstalk, etc. In this case, the data sent from the transmitting side will be transmitted to the receiving side with changes, and the transmission quality of the digital communication line will deteriorate. The transmission quality of a digital communication line can be evaluated by the bit error rate. The measuring device for this purpose is equipped with a PN signal generation circuit on the receiving side that generates a signal with the same pattern as the pseudo-random signal pattern prepared on the transmitting side, and establishes pattern synchronization between the PN signal and the received signal. After that, each bit of both is compared, and the error rate is calculated from the difference.

Although it is naturally necessary that clock synchronization is established in addition to pattern synchronization, the present invention relates to pattern synchronization, and a description of clock synchronization will be omitted. Hereinafter, the out-of-synchronization of patterns will simply be referred to as out-of-synchronization.

Here, we will define the terms used in the following description.

First, the transmission signal is a pseudorandom signal generated by a transmitting device paired with a pseudorandom signal receiving device according to the present invention. This signal is guided to a receiving device via a transmission medium.

Next, the received signal is a signal guided to the input end of the receiving device, and is the signal that the transmitted signal has passed through the transmission medium.

When no bit errors occur between the transmitting end and the receiving end, the transmitted signal and the received signal are essentially the same. However, when a bit error occurs, the received signal differs from the transmitted signal because certain bits are missing or extra bits are superimposed.

The PN signal refers to the shift register 11 or 41 and the exclusive OR gate 1 provided in the receiving device.
This is a pseudo-random signal generated by a pseudo-random signal generating circuit whose bottom part is 2 or 42, and has exactly the same pattern as the transmission signal.

The operating procedure for detecting out-of-synchronization according to the prior art will be described below with reference to FIG.

i) When generating a PN signal that is repeated at a period of (2'-1) bits using an M-bit shift register, first, a path of 2 cm2a is formed by the first switch 2 according to the control signal from the control unit 28. Then, the state is changed so that the received signal is read into the shift register 11.

ii) The shift register 11 reads one column of M bins in the received signal.

After reading one row of M bins of the received signal into the shift register 11, the first switch 2 is switched by a control signal from the control unit 28 to form a path between 2 cm 2b. As a result, the measurement synchronization circuit 1 generates a PN signal that has the same pattern as the first and subsequent M highs of the transmitted signal and also has the same phase as the received signal.
Generate a signal. That is, the synchronization of the measurement synchronization circuit 1 is established. This is assuming that there is no error in one column of M highs read into the shift register 11.

tv) - When fishing on a boat, take into consideration that there may be errors in the bits of the received signal that has been read in, and continue with the following procedure.

That is, the signal generated inside the measurement synchronization circuit 1 and the received signal are compared by the comparator 3 for more than M pits, and if there is no error, it is assumed that synchronization has been established (this operation is called synchronization protection).

V) After synchronization is established, the received signal and the PN signal output from the measurement synchronization circuit 1 are compared by the comparator 3, and the number of times of comparison is counted by the first counter 14. A second counter 15 counts the number of bit errors that occur within a period of time, and when the number exceeds a preset number, it is considered that an out-of-synchronization has occurred.

The above is the method of detecting out-of-synchronization according to the prior art.

[Problems to be Solved by the Invention] The conventional method detects out-of-synchronization by counting the number of times a bit error occurs, and synchronizes only when the number of bit errors has occurred exceeds a preset number. Therefore, even though no synchronization has occurred between the received signal and the PN signal output from the receiving side PN signal generation circuit, it is determined that a bit error has simply occurred. , there is a problem that it is determined that the synchronization is out of synchronization.

Another drawback is that it takes time to detect out-of-synchronization.

There was also no way to know exactly how much, if any, they were out of sync.

[Means to solve the problem]

In order to solve the above problems, the present invention has a shift register 11 and an exclusive OR gate 12, as shown in FIG.
and an out-of-synchronization detection circuit having the same configuration as the above-described measurement synchronization circuit for determining whether or not out-of-synchronization has occurred. A bit pattern comparator 7 is provided for comparing the logical states of the shift registers 11 and 41 in both synchronizing circuits in parallel.

[Effect]

Next, the operating procedure for detecting out-of-synchronization according to the present invention will be described.

The received signal and the P on the receiving side generated by the shift register 11 and exclusive OR gate 12 of the measurement synchronization circuit 1
After synchronization with the N signal is established, (1) the received signal and the output of the measurement synchronization circuit 1 are compared by the comparator 3;

■When the comparator 3 detects a bit error, the received signal is read into the shift register 41 on the side of the out-of-synchronization detection synchronization circuit 4, which has the same configuration as the measurement synchronization circuit 1, and the received signal and , synchronization circuit 4 for detecting out-of-synchronization
Establish synchronization with the PM signal on the receiving side generated by .

■Compare the logic states of the shift registers 11.41 of the measurement synchronization circuit l and the synchronization circuit 4 for out-of-synchronization detection in parallel using the bit pattern comparator 7, and if the logic states of both differ by even l bit, the synchronization I judge it to be a mistake.

〔Example〕

The present invention will be explained in detail below.

First, the authority of the embodiment of the present invention shown in FIG. 3 will be explained.

The measurement synchronous circuit 1 is authorized by a shift register 11 and an exclusive OR gate 12. The first switch 2 is set to 2cm2a or 2cm2b depending on the control signal from the control unit 8.
form a route. When the first switch 2 forms a path of 2 cm2a, the received signal is input to the shift register 11 while the path is being formed. On the other hand, when the first switch 2 forms the path 2c-2b, the output of the exclusive OR gate 12 is guided to the input of the shift register 11. Further, the output of the shift register 11 and the output of a predetermined bit of the shift register 11 are guided to respective inputs of the exclusive OR gate 12. In this state,
The measurement synchronization circuit 1 generates a PN signal having essentially the same pattern as the transmission signal. The comparator 3 compares the received signal with the PN signal generated inside the measurement synchronization circuit 1, and if there is a discrepancy, it notifies the control unit 8 that a bit error has occurred. The control unit 8 receives the error notification from the comparator 3 and outputs a switching signal to the second switch 5. The out-of-synchronization detection synchronization circuit 4 has exactly the same authority as the measurement synchronization circuit 1, and is authorized by the shift register 41 and the exclusive OR gate 42. Further, the second switch 5 also has exactly the same authority as the first switch 2. The bit pattern comparator 7 compares the logic states of the two shift registers 11 and 41 in parallel, and outputs the result when it detects an out-of-synchronization.

Next, the operation procedure of the present invention will be explained. The operation is performed by executing the procedures described in prior art i) to tv) and establishing synchronization between the received signal and the PM signal generated from the measurement synchronization circuit 1. , we will start from the state after the synchronization protection is taken care of. Further, in this embodiment, the shift register is 5 bits (M-5).

Once the synchronization is established between the received signal and the PN signal generated from the measurement synchronization circuit 1, the synchronization may be caused by the extraction process when extracting the clock from the received signal, or by interference between the transmitting device and the receiving device. This may occur due to bit loss in the equipment used or the transmission medium used. If synchronization is lost, follow the steps below to detect this.

(1) PN generated from the received signal and measurement synchronization circuit 1
Compare with the signal.

(2) Comparator 3 detects a bit error.

(3) If an error is detected in the comparator 3, the comparator 3 notifies the control unit 8 of the occurrence of the error.

(4) A control signal from the control unit 8 causes the second switch 5 to form a path of 5 cm 5a and switch to a state in which the received signal is read into the shift register 41.

(5) Read one column of M bins in the received signal into the shift register 41.

(6) After reading one column of M bins in the received signal into the shift register 41, the second switch 5 is switched by the control signal from the control section 8 to form a path between 5 cm 5b. As a result, the out-of-synchronization detection synchronization circuit 4 generates a PN signal that has the same pattern as the transmission signal from the fourth row of M bins onward and has the same phase as the reception signal.

That is, the synchronization of the out-of-synchronization detection synchronization circuit 4 is established. This is the case assuming that there is no error in one column of M highs read into the shift register 41.

(7) - When fishing on a boat, take into account that there is an error in the received signal that has been read, and then perform the following procedure. The comparator 6 compares M bits by 1 or more, and if there is no error, it is assumed that synchronization has been established (this operation is called synchronization protection).

(8) After the synchronization of the out-of-synchronization detection synchronization circuit 4 is established, the bit pattern comparator 7
The logical states of the shift registers 11 and 41 of the out-of-synchronization detection synchronization circuit 4 are compared in parallel.

(9) If all of the comparison results are equal, follow the steps (1) above.
Since the bit error detected in step (2) is a simple bit error and is not caused by out-of-synchronization, the process returns to step (1) above and waits for the next bit error detection.

0[D On the other hand, if the comparison result differs by even 1 bit, it is determined that the bit error detected in the above procedure (1) is due to an out-of-synchronization, and that the measurement synchronization circuit 1 has caused an out-of-synchronization.

The result of this out-of-synchronization is displayed on the display unit 10 for the operator of the measuring instrument to recognize. Alternatively, the comparator 3 compares the received signal and the PN signal output from the measurement synchronization circuit 1, and the first and second counters 14 and 15 count the number of times the comparison has been made and the number of bit errors, respectively. You may perform processing to invalidate the results.

Furthermore, when it is determined that an out-of-synchronization has occurred, the control unit 8 is notified of the out-of-synchronization. Normally, the measurement synchronization circuit 1 is resynchronized, but in the present invention, the measurement synchronization circuit 1 and Since the synchronization circuit 4 for detecting out-of-synchronization has exactly the same configuration, the synchronization circuit 4 for detecting out-of-synchronization, which has been synchronized, by the instructions from the control unit 8 according to steps (4) to (6) above. It is of course also possible to continue counting the number of bit errors by using the out-of-synchronization detection synchronization circuit 4 as the measurement synchronization circuit 1 instead of the measurement synchronization circuit 1. In this case, the third switch 13 changes the path from 13a to 13c to 13b to 13c according to an instruction from the control unit 8.
13c, the first counter 14 and the second counter 15 count the number of times the received signal is compared with the PN signal output from the synchronization circuit 4 for out-of-synchronization detection and the number of bit errors, respectively.

The above description is the 4th W! This corresponds directly to the flowchart shown by J. Steps i) to tv) are the procedures of the prior art, and in addition to steps i) to tv), steps (1) to aω are the procedure of the present invention.

Next, the difference in average out-of-synchronization detection time between the conventional technique and the present invention will be explained using FIG. The detection time by the method of the prior art is shown by a broken line, and the detection time by the method of the present invention is shown by a solid line, respectively. In the conventional technology, as a method for detecting synchronization loss, a comparator 3 compares the received signal and the PM signal output from the measurement synchronization circuit 1, and detects bit errors exceeding a certain probability set in advance. If this occurs,
The method is to assume that the synchronization is out of sync.

Usually, the probability is expressed by a received signal of a predetermined number of bits and a predetermined number of bit errors therein. - The probability for boat fishing is set from 1/10 to 115. The number of times the received signal and the PN signal output from the measurement synchronization circuit 1 are compared is counted, and the counting result is determined by a predetermined number of bits (
When the counted number of bit errors exceeds a predetermined number of bit errors (n) before reaching number m), it is considered to be out of synchronization.

In FIG. 5, the horizontal axis represents the predetermined number of bits m, and the vertical axis represents the time T required for average out-of-synchronization detection.

When out-of-synchronization is detected using the method of this prior art, the time required from when out-of-synchronization occurs until it is detected as out-of-synchronization is determined as follows. When synchronization is lost, comparator 3 detects an error once every two bits on average. Therefore, it takes an average of 2X to reach the predetermined bit error count n.
A period of nXt is required. Here, t is the period of the clock. Further, in this method, the control unit 28
The number of times the received signal and the PN signal output from the measurement synchronization circuit l are compared and the number of bit errors are counted by the first counter 14 and the second counter 15, respectively, and each time the counting result reaches m. Counter 1 that re-counted the value
It may take more time to clear 4.15 and re-count. The probability that the number of times the received signal is compared with the PN signal output from the measurement synchronization circuit l reaches m before the counted value of the number of bit errors reaches n is 2n/
m, and the time required to detect out-of-synchronization in that case is 3XnXt on average. Therefore, for example, if n=(115)m, the average time T required for the synchronization to be lost is T=0.48mt.

In this way, in the conventional method, if the predetermined number m of bits is small, the time required to detect out-of-synchronization is short; however, if you want to accurately detect out-of-synchronization, As the number of bit errors increases, the time required to detect out-of-synchronization increases proportionally.If you try to detect out-of-synchronization faster by reducing 0m, the accuracy of detecting bit errors and out-of-synchronization will decrease. Become.

In the present invention, when the comparator 3 on the measurement synchronous circuit 1 side detects a bit error, the synchronization circuit 4 for out-of-synchronization detection starts detection. It takes time to read the signal into the shift register 42, generate a PN signal in the synchronization circuit 4 for out-of-synchronization detection, and perform synchronization protection. The shift register 42 is 5 bits, and the number of bits of the shift register is 2.
If 10-bit synchronization protection, which is twice as long, is performed, the time required to establish synchronization is 16T. It is the following formula T-(
Mt+t+2Mt). The first term on the right side of this equation, Mt, is the time required to read into the shift register, the second term, t, is the time to detect bit errors, and the third term, 2
Mt is the time required for synchronization protection.

Furthermore, after that, the shift register 1 of the measurement synchronous circuit 1
1 and the shift register 41 of the synchronization circuit 4 for detecting out-of-synchronization.
It is determined whether or not synchronization is out of synchronization by directly comparing the contents bit by bit. Therefore, the time required to detect out-of-synchronization is constant regardless of m, , n, and the accuracy of out-of-synchronization detection is always maintained.

The bit pattern comparator 7 described above is connected to each shift register 11.
．． 41 logic states are compared in parallel and only a match or mismatch is detected, but in another embodiment, the bit pattern comparator 7 compares the logic states of each shift register 11.4.
1 in parallel, it is also possible to output how many bits the PN signal outputs from the measurement synchronization circuit 1 and the synchronization circuit 4 for out-of-synchronization detection have shifted (number of slips). The method for detecting the number of slips in this bit pattern will be explained with reference to FIGS. 6 and 7.

FIG. 6 shows a memory 81 in which slip numbers of bit patterns corresponding to possible states of the two shift registers 11.41 are written in advance, and the mutual relationship between the memory 81 and the shift registers 11.41. receives input from shift register H,41 as an address,
The number of slips and the out-of-synchronization detection signal (a) are output.

FIG. 7 is a diagram showing the internal state of the memory 81.

In this memory 81, the last bit of the data is used as a bit indicating whether or not an out-of-synchronization has occurred.

The number of slips in this bit pattern is detected by the following procedure. First, an address is generated using the logic state of the shift register 11 as the upper bits and the logic state of the shift register 41 as the lower bits. Then, the data (slip number) pointed to by that address is output from the memory 81. This address and data are determined in advance by the relationship between the states of any two shift registers and the number of slips of the PN signal in that case.For example, the input from shift register 11 is 00001, and the input from shift register 41 is is 0
1001, the address is 0000101001, the data pointed to by that address is 26, and both P
The pattern of the N signal has 26 slips. By preparing such a table in the memory 81 and configuring the bit pattern comparator 7, it becomes possible not only to simply detect out-of-synchronization, but also to easily detect the number of bit pattern deviations.

〔Effect of the invention〕

According to the pseudorandom signal receiving device of the present invention, the synchronization circuit 4 for out-of-synchronization detection having the same authority as the measurement synchronization circuit 1 is provided, and each shift register 11 in the two synchronization circuits is provided.
．． Since the bit pattern comparator 7 is provided to compare the logic states of 41 in parallel, it is possible to accurately distinguish between the occurrence of a simple bit error and the occurrence of out-of-synchronization.
Even if a large number of bit errors occur, it is no longer necessary to mistakenly assume that synchronization has occurred and redo the measurement.

In addition, as a method for detecting out-of-synchronization, the received signal and the PN signal output from the measurement synchronization circuit 1 are compared with the comparator 3, and bit errors exceeding a preset number are detected. Compared to the conventional method, which assumes that synchronization is out of synchronization, it is possible to detect out of synchronization in a fixed amount of time regardless of the predetermined number of bits, etc. can also be done easily.

In addition, the measurement synchronous circuit 1 and the out-of-synchronization detection synchronous circuit 4
have exactly the same configuration, and when the out-of-synchronization circuit 4 detects out-of-synchronization of the measurement synchronization circuit 1, the out-of-synchronization detection synchronization circuit 4 can continue to detect bit errors. The measurement synchronization circuit 1 saves time until bit error detection can be started compared to when synchronization with the received signal is reestablished.

Furthermore, it is also possible to detect the number of bit pattern slips, which was previously impossible.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the configuration of the present invention, Figure 2 is a block diagram showing the configuration of the prior art, Figure 3 is a block diagram of an embodiment of the present invention, and Figure 4 shows the prior art and the present invention. FIG. 5 is a flowchart showing the operation of FIG. 5, which shows the difference in average desynchronization detection time between the conventional technique and the present invention. Further, FIG. 6 is a diagram showing the authority when the bit pattern comparator 7 is provided with a memory 81 for detecting the number of bit pattern slips, and FIG. 7 is a diagram showing the inside of the memory.・Shift register, 12... Exclusive OR gate, 41... Gate, 14. 8 shift register, 42. 28... Control unit, ・First counter, 15. 13... Third switch: -Memory.・Exclusive OR・Second currant・・Measurement synchronization circuit, 2・・First switch, 3・
...Comparator, 4...Synchronization circuit for detecting out of synchronization, 5.
...Second switch, 6.Comparator, 7.Bit pattern comparator, 8.Control unit, 9.Counter, IO
...Display section, 11 patents issued

Claims (1)

[Claims] A measurement synchronous circuit (1) having a shift register and an exclusive OR gate, and a receiving signal consisting of a pseudo-random signal and the output from the exclusive OR gate are switched and input to the shift register. A pseudorandom signal receiving device having a first switch (2) and a comparator (3) that compares the received signal with an output from the measurement synchronization circuit, the configuration being the same as that of the measurement synchronization circuit. and a second switch (5) that switches between the received signal and the output from the exclusive OR gate of the synchronization circuit for out-of-synchronization detection and inputs it into the shift register.
a comparator (6) that compares the received signal with the output from the out-of-synchronization detection synchronous circuit; and a bit comparison between the shift register of the measurement synchronous circuit and the shift register of the out-of-synchronization detection synchronous circuit. 1. A pseudo-random signal receiving device comprising: a bit pattern comparator (7) that performs the following.