JPH03274799A - Metallic insulating substrate of semiconductor device - Google Patents
Metallic insulating substrate of semiconductor deviceInfo
- Publication number
- JPH03274799A JPH03274799A JP7430590A JP7430590A JPH03274799A JP H03274799 A JPH03274799 A JP H03274799A JP 7430590 A JP7430590 A JP 7430590A JP 7430590 A JP7430590 A JP 7430590A JP H03274799 A JPH03274799 A JP H03274799A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- metal
- metallic
- semiconductor device
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 239000011888 foil Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 36
- 239000003822 epoxy resin Substances 0.000 abstract description 6
- 229920000647 polyepoxide Polymers 0.000 abstract description 6
- 239000004020 conductor Substances 0.000 abstract description 4
- 239000000919 ceramic Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000020169 heat generation Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の基板、特に金属絶縁基板の構成に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a substrate for a semiconductor device, particularly a metal insulating substrate.
昨今では半導体装置の基板として、旧来のセラミック基
板の代わりに製作コストの安価な金属絶縁基板が多用さ
れている。Nowadays, metal insulating substrates, which are inexpensive to manufacture, are often used as substrates for semiconductor devices instead of conventional ceramic substrates.
この金属絶縁基板の構造は、第2図に示すように、例え
ばアルミなどの金属ベース板lの上にエポキシ樹脂など
の有機系絶縁層2.および半導体チップ3などの回路部
品に対する配線用導体として必要形状にパターンニング
した銅箔4を重ねて一体に構成したものである。The structure of this metal insulating substrate is, as shown in FIG. 2, on a metal base plate l made of aluminum, for example, and an organic insulating layer 2 made of epoxy resin or the like. A copper foil 4 patterned into a required shape as a wiring conductor for circuit components such as a semiconductor chip 3 is laminated and integrated.
〔発明が解決しようとするII)
ところで、前記した金属絶縁基板を高電圧、高周波用パ
ワー半導体装置の基板として採用する場合に次記のよう
な問題点がある。[Object to be Solved by the Invention II] By the way, when the metal insulating substrate described above is employed as a substrate for a high voltage, high frequency power semiconductor device, there are the following problems.
すなわち、半導体装置に電圧を印加した際に絶縁層を通
して金属ヘース板にリーク電流が流れる。That is, when a voltage is applied to the semiconductor device, a leakage current flows to the metal base plate through the insulating layer.
しかも、このリーク電流が大であると発熱、感電のおそ
れがあり、一般の電気II器では1st、火災防止のた
めにリーク電流を数mA以下に抑えるよう規定されてい
る。Moreover, if this leakage current is large, there is a risk of heat generation and electric shock, and in general electric appliances, it is specified that the leakage current should be suppressed to several mA or less to prevent fires.
ここで、電圧を印加した際に基板に流れるリーク電流I
は次式で表される。Here, the leakage current I flowing through the substrate when voltage is applied is
is expressed by the following formula.
■−2π fcV−・−・・・・・−・・・−・・−・
・−・−(1)C奪ε、εPA/l・・・・−・・−・
・−・−・・伐)但し、【:使用周波数、■:印加電圧
、C;絶縁層の静電容量、
ε、:真空での誘電率、
ε、:比誘電率、
A:基板の面積、t:絶縁層の淳さ、
上記(1)、 (2)式から明らかなように、リーク電
流■は基板絶縁層の静電容量に比例し、かつその静電容
量は比誘電率ε1.基板面積Aを一定とすれば絶縁層の
厚さtに逆比例する。■−2π fcV−・−・・・・・−・・・−・・−・
・−・−(1) C deprivation ε, εPA/l ・・・・−・・−・
・-・-・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・However, [: operating frequency, ■: applied voltage, C: capacitance of insulating layer, ε,: dielectric constant in vacuum, ε,: relative dielectric constant, A: area of substrate , t: Thickness of the insulating layer As is clear from the above equations (1) and (2), the leakage current ■ is proportional to the capacitance of the substrate insulating layer, and the capacitance has a relative dielectric constant ε1. If the substrate area A is constant, it is inversely proportional to the thickness t of the insulating layer.
一方、特にパワー半導体装置では回路素子の発熱が大き
く、その温度上昇を規定温度内に保持するためには適切
な熱設計を行うことが実装面で重要である。かかる点、
基板の絶縁層(誘電体)の厚さを薄くすれば回路素子に
対する熱抵抗を低くできる反面、静電容量が増大して先
記のようにリーク電流が増大する。On the other hand, especially in power semiconductor devices, circuit elements generate a large amount of heat, and in order to maintain the temperature rise within a specified temperature range, it is important from a mounting standpoint to perform appropriate thermal design. Such points,
If the thickness of the insulating layer (dielectric material) of the substrate is reduced, the thermal resistance to the circuit elements can be lowered, but on the other hand, the capacitance increases and leakage current increases as described above.
この点につき金属絶縁基板とセラ電ツク絶縁基板とを比
べると、比誘電率t1は両者ともほぼ近い値であるのに
対して、熱伝導率(W/c+e”c)はセラミック基板
よりも1桁低い値を示す、このため基板の熱抵抗をセラ
ミック基板と同等に抑えるには、金属絶縁基板の絶縁層
厚さを大幅に薄くする必要があり、基板の面積を同一と
すれば、金属絶縁基板の絶縁層(エポキシ樹脂)の静電
容量Cはセラミック基板(アルミナ製)の約6.6倍に
も達する。In this regard, when comparing a metal insulated substrate and a ceramic insulated substrate, the dielectric constant t1 of both is almost similar, but the thermal conductivity (W/c+e''c) is 1 higher than that of the ceramic substrate. Therefore, in order to suppress the thermal resistance of the board to the same level as that of a ceramic board, the thickness of the insulating layer on the metal insulating board must be significantly reduced. The capacitance C of the insulating layer (epoxy resin) of the substrate is about 6.6 times that of the ceramic substrate (made of alumina).
このために、第2図に示した従来構造の金属絶縁基板を
高電圧、高周波用パワー半導体装置の基板として採用す
るに当たり、リーク電流を低く抑えるために絶縁層の厚
さを大にすると熱抵抗が増大し、逆に熱抵抗を抑えるた
めに絶縁層の厚さを小にするとリーク電流が増大すると
言った問題があり、このことが高電圧、高周波用パワー
半導体装置への金属絶縁基板の適用化を困難にしている
大きな原因となっている。For this reason, when a metal insulating substrate with the conventional structure shown in Figure 2 is used as a substrate for a high-voltage, high-frequency power semiconductor device, increasing the thickness of the insulating layer in order to suppress leakage current reduces thermal resistance. On the other hand, reducing the thickness of the insulating layer to suppress thermal resistance increases leakage current. This is a major reason why it is difficult to
本発明は上記の点にかんがみなされたものであり、基板
の構造を改良することにより、金属ベース板側にリーク
電流が流れるのを防止できるようにした半導体装置の金
属絶縁基板を提供することを目的とする。The present invention has been made in view of the above points, and aims to provide a metal insulating substrate for a semiconductor device that can prevent leakage current from flowing to the metal base plate side by improving the structure of the substrate. purpose.
上記課題を解決するために、本発明の金属絶縁基板は、
有機系絶縁層の層内にシールド用金属箔を埋設して構成
するものとする。In order to solve the above problems, the metal insulating substrate of the present invention
A shielding metal foil is embedded in an organic insulating layer.
(作用〕
上記の構成において、シールド用金属箔は半導体装置内
部で例えば零電位の回路導体に接続される。したがって
、半導体装置の通電時に基板内に流れるリーク電流はシ
ールド用金属箔に集電されて装置内部で処理されること
になり、金属ベース板にリーク電流の流れることがない
。(Function) In the above configuration, the shielding metal foil is connected to, for example, a zero-potential circuit conductor inside the semiconductor device. Therefore, the leakage current flowing in the substrate when the semiconductor device is energized is collected by the shielding metal foil. This means that no leakage current flows through the metal base plate.
第1図は本発明実施例による金属絶縁基板の構造を示す
ものであり、第2図に対応する同一部材には同じ符号が
付しである。FIG. 1 shows the structure of a metal insulating substrate according to an embodiment of the present invention, and the same members corresponding to FIG. 2 are given the same reference numerals.
すなわち、本発明により金属絶縁基板の有機系絶縁層(
エポキシ樹脂)2は2層2a、 2bに分割されており
、この分割層2aと2bとの間に符号5で示すシールド
用金属箔が介装されている。このシールド用金属M5は
、例えば圧延加工で作られた銅箔である。また、かかる
金属絶縁基板を製造するには、例えばアル果などの金属
ベース板1の上に分割絶縁層2a+金属ベース板lと同
じ外形のシールド用金属箔51分割絶縁層2b、配線用
金属箔4を順に重ねて一体形成する。なお、図示のよう
に分割絶縁層2bにあらかしめスルーホール2Cを形成
しておくことにより、シールド用金!KFfi5と回路
側の導体との間の接続を簡単に行うことができる。That is, according to the present invention, the organic insulating layer (
The epoxy resin (epoxy resin) 2 is divided into two layers 2a and 2b, and a shielding metal foil indicated by reference numeral 5 is interposed between the divided layers 2a and 2b. This shielding metal M5 is, for example, a copper foil made by rolling. In addition, in order to manufacture such a metal insulating substrate, for example, on a metal base plate 1 such as an apple, a divided insulating layer 2a + a metal foil 51 for shielding having the same external shape as the metal base plate 1, a divided insulating layer 2b, a metal foil for wiring, etc. 4 are stacked one on top of the other in order to form one piece. In addition, by forming roughened through holes 2C in the divided insulating layer 2b as shown in the figure, shielding gold can be removed. Connection between the KFfi5 and the conductor on the circuit side can be easily made.
本発明による半導体装置の金属絶縁基板は、以上説明し
たように構成されているので、次記の効果を奏する。Since the metal insulating substrate of the semiconductor device according to the present invention is configured as described above, it achieves the following effects.
(1)半導体装置の通電時に基板内に流れるリーク電流
は、シールド用導体箔を通して半導体装置の内部で処理
することが可能であり、金属ベース板側での発熱、感電
のおそれがない。(1) Leakage current that flows into the substrate when the semiconductor device is energized can be disposed of inside the semiconductor device through the conductive foil for shielding, and there is no risk of heat generation or electric shock on the metal base plate side.
(2)これにより、金属絶縁基板を高電圧、高周波のパ
ワー半導体装直に適用するに際して、放熱性を考慮した
低熱抵抗、並びに金属ベース板へのリーク電流防止の双
方の条件を十分に満たす金属絶縁基板を得ることができ
る。(2) As a result, when applying a metal insulating substrate directly to high-voltage, high-frequency power semiconductor devices, a metal that satisfies both the requirements of low thermal resistance in consideration of heat dissipation and prevention of leakage current to the metal base plate. An insulating substrate can be obtained.
第1図は本発明実施例による金属絶縁基板の構造を示す
部分断面図、第2図は従来における金属絶縁基板の部分
断面図である0図において、1:金属ベース板、2:有
機系絶縁層、2a、2b:分割絶縁層、3:半導体チッ
プ、4:配線用金属術1
痢Z区Fig. 1 is a partial sectional view showing the structure of a metal insulating substrate according to an embodiment of the present invention, and Fig. 2 is a partial sectional view of a conventional metal insulating substrate. Layer, 2a, 2b: Divided insulating layer, 3: Semiconductor chip, 4: Wiring metal technique 1 Z area
Claims (1)
ねた構造の半導体装置の金属絶縁基板において、前記絶
縁層の層内にシールド用金属箔を埋設して構成したこと
を特徴とする半導体装置の金属絶縁基板。1) A metal insulating substrate for a semiconductor device having a structure in which an organic insulating layer and a conductive foil for wiring are stacked on a metal base plate, characterized in that a shielding metal foil is embedded within the insulating layer. Metal insulating substrate for semiconductor devices.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7430590A JPH03274799A (en) | 1990-03-23 | 1990-03-23 | Metallic insulating substrate of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7430590A JPH03274799A (en) | 1990-03-23 | 1990-03-23 | Metallic insulating substrate of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03274799A true JPH03274799A (en) | 1991-12-05 |
Family
ID=13543285
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7430590A Pending JPH03274799A (en) | 1990-03-23 | 1990-03-23 | Metallic insulating substrate of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03274799A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05304345A (en) * | 1992-04-27 | 1993-11-16 | Sanken Electric Co Ltd | Metallic wiring board and its production |
US7638873B2 (en) | 2005-12-01 | 2009-12-29 | Nitto Denko Corporation | Wired circuit board |
US7723617B2 (en) | 2006-08-30 | 2010-05-25 | Nitto Denko Corporation | Wired circuit board and production method thereof |
US8134080B2 (en) | 2005-07-07 | 2012-03-13 | Nitto Denko Corporation | Wired circuit board |
US8760815B2 (en) | 2007-05-10 | 2014-06-24 | Nitto Denko Corporation | Wired circuit board |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61180571A (en) * | 1985-02-06 | 1986-08-13 | Matsushita Electric Ind Co Ltd | Semiconductor insulator |
-
1990
- 1990-03-23 JP JP7430590A patent/JPH03274799A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61180571A (en) * | 1985-02-06 | 1986-08-13 | Matsushita Electric Ind Co Ltd | Semiconductor insulator |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05304345A (en) * | 1992-04-27 | 1993-11-16 | Sanken Electric Co Ltd | Metallic wiring board and its production |
US8134080B2 (en) | 2005-07-07 | 2012-03-13 | Nitto Denko Corporation | Wired circuit board |
US7638873B2 (en) | 2005-12-01 | 2009-12-29 | Nitto Denko Corporation | Wired circuit board |
US7723617B2 (en) | 2006-08-30 | 2010-05-25 | Nitto Denko Corporation | Wired circuit board and production method thereof |
US8266794B2 (en) | 2006-08-30 | 2012-09-18 | Nitto Denko Corporation | Method of producing a wired circuit board |
US8760815B2 (en) | 2007-05-10 | 2014-06-24 | Nitto Denko Corporation | Wired circuit board |
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