JPH0327478A - Arithmetic circuit - Google Patents

Abstract

PURPOSE:To make it possible to process two or more processing at a time by providing a distributing means which is provided with inputs connected respectively to the outputs of a multiplying part to obtain the result of the multiplication of digital data by a numerical value and leads these inputs to the optional one or plural outputs and an integrating means which integrates numerically the outputs of the distributing means into plural systems. CONSTITUTION:A selector 20 is provided with N input terminals which is the same as the number of the groups of the multiplication of the multiplying part 10, and is provided with output terminals whose number is N which is equal to the number of the input terminals or N' which is greater than N, and leads the multiplied result inputted to each input terminal to the optional output terminal or distributes it to the optional plural output terminals. A first and a second integrating parts 30, 40 are provided with N or N' input terminals of the same number as the number of the output terminals of the selector 20, and integrate the multiplied result led to the input terminal as executing addition, subtration or other calculation to it. Thus, this circuit can be applied to extensive image processing, and the image processing system of high processing speed and high cost performance can be constructed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic circuit, and particularly to an arithmetic circuit useful for real-time video processing and display, real-time image analysis, etc. in a digital video processing system.

[Conventional technology]

Conventionally, digital processing systems have often been used, for example, in image processing systems that recognize images based on features extracted from an input image, due to the sophistication, reproducibility, quantitative nature of the processing results, and the diversity of processing. . In this digital processing system, it is necessary to treat the video as a collection of pixels, and the calculations regarding the pixels become enormous. For example, in order to measure the particle size distribution of 512 x 512 pixels with 8 bits each for RGB, the processing speed is 20 MIPS.
Even if the calculations were performed using a very large computer, the processing time would be several seconds, which is not fast enough for real-time processing. Therefore, although there have been attempts to speed up video processing using a dedicated IC for image processing, the purpose of this dedicated IC is extremely narrow and cannot be applied to a wide range of video processing.

Therefore, when a video processing system is constructed using these dedicated ICs, the applications are limited and the cost performance is generally low.

[Problem to be solved by the invention]

The present invention was devised to solve these conventional problems, and provides a video processing system that can be applied to a wide range of video processing, is capable of faster processing than a general-purpose ultra-large computer, and has high cost performance. The purpose is to provide an arithmetic circuit for constructing.

[Means to solve the problem]

The arithmetic circuit according to the present invention has a multiplication section into which a plurality of digital data is input and obtains the result of multiplying these digital data by a numerical value, and inputs respectively connected to the outputs of this multiplication section. The present invention is characterized in that it includes a distribution means that can lead the output to one or more arbitrary outputs, and an integration section that numerically integrates the output of the distribution means into a plurality of systems.

〔Example〕

The present invention will be explained below based on illustrated embodiments.

In FIG. 1, the arithmetic circuit includes a multiplier 10 and a selector 20.
, the first and second integration sections 30 and 40 are connected in sequence, and the multiplication section 10 and the selector 20 are branched, and the state calculation section 50 is connected.

N pieces of data (D.) are input to the multiplier 10,
The multiplier 10 multiplies each of these pixel data by an appropriate numerical value (A,) and calculates the result, for example, Di=A. XDi
The calculation result is output to the same number of output terminals as the human input terminals. Here, the multiplication result in the multiplication unit 10 does not necessarily need to be obtained by performing multiplication, but can also be obtained by storing the multiplication result in a ROM or the like in advance and reading out the value.

The selector 20 has the same number of N input terminals as the multiplication sets of the multiplier 10, and the number of output terminals thereof is the same as the number of human input terminals, or more than N'. selector 20
can direct the multiplication results input to each input terminal to any output terminal or distribute them to any plurality of output terminals.

The first and second integrating sections 30 and 40 have N or N'' input terminals, which is the same number as the output terminals of the selector 20,
The multiplication results led to the manual terminal are integrated while performing 3-4 addition, subtraction, and other operations.

Multiplication section 10, selector 20, first and second integration section 3
0 and 40, a numerical calculation unit is configured, and this numerical calculation unit performs density averaging, first-order differentiation, second-order differentiation, filter processing, and the like.

On the other hand, the state calculation unit 50 performs various processing on the output of the multiplication unit 10, and calculates the number of connections, an index of whether the pixel is a processing target, and parameters T, F, and D for determining the Euler number.
, E, calculate a converged signal, etc. representing the state of the processed pixel and its vicinity.

The outputs of the first and second integration sections 30 and 40 and the state calculation section 50 are guided to selectors 60 and 65.

Conversion sections 70 and 75 are connected to the selector 60, and a memory 80 is connected to the selector 65.

The selector 60 includes the state calculation unit 50 and the second integration unit 4
The output of 0 is selectively guided to converters 70 and 75. Conversion section 7
0 and 75 are constructed by connecting a light arithmetic unit to the output of a memory consisting of a static RAM or a dynamic RAM, and returning the output of this light arithmetic unit to the input of the memory.

These conversion units 70 and 75 are capable of performing various processes such as data integration, data gradual reduction, and data successive comparison. Outputs a density histogram based on the input value.

The selector 65 includes the state calculation unit 50 and the first integration unit 3
0 output is selectively routed to memory 80.

The memory 80 stores the output results of the state calculation section 50 and the first integration section 30, and stores, for example, the differential value output from the first integration section 30.

FIG. 2 shows the multiplier 10, selector 20, first and second
This figure shows the structure of the integrating sections 30 and 40 in detail. This embodiment is configured to process 3×3 pixel data, and nine multipliers 10 are provided corresponding to each pixel data. The output of each multiplication section 10 is guided to two selectors 20 and selectively sent to the first or second integration section 3.
0 and 40 are input. Each of the integration units 30 and 40 is constructed by connecting a plurality of arithmetic circuits (four shown in the figure) in series. The arithmetic circuit numerically integrates the 51-61 input data while performing arithmetic operations such as addition, and the number of output terminals of the arithmetic circuit decreases as the distance from the selector 20 increases.

Next, as an example of the operation of this embodiment, a process of calculating a differential value while obtaining a histogram of pixel density will be described.

Center pixel data (indicating density) manually input to the multiplication unit 10
is multiplied by l in the multiplier 10, inputted manually to the second integration unit 40, and guided directly to the conversion unit 75. The conversion unit 75 integrates the number of pixels for each density and obtains a histogram. In addition, the pixel data around the center pixel manually entered into the multiplication section 10 is multiplied by a predetermined coefficient in the multiplication section 10 and inputted to the first integration section 30, where it is added and integrated in each arithmetic circuit to obtain a differential value. is required. This differential value is stored in memory 80.

As a result, a histogram and a differential value are obtained simultaneously for the same pixel data, improving the calculation processing speed.

Generally, a circuit for multiplication has a large number of gates, and it is desirable to have a small number of multiplication circuits, but as in this embodiment, the number of multiplication circuits, that is, the number of inputs, is set to a minimum value equal to the number of parameters. Therefore, the circuit structure is the minimum for a given number of parameters.

The calculations in the integration units 30 and 40 are performed hierarchically, and different calculations are performed simultaneously in each layer and are passed to the next stage in a pipeline process. By employing this pipeline processing, the calculation speed of the entire calculation circuit is significantly improved.

Furthermore, in this embodiment, multiplication is performed first and the result is guided or distributed to any input terminal of the integration section, so high gate efficiency is achieved, and the circuit itself is extremely Due to its simple structure, its expansion,
Improvement is also easy.

Note that the input pixel data is not limited to data in 8 neighborhoods of 3×3, and the present invention is effective for 2×2 pixels in 4 neighborhoods, fewer pixels, or more pixels than 8 neighborhoods. In particular, as the number of raw data increases, its effectiveness becomes more pronounced.

Furthermore, although the arithmetic circuit has been described as processing pixel data in the above embodiment, it is not limited to pixel data, and the present invention can be applied to all digital data processing systems.

〔Effect of the invention〕

As described above, the present invention has a circuit structure with high gate efficiency and high flexibility and expandability of the circuit structure,
Furthermore, an arithmetic circuit capable of simultaneously performing two or more processes can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an arithmetic circuit according to the present invention, and FIG. 2 is a block diagram showing the structure of a numerical calculation section. 10...Multiplication unit 20...Selector 30...First integration unit 40...Second integration unit 9

Claims (1)

[Claims] (1) A multiplier that receives a plurality of digital data and calculates the result of multiplying these digital data by a numerical value, and has inputs connected to the outputs of this multiplier, and allows any one of these inputs to be connected to the output of the multiplier. Or an arithmetic circuit comprising a distribution means that can lead to a plurality of outputs, and an integration section that numerically integrates the output of the distribution means into a plurality of systems.