JPH03274746A - Multi-chamber device - Google Patents

Abstract

PURPOSE:To execute a large number of treatment without widening an occupying area by installing a structure section in which a plurality of chambers or a plurality of treating sections are arranged in different height. CONSTITUTION:In a multi-chamber device, process chambers 8 are connected to each of the three side faces of a transfer chamber 5 having a approximately square-shaped plane shape through six gate valves 4 in total at every two stage vertically, and a load lock chamber 1 is mounted on residual one side face. Cryopumps 10 conducting discharge to upper sections are set up to the process chambers at an upper stage and a cryopump 10 performing discharge to a lower section to the process pump at a lower stage respectively in each process chamber 8, 8,.... A wafer transfer mechanism 9 can lift and lower an arm 6 and a fork 7 as a whole so as to be able to transfer semiconductor wafers 3 among the chambers 8 at the upper stage and the chamber 8 at the lower stage. Accordingly, the kinds of treatment or throughput capable of being conducted by the multi-chamber device can be increased without approximately widening the occupied area.

Description

[Detailed description of the invention] The present invention will be described in the following order.

A. Industrial field of application B0 Overview of the invention C3 Prior art [Fig. 13] D. Problems to be solved by the invention E4 Means for solving the problems 10 Effects G. Examples [Figs. 12 Figure 2 First embodiment [Figures 1 and 2] b, Second embodiment [Figures 3 to 5] C9 Third embodiment [Figure 6] d, Fourth embodiment Embodiment [Figures 7 to 10] e, Fifth embodiment [Figure 11] f, Sixth embodiment [Figure 12] H1 Effects of the invention (A, industrial application field) The present invention The present invention relates to a multi-chamber apparatus, that is, a multi-chamber apparatus capable of performing a plurality of types of processing on a wafer by moving the wafer between different chambers without exposing the wafer to the atmosphere.

(B. Summary of the Invention) The present invention provides a multi-chamber device in which multiple chambers or multiple processing sections are arranged at different heights in order to be able to perform many treatments without increasing the occupied area. In addition, in order to improve throughput, multiple chambers should be installed for time-consuming processing. , or alternatively, divide multiple chambers into multiple groups,
A transfer chamber is interposed between the different groups, or a wafer transfer mechanism with a wafer reversal function is provided.

(C, Prior Art) [Figure 13] For semiconductor manufacturing process technology to meet the demands for miniaturization and higher precision of semiconductor elements, it is necessary to complete the process in one chamber and move on to the process in another chamber. It is necessary to prevent deterioration of the surface portion of the semiconductor substrate. However, in actual processes, when a process (e.g. etching) is completed in one chamber and the next process (e.g. CVD) is performed in another chamber, the semiconductor wafer is exposed to the atmosphere, so for example, through-holes in the wiring film are exposed. A problem arises in that a natural oxide film is formed on the exposed portion. Since the presence of such a native oxide film causes an increase in contact resistance, it is often necessary to remove it. The natural oxide film is removed by dipping the semiconductor wafer in an etching solution.
Furthermore, it is necessary to wash the etching solution with water, which causes a significant increase in the number of steps and reduces the throughput.

Therefore, multi-chamber devices that integrate multiple chambers via gate valves have been developed, such as the NIKKEI MICRO DEVICES 19
It is introduced in the October 1989 issue, pages 34-39.

FIGS. 13(A) and 13(B) show an example of such a multi-chamber device, with FIG. 13(A) being a plan view and FIG.
) is a cross-sectional view.

In the drawings, reference numeral 1 denotes a load lock chamber, which is a chamber in which a semiconductor wafer 3 to be processed is placed on standby. 2 is a wafer cassette that stores the semiconductor wafer 3; The load lock chamber 1 has a gate valve 4
It is connected to the transfer chamber 5 via. Reference numeral 6 denotes a transfer arm provided in the transfer chamber 5, which uses a fork 7 to transfer the semiconductor wafer 3 between the load lock chamber 1 and the process chambers 8, 8, . 9 is a wafer transport mechanism that drives the transport arm 6, 10° 10...
- Transfer chamber 5 and each process chamber 8.8, -
It is a vacuum pump installed in...

According to such a multi-chamber apparatus, the semiconductor wafer 3 that has completed one process in one chamber can be moved to another chamber through a gate valve to perform the next process without being exposed to the atmosphere. That is, processes on two sides can be performed continuously without exposing the semiconductor wafer 3 to the atmosphere. It can be said that it is excellent in that respect.

(D. Problems to be Solved by the Invention) However, multi-chamber devices generally have the following problems.

First, the multi-chamber device has a problem in that the occupied area of the multi-chamber device becomes large because a plurality of chambers are arranged and integrated only in the plane direction.

Furthermore, although a multi-chamber device generally requires at least one transfer chamber 5, the proportion of the area occupied by the transfer chamber 5 in the multi-chamber device is so large that it cannot be ignored. Therefore, it has been difficult to increase the ratio of the area occupied by the multi-chamber device to the amount of work that the multi-chamber device can do (this is related to the utilization rate for effectively utilizing the area of the factory).

Furthermore, it is difficult to say that the conventional multi-chamber apparatus has been sufficiently designed to further improve throughput. This point will be explained as follows.

First, the time required for processing in each chamber of a multi-chamber device is not uniform, and the average speed of semiconductor wafers flowing through a multi-chamber device is determined by the speed of the slowest process (this is called "rate-limiting"). As a result, it becomes extremely difficult to improve throughput.

Second, in multi-chamber devices, there is generally a rule that multiple gate valves 4 between the transfer chamber 5 and the process chambers 8, 8, etc. are not opened at the same time, which improves throughput. It becomes a hindering factor. This is because, in order to completely prevent cross-contamination between the chambers 5, 8, 8, . . . , it is necessary to prevent two or more gate valves 4 from being opened at the same time. However, some process chambers 8.8 may communicate with each other without any cross-contamination. Nevertheless, two gate valves 4 can be operated at the same time in the entire multi-chamber device.
Because the rule of not opening more than 300 mm had to be followed, improvements in throughput were hindered.

Thirdly, since many of the processes performed in the process chamber 8 are carried out with the semiconductor wafer in a face-up state, it is preferable that the semiconductor wafer 3 is transported in a face-up state even in a multi-chamber device. Commonly, however, some processes are performed face-down, such as selective CVD of tungsten. Therefore, when performing face-down processing such as selective CVD of tungsten in some process chambers 8 of a multi-chamber apparatus, only the semiconductor wafer 3 is inverted between the process chamber 8 and the transfer chamber 5. A chamber, an inversion chamber, had to be provided. Therefore, when transferring a semiconductor wafer from a transfer chamber to its process chamber, the semiconductor wafer is transferred from the transfer chamber to an inversion chamber, inverted in the inversion chamber, and then transferred from the inversion chamber to the process chamber. It had to be done. Also,
The same was true when returning from the process chamber to the transfer chamber.

Therefore, the time required for transportation has become so long that it cannot be ignored. This was also a factor that hindered the improvement of throughput. Furthermore, since an inversion chamber is required, this also increases the area occupied by the multi-chamber device.

The present invention has been made to solve these problems, and enables processing of many types and amounts without unnecessarily increasing the occupied area of a multi-chamber device, and also enables throughput. The purpose is to improve the

(E. Means for Solving Problems) A first multi-chamber device of the present invention is characterized by having a structural part in which a plurality of chambers or processing sections are arranged at different heights.

A second multi-chamber device of the present invention is characterized in that a plurality of sets of a plurality of chambers are provided for performing continuous processing.

A third multi-chamber device of the present invention is characterized by having a plurality of chambers for performing time-consuming processing.

A fourth multi-chamber device of the present invention is characterized in that a plurality of chambers are divided into a plurality of groups, and a transfer chamber is interposed between the groups.

A fifth multi-chamber apparatus of the present invention is characterized by having a wafer transport mechanism having a wafer reversing function capable of reversing a wafer.

(F. Effect) According to the first multi-chamber device of the present invention, chambers stacked vertically or chambers in which processing sections are arranged at different heights can be operated with almost no increase in occupied area. The types of processing that can be performed or the amount of processing that can be performed can be increased.

Therefore, it is possible to increase the types and amounts of processing without increasing the area occupied by the multi-chamber device.

According to the second aspect of the multi-chamber apparatus of the present invention, a plurality of sets of a plurality of chambers for performing a series of processes are provided;
One transfer chamber can be shared by multiple sets. Therefore, the ratio of the area occupied by the multi-chamber device to the work that can be done by the entire multi-chamber device can be reduced.

This leads to effective use of IC manufacturing plants that cannot be allowed to go to waste.

According to the third multi-chamber apparatus of the present invention, since there are a plurality of chambers for performing time-consuming processing, the time-consuming processing can be performed simultaneously on different semiconductor wafers in the plurality of chambers. This makes it possible to improve the throughput of the entire multi-chamber device. For example, if there is a process that takes more than twice as long as other processes, by setting the number of chambers for that process to two, for example, the process will not become a factor in lowering the throughput of the multi-chamber device. In other words, it is no longer rate-limiting.

According to the fourth multi-chamber device of the present invention, if chambers that do not cause mutual contamination are grouped together, there is no risk of mutual contamination between the chambers within each group, so the gate valve is Multiple openings are allowed at the same time. Therefore, throughput can be improved.

According to the fifth multi-chamber device of the present invention, since the wafer transport mechanism can reverse and transport the semiconductor wafer,
The semiconductor wafer can be directly inverted and transferred from the transfer chamber to a target process chamber without interposing an inversion chamber between the transfer chamber and the process chamber.

(G. Embodiment) [FIGS. 1 to 12] The multi-chamber apparatus of the present invention will be explained in detail according to the illustrated embodiment.

(a, 1st embodiment) [Fig. 1, Fig. 2] Fig. 1 (A)
, (B) show the first embodiment of the multi-chamber device of the present invention, (A) is a plan cross-sectional view, and (B) is a cross-sectional plan view.
is a vertical sectional view.

In this multi-chamber device, a total of six process chambers 8 are connected to each of three sides of a transfer chamber 5, which has a substantially square planar shape, through gate valves 4, with two stages above and below.
A load lock chamber l is provided on the remaining side. Among the process chambers 8, 8, . . . , the upper stage is provided with a cryopump 10 for evacuation upward, and the lower stage is provided with a cryopump 10 for evacuation downward.

The wafer transport mechanism 9 is capable of raising and lowering the arm 6 and fork 7 as a whole so that the semiconductor wafer 3 can be transported between the upper chamber 8 and the lower chamber 8.

According to such a multi-chamber device, the number of process chambers 8 can be increased without increasing the occupied area. Furthermore, if the number of process chambers 8 is the same, the area occupied by the multi-chamber device can be reduced.

FIGS. 2(A) and 2(B) show a modification of the multi-chamber device shown in FIG.
B) is a longitudinal sectional view.

This multi-chamber device includes the multi-chamber device shown in FIG. 1 and each chamber l, 5.8.8. ... have the same arrangement, but it has two wafer transport mechanisms 9 that can be raised and lowered, and the semiconductor wafer 3 can be transported using the two transport mechanisms 9.9. The difference is that the throughput can be further improved.

(b, Second embodiment) [Figures 3 to 5 1 Figure 3 (A
) to (C) show a second embodiment of the multi-chamber device of the present invention, where (A) is a longitudinal sectional view of the multi-chamber device, (B) is a plan view, and (C) is a plan view of the multi-chamber device. is the same figure (A)
FIG. 2 is a sectional view taken along line CC of FIG.

This multi-chamber device performs three types of sputtering in one chamber 8a, where Lla is a sputtering cathode that sputters titanium, llb is a sputtering cathode that sputters aluminum, and llc is a sputtering cathode that sputters titanium. Sputter cathode, ll
b is located higher than 11a and llc.

Reference numeral 12 denotes a disk-shaped holder plate, which has wafer holding holes 13, 13, 13, and 13 formed at four locations, and its center portion is fixed to the rotating shaft of a motor 14, and is rotated by the motor 14 to hold the semiconductor wafer 3. 3. 3 and 3 are sequentially located at locations corresponding to each sputtering cathode 11a, llb, and llc. Note that the lowest part of the chamber 8a is used as a place where the semiconductor wafer 3 is transferred between the holder plate 12 and the transfer chamber 5.

According to this multi-chamber apparatus, 1. Sputtering can be performed separately at three locations within one process chamber 8a. Furthermore, since the locations where sputtering is performed are arranged three-dimensionally, the types of processing and the amount of processing can be increased without significantly increasing the area occupied by the multi-chamber device.

In addition, the semiconductor wafer can be transferred from one sputtering location to the next by simply rotating the motor 14 by 90 degrees, thereby making it possible to improve the throughput.

In addition, in this multi-chamber apparatus, each sputter cathode lla~ every time the holder plate 12 rotates 90 degrees.
It is also possible to adopt a configuration in which each llc is isolated from other parts and placed in a sealed state.

4(A) and 4(B) show a modification of the multi-chamber device shown in FIG. 3, with FIG. 4(A) being a perspective view of the multi-chamber device, and FIG. 4(B) showing sputtering. FIG. 3 is an enlarged perspective view showing a wafer holder in the process chamber.

In this multi-chamber apparatus, when a semiconductor wafer 3 is transferred from a load chamber (not shown) to a transfer chamber 5 through a gate valve 4, processing is performed in each process chamber 8, 8, . has a plurality of sputtering cathodes lla to lie, and sputtering can be performed simultaneously at each part. And process chamber 8a
An octagonal column-shaped wafer holder 15 is arranged at the center of the wafer holder 15 . 16 is a rotation shaft for rotating the wafer holder 15.

The wafer holder 15 has semiconductor wafers 3 on each side thereof.
3, . . . can be held so that each semiconductor wafer 3° 3, .

According to such a multi-chamber device, the types of processing can be increased without unnecessarily increasing the area occupied by the device, and throughput can be improved.

A detailed explanation of the aspect of improving throughput is as follows.

It is necessary to provide a barrier metal to prevent mutual sintering between AI2 and the silicon substrate.
j2 (500nm)/TiN (100nm)/Ti
There is a need to form a film with a multilayer structure (50 nm) by sputtering. In this case, for %AI2, if we leave the Ar gas flowing and start the film formation process immediately, the Ar gas is 0.4 Pa and the power is about 12
W/cm'', the rate is 15 nm/sec, and an A4 film with a thickness of 500 nm can be formed in about 33 seconds.Also, even if the substrate is heated, the rate is 15 nm/sec.
It only takes about 0 seconds extra time.

However, when forming TiN111, N2゜02
In the case of the reactive sputtering method using gas, conventional multi-chamber equipment requires exhausting the Nx and Ox gases after each sputtering process before transporting them, in order to prevent negative effects on the chambers for forming An and Ti films. There is a need to do. Therefore, after setting the semiconductor wafer in the process chamber, Art N
Introduce a gas such as Ox, Ox, etc., stabilize it for about 20 seconds, and then set the gas pressure to 0.5 Pa and the power to about 6 W/
If sputtering is performed under conditions of 1 nm7, the rate will be 1 nm7.
It takes about 100 seconds to form 1100 nm of TiN. Furthermore, it is necessary to stop the gas introduction and exhaust the gas, which takes about 30 seconds. Therefore, if it takes about 150 seconds to form a TiN film and heats for 10 seconds before and after film formation,
It will take 60 seconds.

Furthermore, in order to reduce the number of chambers used, the first layer of Ti film (50 nm) and the second layer of TfNIl! (10
0 nm) in the same process chamber, the following sequences (1) to (6) will be obtained. In addition, Ti has a power of about 3 W/c in Ar gas 014 Pa.
sputtering under conditions of 2 nm/sec.
Suppose that

(1) Ar gas introduction (20 seconds), (2) Ti film 50 nm
Formation (25 seconds), (3) Ar gas exhaust (30 seconds), (4
) Ar, N-, 02 gas introduction (20 seconds), (5) TiN
Formation of film 1100n (100 seconds), (6) Ar, N-, O
x gas exhaust (30 seconds) Therefore, even if heating is not performed before and after film formation, the
It takes seconds. Therefore, the manufacturer's nominal value of 40 to 50 s/hr of throughput per 1 μm of An for a multi-chamber device using chamber ]II for An film formation is also the same as the Aj2 (500 n
In the case of a structure of (m)/TiN (100n)/Ti (50nm), if A, 9, TiN, and Ti are formed in separate chambers, the actual speed can be said to be only 20 to 25 s/hr at most. This is because the throughput of a multi-chamber device is determined by the most time-consuming rate-limiting process.

However, according to a multi-chamber device as shown in FIG. 4 (or a multi-chamber device as shown in FIG. 3), a plurality of semiconductor wafers 3.3, . Since sputtering can be performed by the sputtering cathodes 11a-lie, throughput can be significantly improved.

FIG. 5 is a perspective view showing another example of a chamber for performing sputtering. In this chamber, the rotation shaft 16 of the octagonal prism-shaped wafer holder 15 is connected to the partition wall 5a between the chamber 8a and the transfer chamber 5.
The rotation axis 16 of the wafer holder 15 may be set parallel to the partition wall 5a as in the multi-chamber apparatus shown in FIG. 4, but in the present process chamber shown in FIG. You can also make it vertical like this.

In addition, illustration of the rotational drive mechanism for rotating the wafer holder 15 is omitted in FIGS. 4 and 5.

(c, Third Embodiment) [FIG. 6] FIG. 6 is a plan sectional view showing a third embodiment of the multi-chamber apparatus of the present invention. In this figure, gate valves and other parts that are not related to the characteristics of this multi-chamber apparatus are omitted, and only the characteristic parts are shown schematically. Process chambers 8A, 8B,
It has two sets of 8C combinations, and these two sets have six chambers 8.
A, 8B, 8C 18A, 8B, 8C share one transfer chamber 5 and one load and load chamber 17. The broken line shows the flow of the semiconductor wafer 3.

8A and 8A are process chambers that perform Ti sputtering, 8B and 8B are process chambers that perform TiN sputtering, and 8C18C is a process chamber that performs AJ2Si sputtering. The steps consisting of the three treatments A, B, and C can be performed simultaneously through two routes indicated by broken lines. That is, this multi-chamber device performs the functions of two multi-chamber devices each consisting of three process chambers 8. However, only one transfer chamber 5, one wafer transfer mechanism therein, and one load-and-load chamber 17 are required.

Therefore, the area occupied can be reduced compared to the amount of work that can be done by a multi-chamber device, and the required energy can also be reduced.

In addition, when performing maintenance such as replacing a target on one process chamber, for example, the process chamber 8A on the left side in FIG. It can be shared to form a film. Therefore, the degree of freedom in responding to trouble is increased, and even if trouble occurs, there is no need to significantly lower the throughput of the multi-chamber device.

The technical idea of having multiple process chamber combinations that sequentially perform a series of processes consisting of multiple processes is not limited to multi-chamber equipment that performs sputtering, but can also be applied to other series of processes such as CVD and dry etching. Needless to say, the method can also be applied to a multi-chamber device that performs.

(d, Fourth Embodiment) [FIGS. 7 to 10] FIG. 7 is a plan sectional view showing a fourth embodiment of the multi-chamber apparatus of the present invention.

In the same figure, 1 is a load chamber, 8A, 8A is a Ti/Ti
A process chamber for forming an N/Ti film by sputtering; 8B is a process chamber for forming an A11 film; 8C is a process chamber for forming a Ti film.
A process chamber for forming an N film, 18 a load chamber, 1
9A is a target set in the process chamber 8A, 19B is a target set in the process chamber 8B, and 19c is a target set in the process chamber 9C.

This multi-chamber apparatus is characterized in that it has two process chambers 8A for forming Ti/TiN/Ti films by sputtering. The reason why there are two process chambers 8A is that Ti/T i N/T i is performed there.
The time required to form a film is different from that of other process chambers 8B and 8
This is because the time required for forming an A11 film and a TiN film using C is more than twice as long. In other words, the process chamber 8A is the rate-limiting chamber.

That is, when forming AfflI, for example, a Ti/TiN/Ti film is required as a barrier metal as a lower layer film to prevent mutual sintering with the silicon semiconductor substrate. Further, as an upper layer film, a TiN film, for example, is required as an antireflection film that prevents reflection during exposure. When forming a Ti/TiN/Ti film by sputtering, it takes about 140 seconds. The breakdown is: Ar
10 seconds for gas introduction and stabilization, 15 seconds for Ti film (50 nm) formation, 10 seconds for N2.0□ gas introduction stabilization, TiN
It takes 60 seconds to form a film (100 nm), 10 seconds to exhaust Nz and Os gases, 15 seconds to form a Ti film (50 nm), and 20 seconds to exhaust Ar gas.

On the other hand, when forming an A12 film, it is sufficient to allow the Ar gas to flow, and the time required to form an A11 film of 500 nm is about 30 seconds. If Ar gas is introduced (10 seconds),
Even if exhaustion (20 seconds) is performed, it will take 660 seconds.

In addition, when forming a TiN film, Ar, Nz, and O2 gases are introduced and stabilized for 10 seconds, and for forming a TiN film (20 nm), it is 10 seconds.
It takes 2 seconds, 20 seconds to exhaust the gas, and 42 seconds.

Therefore, if there is only one process chamber 8A for forming a Ti/TiN/Ti film, the process chamber 8A
becomes a rate-limiting chamber and determines the throughput of the multi-chamber apparatus, and the waiting time (idle time) of the other process chambers 8B and 8C becomes longer.

Therefore, in this multi-chamber apparatus, two transfer chambers 8A are provided, and Ti/TiN/Ti films are formed simultaneously in the two transfer chambers 8A and 8A, so that the waiting time of the other process chambers 8B and 8C is reduced. becomes shorter,
Throughput can be improved. That is, some of the semiconductor wafers (not shown) in the load chamber 1 are -
The other one is sent to one process chamber 8A and sputtered there, and the other one is sent to the other process chamber 8A and sputtered there. And process chambers 8A, 8
Everything that has been sputtered in A is placed in process chamber 8.
B, the sputtering is performed in sequence in the process chamber 8C and sent to the unloading chamber 18. The dashed line indicates the flow of semiconductor wafers.

FIG. 8 shows a modification of the multi-chamber device shown in FIG. 7.

The multi-chamber device shown in Fig. 7 is a one-way type multi-chamber device to which the present invention is applied, whereas the present multi-chamber device has a transfer chamber in the center and process chambers arranged around it. The present invention is applied to a random access type multi-chamber device.1. They are different in that respect, but they are similar in other respects. That is, only the number of process chambers 8A that determines the rate is two, and the other process chambers 8B and 8C are one each.

In FIGS. 7 and 8, parts not related to the features of the multi-chamber apparatus, such as the wafer transfer mechanism and vacuum pump, are omitted.

The technical idea of increasing the number of rate-determining process chambers present in the multi-chamber apparatus of this embodiment is applicable only to the multi-chamber apparatus for forming the TiN/Aβ/T i /TiN/Ti laminated film. Not CVD
The present invention can also be applied to a multi-chamber apparatus that performs a series of other processes such as etching, dry etching, etc. That is, the present invention can be applied to any multi-chamber device having a rate-determining process chamber.

FIGS. 9 and 10 illustrate still another modification, with FIG. 9 being a plan sectional view and FIGS. 10(A) to 10(H) being process sequence diagrams.

This multi-chamber apparatus is designed to perform both a series of processes including a rate-limiting process and a series of processes not including a rate-limiting process.

In the figure, 17 is a load-unload chamber, 8a is a process chamber for plasma etching, and the etching time is 1 minute, and 8b is W (tungsten).
In a process chamber where selective CVD is performed, the selective CVD
The time required for D is 5 minutes, 8c is a process chamber for sputtering a Ti/TiN/Ti multilayer film, and the time required for that sputtering is 50 seconds, 8d is a process chamber for forming Aβ5ili in a standby, and for that sputtering. The time required is 40 seconds. 5 is a transfer chamber located in the center surrounded by these process chambers 88 to 8d and the load/unload chamber 17. In addition, FIG. 9 and FIGS. 10 (A) to (H) which are process sequence diagrams
In this figure, parts not directly related to the features of the multi-chamber apparatus, such as gate valves and wafer transfer mechanisms, have been omitted.

This multi-chamber device performs two types of processing.

The first series of treatments includes (1) etching (pretreatment) in the process chamber 8a, (2) selective CVD of W in the process chamber 8b.
, (3) Ti/TiN/ in the process chamber 8c
Sputtering of a Ti laminated film; and (4) sputtering of AβSi in the process chamber 8d.

Further, the second series of treatments includes (1) etching (pretreatment) in the process chamber 8a, (2) Ti/TiN/etching in the process chamber 8C.
(3) sputtering of Ti laminated film; and (3) sputtering of AnSi in the process chamber 8d.

FIG. 9 shows the process sequence in this case, and 38.3□, . . . are the semiconductor wafers supplied to the load-and-load chamber 17, and the small numbers 1.2, . . . . indicates the order in which the semiconductor wafers 3 are supplied to the load-and-load chamber 17. And the first
th, 6th, 11th, etc. semiconductor wafer 3
．． ．． 3. ．． 3. ,.

. . . In other words, every fifth semiconductor wafer is supplied to undergo the first series of processing, and the other wafers 3□, 3. ．． 3. ．． 3. ．． 3. ．． 3. .

3e, 3+. , 3□, 3°, 31.34.31? ,...
・Provide one that performs the second series of processing.

Then, each chamber 88 to 8d is mostly idle (waiting).
If you don't have the time, you can increase the amount of work you can do with a multi-chamber device.

If you ignore the transfer time by the arm, every 5th sheet will be
It is calculated that it is sufficient to supply semiconductor wafers 3 for a series of processing, but considering the transportation time, the first
It seems that it would be sufficient to supply the semiconductor wafers 3 for the first series of processes, and then supply the remaining semiconductor wafers 3 for the second series of processes.

In addition, in practical use, it is preferable to strictly calculate two types of processing sequences that can operate the multi-chamber apparatus most efficiently using a computer, and to control each part of the multi-chamber apparatus based on the results.

(e, Fifth Embodiment) [FIG. 11] FIG. 11 is a plan sectional view showing a fifth embodiment of the multi-chamber apparatus of the present invention.

In the figure, 8al is a process chamber that performs lamp annealing, 1 is a load lock chamber 58a2 is Afl
Process chambers for sputtering, these include gate valves 4.4.4 on three sides of the second transfer chamber 5a.
The process chambers 8al and 8a2, which are connected to the side surface of the first transfer chamber 5b via a gate valve 4.4, form a first group. This is because both Aj2 sputtering and lamp annealing are performed using an Ar-based inert gas, so there is no possibility of mutual contamination.

5b is the third transfer chamber, and the first transfer chamber 5a
and is connected at one side via a gate valve 4ab. 8bl, 8b2, and 8b3 are process chambers forming the second group. 8bl is a process chamber for dry etching, 8b2 is a process chamber for interlayer insulating film CVD, and 8b3 is a metal CVD process chamber.
It is a process chamber in which the gate valve 4.
4.4 to the three sides of the second transfer chamber 5b.

The reason why 8bl, 8b2, and 8b3 constitute the second group is because they all use fluorine-based gas, and there is no risk of mutual contamination between them.

However, there is a possibility of mutual contamination between the first group of process chambers 8a and the second group of process chambers 8b because the gases used are completely different.

In the case of transporting within the first group, that is, between the process chambers 8al and 8e2, and the second
in the group of process chambers 8bl,
When transporting between 8b2 and 8b3, gate valve 4
It is allowed to have multiple open at the same time. In other words, the rule that multiple gate valves 4.4 must not be opened at the same time does not need to be applied within the group. Therefore,
The time required for transporting semiconductor wafers is greatly reduced.

Note that the gate valve 4ab existing between the first group and the second group is subject to the rule that it does not open when the other gate valves 4.4, . . . are open.
Opening and closing are strictly performed.

(f, Sixth Embodiment) [FIG. 12] FIG. 12 is a longitudinal sectional view showing a wafer transport mechanism which is a main part of a sixth embodiment of the multi-chamber apparatus of the present invention.

In the figure, 5 is a transfer chamber, and 6 is a transfer arm that transfers the semiconductor wafer 3 by expanding and contracting, and is configured to be able to rotate around an expansion and contraction axis. 7
A is a wafer holder attached to the tip of the transfer arm 6, and is provided with a bin 20 for fixing the held semiconductor wafer 3 so that it does not fall. Note that the semiconductor wafer 3 may be held by an electrostatic chuck.

8 is a process chamber in which selective CVD of W is performed, and has a reaction electrode 21 on the lower side. Since selective CVD cannot be performed unless the semiconductor wafer 3 is placed on the reaction electrode 21, the semiconductor wafer 3 must be placed face down in the process chamber 8.

4a is a vacuum valve disposed between the process chamber 8 and the transfer chamber 5.

Processing is generally performed with the semiconductor wafer 3 face up, but may also be performed with the semiconductor wafer 3 face down. Therefore, in this multi-chamber apparatus, the wafer transport mechanism is provided with the function of reversing the semiconductor wafer 3.

Here, a method of transporting a semiconductor wafer will be explained.

First, after evacuating a load rotor chamber (not shown), the semiconductor wafer 3 is placed on the wafer holder 7a of the transfer arm 6.
Posted face-up. Then, the semiconductor wafer 3 is fixed by the bin 20.

Next, within the transfer chamber 5, the transfer arm 6
Once the paper rotates, the semiconductor wafer 3, which was facing upward, now faces downward. In this state, the arm 6 is extended and the wafer holder 7a enters the process chamber s and is positioned above the reaction electrode 21.

Next, the fixing bottle 20 is removed and the semiconductor wafer 3 is placed on the reaction electrode 21. Then, the arm 6 is contracted and is housed within the transfer chamber 5.

Next, the vacuum valve 4a is closed, and selective CVD of W is started within the process chamber 8.

When the W selection CVD is completed, the semiconductor wafer 3 is accommodated face down in the transfer chamber 5 by the arm 6. Thereafter, the semiconductor wafer 3 is transferred to another chamber (not shown), but if the process in that chamber is a face-down process, the semiconductor wafer 3 is transferred face-down. Conversely, if the process in that chamber is a face-up process, the arm 6 is rotated 180 degrees again and the paper is conveyed.

According to such a multi-chamber device, the semiconductor wafer 3 can be inverted without requiring an inversion chamber, and the area occupied by the multi-chamber device can be reduced. Further, since the semiconductor wafer 3 can be reversed during the process of directly transporting it from the transport chamber 5 to the process chamber 8, throughput can be improved.

(H, Effect of the invention) As described above, the first aspect of the multi-chamber device of the present invention
The device is characterized by having at least a structural part in which a plurality of chambers or a plurality of processing sections are arranged at different heights.

Therefore, according to the first multi-chamber apparatus of the present invention, since the chambers and processing sections are arranged at different heights, the types of processing that can be performed by the multi-chamber apparatus without substantially increasing the occupied area or Throughput can be increased.

A second multi-chamber device of the present invention is characterized in that it includes a plurality of sets of a plurality of chambers that perform continuous processing.

Therefore, according to the second multi-chamber apparatus of the present invention, a plurality of sets of a plurality of chambers that perform a series of processes are provided, so that a single transfer chamber can be shared by multiple sets. Therefore, the ratio of the area occupied by the multi-chamber device to the work that can be done by the entire multi-chamber device can be reduced. This leads to effective use of factories that cannot be allowed to go to waste.

A third multi-chamber device of the present invention is a multi-chamber device in which each process is performed in a separate chamber, and is characterized by having a plurality of chambers in which time-consuming processes are performed. .

Therefore, according to the third aspect of the multi-chamber apparatus of the present invention, since the number of chambers for performing time-consuming processing is made plural, different semiconductor wafers can be processed simultaneously in the plurality of chambers for time-consuming processing. It is possible to improve the throughput of the entire multi-chamber device.

A fourth multi-chamber device of the present invention is characterized in that a plurality of chambers are divided into a plurality of groups, and a transfer chamber is interposed between the groups.

Therefore, according to the fourth multi-chamber device of the present invention, by forming groups of chambers that do not cause mutual contamination, there is no risk of mutual contamination with respect to the chambers in each group. It is possible to allow more than one to be open at the same time. Therefore, throughput can be improved. And cross-contamination between groups can be prevented by a transfer chamber between them.

A fifth multi-chamber apparatus of the present invention is characterized by having a wafer transfer mechanism in which a transfer arm that holds a wafer in a wafer holder can rotate and invert the wafer.

Therefore, according to the fifth multi-chamber apparatus of the present invention, since the wafer transfer mechanism can invert and transfer the semiconductor wafer, the semiconductor wafer can be directly transferred without interposing an inversion chamber between the transfer chamber and the process chamber. It can be inverted and transported from the transport chamber to the target process chamber. Therefore, throughput can be improved.

[Brief explanation of drawings]

FIGS. 1(A) and 1(B) show a first embodiment of the multi-chamber device of the present invention, in which FIG. 1(A) is a plan sectional view, FIG. 1(B) is a longitudinal sectional view, and FIG. (A) and (B) show modified examples, where (A) is a plan sectional view, (B) is a longitudinal sectional view, and FIGS. This figure shows a second embodiment of the device, in which figure (A) is a plan sectional view, figure (B) is a longitudinal sectional view, and figure (C) is the figure (A).
), FIG. 4 (A>, (B) shows a modified example, FIG. 4 (A) is a perspective view, FIG. 4 (B) is an enlarged perspective view of the wafer holder, FIG. 5 is a perspective view showing another example of a chamber for performing sputtering, FIG. 6 is a plan sectional view showing a third embodiment of the multi-chamber apparatus of the present invention, and FIG. 7 is a fourth embodiment of the multi-chamber apparatus of the present invention. 8 is a plan sectional view showing a modified example, FIGS. 9 and 10 are for explaining another modified example, and FIG. 9 is a plan sectional view showing the configuration. 10(A) to (H) are diagrams showing the process sequence, FIG. 11 is a plan cross-sectional view showing the fifth embodiment of the multi-chamber device of the present invention, and FIG. 12 is a diagram showing the multi-chamber device of the present invention. 13(A) and 13(B) show a conventional example; FIG. 13(A) is a plan sectional view, and FIG. 13(B) is a vertical sectional view. 3. 5. 6. a 9. a Wafer, 4... Gate valve, Transfer chamber, Transfer arm, - Wafer holder, 8... Chamber, Wafer transfer mechanism, - Wafer transfer mechanism with reversing function. Explanation of symbols No. 3 Plane sectional view (A) CB) Conventional example No. 13 - %/-n wp

Claims (5)

[Claims] (1) A multi-chamber device characterized by having at least a structural part in which a plurality of chambers or a plurality of processing sections are arranged at different heights. (2) A multi-chamber device characterized by having multiple sets of multiple chambers that perform a series of treatments (3) A multi-chamber device that performs a series of processes in separate chambers, the multi-chamber device comprising a plurality of chambers that perform time-consuming processes. (4) A multi-chamber device characterized by dividing a plurality of chambers into a plurality of groups and interposing a transfer chamber between the groups. (5) A multi-chamber device characterized by having a wafer transfer mechanism that allows a transfer arm that holds a wafer in a wafer holder to rotate and reverse the wafer.