JPH03272253A - Alarm collection memory circuit - Google Patents

Abstract

PURPOSE:To make a protection priority processing circuit common to a secondary alarm between alarms by providing an alarm pre-state processing circuit and an OR/through circuit or the like and using an AND circuit between a 1st RAM write control signal and a short period signal so as to control the write to a 2nd RAM. CONSTITUTION:The circuit is provided with an alarm pre-state processing circuit 1 applying protection and priority processing to a secondary alarm between alarms, an OR/through circuit 3 applying through or OR processing to an output from the alarm pre-state processing circuit 1, a 1st RAM 4 writing an output data from the OR/through circuit 3 from an address from a collection period counter and a 2nd RAM 5 writing a data of a same address as a data written in the 1st RAM in a shorter period than the 1st RAM. Then an AND circuit 6 controls the write to the 2nd RAM 5 by using a write control signal of the 1st RAM 4 and the shorter period signal.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to standardize protection and priority processing circuits for secondary alarms between each alarm, regarding a memory circuit that collects various alarm information from within the device and from lines, etc. Regarding various alarm information, there is an alarm pre-processing circuit that performs protection and priority processing for secondary alarms between each alarm, a collection cycle counter that counts the alarm collection cycle of the alarm pre-processing circuit, and an output from the alarm pre-processing circuit. an OR/through circuit that performs through or OR processing; a first RAM that writes output data from the OR/through circuit according to an address from the collection cycle counter; and the data that is written to the first RAM is the same. The data at the address of
It has a second RAM that writes in a shorter cycle, and is configured to control the writing surface of the second RAM by an AND circuit of the write control signal of the first RAM and the short cycle signal. .

[Industrial Application Field] The present invention relates to a memory circuit that collects various alarm information from within a device, a line, etc.

The alarm collection LAN inside the NTT station building collects various alarm information from the equipment and lines, but this alarm information includes information that is sent out one second after detection, as well as information from the local alarm collection device, etc. There is information that is sent at the same time as alarm detection, and the latter alarm information is information that requires immediate alarm processing, such as a transmission line switching signal or digital switch switching signal, and is different from the 1 second timing of the former, within 1 second. Alarm information with short timing is required. For this reason, the alarm collection memory contains
Alarm information with different cycles, an alarm signal with a cycle of 1 second and an alarm signal with a short cycle of less than 1 second, is stored, and the CPU
It is necessary to process it by

[Conventional technology]

The block diagram of the conventional alarm collection memory circuit is shown in Fig. 4.
As shown in the figure. In the figure, 2L 25 is an alarm preprocessing circuit, 22.26 is an OR/through circuit, and 23°27 is an RA
M, 24.28 is a collection cycle counter, 29 is a bus alarm T/F, 30 is a ground alarm I/F, and 31 is a CPU.

The collection cycle counter 24 is a 1 second cycle counter that sends the collection cycle pulse every second to the alarm preprocessing circuit 21, stores the alarm cycle data every second in the RAM 23, and outputs the collection cycle pulse every second to the alarm preprocessing circuit 21.
30 and sends out a bus alarm via the bus alarm T/F 29. Collection period counter 28 is 100m
The 5-cycle counter sends the collection cycle pulse every 100 m5 to the alarm pre-processing circuit 25, and the alarm cycle data every 100 m5 is stored in the RAM 27, processed by the CPU 30, and sent to the geo-alarm via the geo-alarm I/F 30. Send out.

The alarm preprocessing circuit 2L 25 inputs various alarm information, protects secondary alarms that occur between each alarm,
A register that performs priority processing, the collection cycle counter 24.2
every 1 second or 1 depending on the counting period from 8 to 1, respectively.
Sends data every 00m5 and sends data to the next OR/Through circuit 2
2 or 26. OR/THRU circuit 22.26
Then, the alarm information of the first address is passed through and is transferred to the next RA.
The alarm information at the following address is ORed with the alarm information stored in the RAM 23.27, and the presence or absence of the alarm information is written into the memory. RAM
Reference numerals 23 and 27 are dual port memories, which store data by alternately repeating writing and reading on both surfaces, 0 and 1, at each acquisition cycle. The data stored in each memory is CP
It is read and processed in U31.

[Problem to be solved by the invention]

In conventional alarm collection memory circuits, different collection circuits were used for things with different processing cycles, for example, for bus alarms and earth alarms, so the alarm pre-processing circuit that performs secondary alarm protection and priority processing is required. Multiple circuits were required, increasing the circuit scale.

The present invention focuses on the fact that the same processing is sufficient for the secondary alarm protection and priority processing, and aims to reduce the circuit scale by making the alarm pre-processing circuit common and only the collection RAM separate. do.

[Means to solve the problem]

FIG. 1 shows the principle configuration diagram of the present invention. In the figure, 1 is an alarm pre-processing circuit that performs protection and priority processing for secondary alarms between each alarm, 2 is a collection cycle counter that counts the alarm collection cycle of the alarm pre-processing circuit,
3 is an OR/THRU circuit that performs a through or OR process on the output from the alarm preprocessing circuit; 4 is a first RAM that writes the output data from the OR/THRU circuit according to the address from the collection cycle counter; The data at the same address as the data written to the first RAM is transferred to the first RAM.
The second RAM, 6, which is written at a cycle shorter than M, is an AND circuit that ANDs the first write control signal and the short cycle signal to obtain a write control signal for the second RAM.

The writing surface of the second RAM 5 is controlled by the first RAM.
OR circuit 6 of the write control signal of 4 and the above short periodic signal
Configure it to do so.

The first RAM 4 and the second RAM 5 each have two sides, with the 0th side of the RAM4 being 40 and the 1st side being 41.
The 0th side of 5 is 50, and the 1st side is 51.

Various alarms are input to the alarm preprocessing circuit 1, and data from the collection cycle counter 2 is input to the OR/through circuit 3 at every 1 second count cycle, and writing and reading are alternately performed on both sides 40 and 41 of the first RAM 4. The stored data is sent to the CPU bus and processed by the CPU. 1st R
The writing of the second RAM 5 is controlled by the OR circuit 6 of the write control signal of the AM4 and the pulse with a cycle shorter than 1 second, and the data at the same address as the first RAM 4 is transferred to the second RAM 4.
Data is written to both sides 50 and 51 of AM5 alternately in short cycles, and the written data is sent to the CPU bus and processed by the CPU.

[Effect]

A timing chart of the present invention is shown in FIG.

In the figure, ■ is the manual alarm signal ALM, ■ is the collection cycle count pulse tI, ■ is the RAM surface control signal t, 1, which repeats on and off in synchronization with the count pulse t1, ■ is the 0th surface data of the first RAM, ■ indicates the first RAM surface data, ■ indicates the RAM surface control signal t2 which repeats on/off in a short period, ■ indicates the second RAM MoO surface data, and ■ indicates the second RAM surface data.

It is synchronized with the RAM surface control signal number collection period count pulse ■, for example, if ■ is the IS period, ■ is 100m5
They are synchronized with each other in cycles. The first RAM surfaces ■ and ■ alternately write and read by the control signal ■.
A through output and an OR output are written on the write side, and data on the write side is read on the read side. In the second RAM planes ■ and ■, the write data of the first RAM planes ■ and ■ are alternately read out by the control signal ■, and writing is repeated. Therefore, it is possible for the CPU to arbitrarily read and output the data on the first RAM surfaces (2) and (2) and the second RAM surfaces (2) and (2).

〔Example〕

A block diagram of an embodiment of the present invention is shown in FIG. The figure shows the timing according to the processing speed (1+ >12> t3 ・
...> This shows the case where RAM is added in t7). In the figure, 11 is an alarm preprocessing circuit, 12 is a collection cycle counter, 13 is an OR/THRU circuit, 14 is a RAMI, 15 is a RAM2.16 is an AND circuit, 17 is RAM n, 1
8 is an AND circuit, 19 is a bus alarm I/F, 20 is an earth alarm I/F, and 10 is a CPU.

RAM1-n and DPRAMXRAM2-n are write-only controlled. If RAMI's timing 1° is IS timing, RAM2's timing t2 is 100m5 timing, and RAMn's timing tn is 10m5 timing, RAM2 is the RAMI write control signal and RAM
Writing is controlled by the AND timing of 2, and the RAM
Writing of n is controlled by ANDing the write control signal of RAMI and the timing of RAMn.

Therefore, 1. >12>1. ...>Alarms collected at intervals of tIl are stored in RAM1 to n,
The CPU can output the alarm processing results in RAMn to the outside at an arbitrary timing, for example, at the trl timing.

〔Effect of the invention〕

According to the present invention, the secondary alarm protection/priority processing circuit can be shared for alarm collection necessary for alarm processing with different processing cycles, and the RAM according to the processing cycle can be used in common.
The alarm collection circuit can be made more compact by simply adding more.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a timing chart of the present invention, Fig. 3 is a block block diagram of an embodiment, and Fig. 4 is a block diagram of the embodiment.
The figure shows a block diagram of a conventional example. In the figure, 1. IL 21.25 is alarm preprocessing circuit, 2.12.24.28 is collection cycle counter, 31
3, 22.26 is an OR/through circuit, 4. 5.14.
15゜23, 27 are RAM, 19.29 is bus alarm I/F, 20.30 is ground alarm I/F, 10.31
is CPU, 616.18 is AND circuit, 40.50 is R
The 0th side of AM, 4151, indicates the 1st side of RAM. In addition, ~
■ indicates the signal waveform of the timing chart.

Claims (1)

[Claims] Regarding various alarm information, an alarm pre-processing circuit (1) that performs protection and priority processing for secondary alarms between each alarm, a collection cycle counter (2) that counts the alarm collection cycle of the alarm pre-processing circuit, and the alarm an OR/through circuit (3) that performs through or OR processing of the output from the preprocessing circuit; a first RAM (4) that writes output data from the OR/through circuit using an address from the collection cycle counter; a second RAM (5) in which data at the same address as the data written in the first RAM is written in a cycle shorter than that of the first RAM;
The first RAM (4) controls the writing surface to the AM (5).
An AND circuit (
6) An alarm collection memory circuit characterized by performing the following.