JPH03272079A - Phase modifying device of vtr - Google Patents

Abstract

PURPOSE:To smoothly and quickly execute the phase modification by providing a reference clock generating means which is used for a servo-circuit of a VTR and generates a clock and a reference signal, and a control means for controlling an oscillation frequency of the clock and the reference signal. CONSTITUTION:A control circuit 32 reads time codes sent from a VTR of a control object and a reproducing device which becomes a reference, respectively from time code readers 30, 31, and sends control data to a reference clock generating circuit 33, based on a difference of both the time codes. That is, in the case the VTR of the control object is reproducing an advanced time code position from the reference reproducing device, the control circuit 32 sends out the control data so as to lower the frequency to the reference clock generating circuit 33, and on the contrary, in the case the VTR is reproducing a delayed time code position, the above circuit sends out the control data so as to raise the frequency. In such a way, running of a tape is subjected to speed control smoothly, the control for migrating to a phase modifying state is simplified, and also, the time required for phase modification is shortened.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention relates to a VTR harmonizing device, and particularly to a harmonizing device for a plurality of VTRs.
Alternatively, the present invention relates to a device for maintaining a constant time relationship between the reproduction signals of the VTR and the signal reproduction apparatus when simultaneously reproducing the VTR and other signal reproduction apparatus.

[Conventional technology]

Figure 6 shows, for example, Japanese Patent Publication No. 1-59662
165950) is a block diagram showing the configuration of a harmonizing device for a VTR disclosed in the publication, in the figure, 1 is the VTR main body, 2 is a phase adjuster for VTR1, 3 is an external reference synchronization signal generation circuit, and 4 is a central processing unit. (CPU), 4a is a pass line, 5 is a control signal reproducing circuit (CTL PRO) that reproduces the control signal CTL of VTR1, 6 is a time code signal reading circuit (TCD READ) that reads the reproduced time code signal from VTR1, 7 controls the tape running drive device of the VTR 1, such as the motor, and
A control circuit (CONT CK
T), 8 is a reference clock (REF CLOCK) that generates a reference clock signal based on the reference frame pulse of rear M, 9
is a reference frame pulse generation circuit that generates a reference frame pulse based on the output of the external reference synchronization signal generation circuit 3
FP GEN).

A part of the control circuit 7 has a configuration shown in the block diagram of FIG. 7, in which 11 is an input terminal for a reproduction control signal CTL, 12 is an input terminal for a clock pulse CP, and 1 is an input terminal for a clock pulse CP.
3 is the reference frame pulse SFp input terminal, 14.15
is a NAND gate, 1619 is a counter (CNT),
18.20 is a latch circuit (LTC) that latches the outputs of counters 16 and 19, 17 is a clock pulse CP o
Frequency dividing circuit that divides the frequency into I/N, 21, 22.23.24
is a D flip-flop.

Next, the operation will be explained.

The control circuit 7 receives a reproduction control signal CTL from the control signal reproduction circuit 5, a tape current time signal and its tape target time signal from the time code reading circuit 6, and a reference current time signal and its reference target time from the reference clock 8. signal and a reference frame pulse from a reference frame pulse generation circuit 9.

The reproduction control signal CTL and the reference frame pulse SFP are transmitted through the D flip-flops 21 and 23 shown in FIG.
is given to. D flip-flop 21.22 and N
By the combination of AND circuit I4, reproduction control signal CTL
A clear pulse CLP is generated at the falling edge of , and applied to the counter 16.degree. 19 and the latch circuit 20.

Further, the D flip-flops 23 and 24 and the NAND circuit 15 generate a latch pulse PSP at the falling edge of the reference frame pulse SFP, and the latch circuit 18
is giving to

Since the output of the counter 16 is connected to the latch circuit 18, the output value of the counter I6 at the falling edge of the reference frame pulse SFP is output from the latch circuit 18. The counter 16 is cleared by CLP output at the falling edge of the reproduction control signal CTL and counts the output clock of the frequency divider circuit 17, so the output of the latch circuit 18 is
The number of pulses Fp is obtained based on the phase difference between the falling edge of the reproduction control signal CTL and the falling edge of the reference frame pulse SFP.

On the other hand, the counter 19 also operates in the same manner as the counter 16, but the launch circuit 20 that receives its output is configured to take in the data immediately before the counter 19 is cleared based on the clear pulse CLP. The number of pulses proportional to the time interval of the control signal CTL, ie, the tape speed detection signal, is the output of the latch circuit 20. The output of the latch circuit 18.20 is supplied to the 110 port of the central processing unit 4.

The harmonization process is explained by the signal waveforms in FIGS. 8(a) and 8(b) and the operation flow in FIG. 9.

In FIG. 8(a), the horizontal axis represents time and the vertical axis represents tape running speed, and in FIG. 8(b), the horizontal axis represents time and the vertical axis represents time. In FIG. 8(b), CCT indicates the reference current time based on the clock signal of the reference clock 8, TCT indicates the target time, CTT indicates the tape current time based on the reproduction time code TCD, and TTT indicates the target time.

First, the tape TP of the VTRI is temporarily run, the reading circuit 6 reads the reproduction time code TCD, and the tape target time TTT is set. Further, the reference start time and reference target time TCT of the reference clock 8 are set in consideration of the tape start time, tape target time TTT, and total processing time. Then, at the same time as starting the operation at reference time 8, the tape TP is fast-forwarded or rewound, and the tape running speed is brought to around the normal playback speed (1x speed) at time t1, for example, three frames before or after the tape target time TTT. Thereafter, the running of the tape is controlled as shown in FIGS. 8 and 9.

The tape speed detection signal obtained from the latch circuit 20 determines whether the tape speed is 1x speed or not. If the tape speed is not 1x speed, after one frame, it is determined again whether the reproduced tape speed is 1x speed or not. conduct.

When the tape speed is 1x, the phases of the playback control signal CTL from the tape TP and the reference frame pulse SFP are compared, and the tape difference time TTT-CTT between the tape target time TTT and the tape current time CTT is compared with the reference time. The reference time difference TCT-CCT between the reference target time TCT based on the hour signal and the reference current time CCT is time-compared, and the phase difference Fp obtained by the phase comparison is within a predetermined value, for example, 60<F,<
100 and the time difference d disappears, that is, the traveling drive means is controlled so that d=(TTT-CTT)-(TCT-CCT)=0. At this time, Fp<
When FP is 60, the tape TP is driven at 1.08 times the speed, while when FP>100, the tape TP is driven at 0.92 times the speed, and the tape position is corrected so that 60<F, <100.

Then, if 60<F, <100, d= (TTT
-CTT)-(TCT-CCT) determines whether d=0, and when d<0, the tape is driven at 0.88 times the speed, and when d>0, the tape is driven at 1.17 times the speed. Correct the tape position by

After this, the process returns to detecting the tape speed. Time L in Figure 8
If d=o at x, the control circuit 7 outputs VT
A reproduction command signal is given to R, and shortly thereafter, at time t, reproduction starts from the track of the frame at tape target time TTT.

If the VTR locks onto the adjacent frame, the phase adjustment will have to be redone, which takes a considerable amount of time. Therefore, in this example, the VTR is set so that the reproduced time code signal obtained from the VTR and the reference time signal obtained from the reference signal match.
control the running state of the frame pulse and the reference frame pulse;
The phase difference with the reproduction frame pulse is also monitored and a reproduction command signal is given to the VTR.

[Problem to be solved by the invention]

The conventional phase adjusting device is configured as described above, and
Because the influence of the control signal on the operation of the servo circuit that controls the tape running built in is not sufficiently considered, the tape speed control performed when entering harmonization is not always smooth, and it is difficult to correct small time differences. could also take time.

This invention was made to solve the above-mentioned problems, and it is possible to smoothly control the speed of tape running, simplify the control for transitioning to the phase adjustment state, and reduce the time required for the phase adjustment. The purpose is to obtain a phase modifier that can be shortened.

[Means to solve the problem]

A VTR0 phase adjustment device according to the present invention has a reference clock generating means for generating a clock and a reference signal used in a servo circuit of a VTR, and a control means for controlling the oscillation frequency of the clock and reference signal.

[Effect]

In this invention, since the tape running speed is controlled by changing the frequency of the lock and reference signals required for the operation of the VTR's servo circuit, variable tape running is possible when the VTR's servo circuit is in the retracted state. This allows the tape speed to smoothly shift to the normal playback state.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a VTR harmonization device according to an embodiment of the present invention, in which 30 is a time code reader circuit (TCR) for reading the reproduced time code signal of the VTR to be controlled; is a time code reader circuit (TCR) for reading the time code signal sent from the playback device that serves as a reference for phase adjustment, 3
2 is a control circuit (CONT) for controlling the reference clock generation circuit 33; 33 is a reference clock generation circuit (CLK G) that generates a clock to be supplied to the servo circuit of the VTR;
EN), 34 is a frequency dividing circuit (Dm), 35 is a VTR reproduction time code signal input terminal, 36 is a reproduction time code signal input terminal from a reference reproduction device, 37 is a servo reference clock output terminal, and 38 is a servo reference signal It is an output terminal.

A VTR incorporates a servo circuit for controlling tape feeding and drum rotation, and the circuit used here is generally a digital servo circuit. Servo circuits can be divided into speed control and phase control.

FIG. 2 is a block diagram showing an example of a servo circuit for speed control, in which 40 is a frequency dividing circuit that divides the capstan FG signal having a frequency proportional to the speed of the capstan, 41 is a latch circuit, 42 is a speed error gate circuit for supplying the output of the speed comparison counter 43 to the latch circuit 4I, 43 is a speed comparison counter that counts clock pulses, 44 is an AND circuit, and 45.46 is a speed comparison counter 4
3, a count value discrimination circuit that becomes high level or low level depending on the count value; 47, a pulse generation circuit that creates launch pulses and preset pulses from the frequency-divided FC signal and clock pulse; 48, a speed comparison counter initializing circuit; A preset circuit for presetting a value, 49 a decoder circuit that decodes a mode designation signal input from the outside and sends a control signal to a preset value generation circuit 50, and 50 a preset that outputs a value in accordance with the output of the decoder circuit. This is a value generation circuit.

The operation of this circuit will be explained with reference to FIG.

A capstan FC signal, which is a pulse having a frequency proportional to the speed of the capstan, is frequency-divided by a frequency dividing circuit 4° and then input to a pulse generating circuit 47.

Based on the output of the frequency dividing circuit 40, the pulse generation circuit 47
A latch pulse is supplied to the latch circuit 41, and a preset pulse having a fixed time interval with respect to the latch pulse is output to the preset circuit 48.

At the timing when the preset pulse is output, the speed comparison counter 43 is preset to the value NP output from the preset value generation circuit 5°. A clock pulse is applied to the speed comparison counter 43 via an AND circuit 44. When the count value of the speed comparison counter 43 reaches NF, the output of the count value discrimination circuit GH45 becomes low level, and the AND circuit 44 stops the clock supplied to the speed comparison counter 43, so the speed comparison counter 43 stops counting. do.

On the other hand, the count value discrimination circuit GL46 is set so that its output becomes high level when the count value becomes equal to or greater than NL. When the count value discrimination circuit GL46 becomes high level, the speed error gate 42 opens, and the latch circuit 41 outputs the speed comparison counter 43.
The count value is transmitted to the latch circuit 41. Therefore, latch times! 41 is given the trapezoidal wave signal value shown in FIG. Therefore, the value latched by the launch circuit 41 is determined by the frequency of the FC signal, that is, the capstan speed. The output value of the latch circuit 41 takes a small value when the frequency of the FC signal is high, and conversely takes a large value when the frequency of the FC signal is low, so this can be used as a speed error signal to apply speed servo.

In the servo that controls tape running, that is, the capstan servo, a servo that matches the phase of the rotation of the drum and the CTL signal recorded on the tape is also operating at the same time.

Figure 4 is a block diagram of the servo for controlling the phase.
60 is a latch pulse creation circuit that creates a latch pulse to be given to the latch circuit 63 from the comparison signal TDMM based on the reproduced CTL signal; 61 is a preset circuit that creates a preset based on the reference signal TRMM; Based on the preset value generation circuit 67
63 is a launch circuit, 6 is a decoder circuit for controlling the
4 is a speed error gate circuit for controlling data given to the latch circuit 63; 65 is a phase comparison counter for counting clock pulses; 66 is a preset circuit for presetting the phase comparison counter; 67 is for presetting the phase comparison counter 65. The preset value generating circuits 68 and 69 each represent a count value determining circuit whose output changes according to the count value of the phase comparison counter 65.

The operation of this circuit is illustrated in FIG.

The reference signal used to create the preset pulse maintains a constant phase relationship with the reference signal of the drum servo, and based on this signal, the preset pulse creation circuit 61 generates the preset value generation time as in the case of FIG. ! 367 and the preset circuit 66 to preset the count value of the phase comparison counter 65.

The count value discrimination circuits GH6B and GL69 detect that the count value of the phase comparison counter 65 has reached NH and NL, respectively, and inform the phase error gate circuit 64. In the phase error gate circuit 64, the count value is between NL and NHO. , the count of the phase comparison counter 65 is directly applied to the launch circuit 63, and when it is below NL, NL is always applied to the launch circuit 63, and when it is above NH, NH is always applied to the launch circuit 63.

On the other hand, a comparison signal (TDM
Since the timing at which the latch circuit 63 latches data is determined by M), the output value of the latch circuit 63 changes depending on the phase error between the reproduced CTL signal and the reference signal. That is, the output value of the latch circuit 63 can be used as an error signal for phase control.

In this way, the servo, which keeps the tape feeding speed constant and matches the phase of the rotation of the drum and the tape feeding, is operated by a clock and a reference signal supplied from the outside.

In the phase adjustment device of the present invention, the tape feeding speed is changed without disturbing the servo system by changing the frequency of the clock and reference signal used in the servo.

The phase adjusting operation will be explained below based on FIG.

The control circuit reads the time codes sent from the VTR to be controlled and the reference playback device from the time code reader 30.31, and sends control data to the reference clock generation circuit 33 based on the difference between the two time codes. send.

It is assumed that the reference clock generation circuit 33 has a built-in frequency synthesizer circuit and is configured to change the frequency of the generated clock based on control data sent from the control circuit 32. The control circuit 32 controls the VT to be controlled.
When R is reproducing a time code position that is ahead of the reference reproduction device, control data is sent to the reference clock generation circuit 33 to lower the frequency, and conversely, the VTR to be controlled is
If the playback device is playing back a time code position that is delayed from the reference playback device, control data is sent to increase the frequency. The clock output from the reference time code generation circuit 33 is used as the clock pulse in FIGS. 2 and 4. As is clear from the operation of the servo circuit described above, when the frequency of the clock pulse shown in FIG. 2 increases, the servo system locks when the frequency of the FG signal is high, that is, when the tape travels quickly.

Therefore, as the output clock frequency of the reference pulse generating circuit 33 increases, tape running becomes faster, and conversely, as the frequency decreases, tape running becomes slower.

On the other hand, the reference signal in FIG. 4 is created by dividing the output clock of the reference pulse generation circuit 33 by a frequency dividing circuit 34. With this configuration, by changing the frequency of the output clock of the reference clock generation circuit 33,
The tape can be run at various speeds with the servo system locked, including the phase.

On the other hand, the drum servo system can be configured in exactly the same way, so if the clock and reference signals are given as the output signals shown in Figure 1,
The drum servo can also be kept locked. Therefore, by controlling the reference clock frequency according to the time code difference and gradually bringing the reference clock frequency closer to normal playback as the time code difference becomes smaller, a smooth and quick start-up operation can be achieved. Further, when transitioning from a state in which the tape speed is changed for phase adjustment to normal playback, disturbances in the servo system of the VTR are small and the tape running state does not change.

The VTR servo circuit to which this embodiment can be applied is not limited to the circuit example described above, but may be any circuit as long as it can input both a clock and a reference signal from the outside.

〔Effect of the invention〕

As described above, according to the VTR0 phase adjustment device according to the present invention, the tape running speed is controlled by changing the clock and reference signal used in the servo system of the VTR to be controlled. It can be done smoothly and quickly.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a VTR harmonizing device according to an embodiment of the present invention, Fig. 2 is a block diagram showing an example of a VTR cab stun speed control circuit, and Fig. 3 is an operation of the circuit shown in Fig. 2. FIG. 4 is a block diagram showing an example of a capstan phase control circuit for a VTR, FIG. 5 is a timing chart showing the operation of the circuit shown in FIG. 4, and FIG. 6 is a conventional 7 is a block diagram showing a part of the control circuit 7 in FIG. 6, FIG. 8 is a characteristic curve diagram, and FIG. 9 is a block diagram showing a conventional VTR0 phase adjuster.
FIG. 3 is a flowchart diagram showing the operation of the TR harmonizer. 30, 31 is a time code reader circuit, 32 is a control circuit, 33 is a reference clock generation circuit, and 34 is a frequency dividing circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a VTR phase adjustment device that maintains a constant time relationship between reproduction signals output from multiple signal reproduction devices, a clock whose frequency changes according to a control signal is used to control the running of a controlled VTR that is the object of control. A reference clock generating means for supplying to the servo system, a frequency dividing means for dividing the frequency of the clock and supplying the clock as a reference signal to the travel control device of the VTR, and a first clock for reading the time code output from the reference reproduction device. time code reading means and the controlled VTR
and a control means for creating the control signal based on the difference between the time codes read by both the time code reading means. VTR phase adjustment device.