JPH03270044A - Inspection of semiconductor device - Google Patents

Abstract

PURPOSE:To decide the deterioration of reliability on the gate of a full-size device easily by forming a plurality of gates for inspection having two kinds of insulating films having different film thickness and/or area ratios while changing the ratios onto a semiconductor substrate at approximately the same time as the full-size device and comparing said film thickness with the structural ratio of a gate for inspection, a calibration curve of which is broken. CONSTITUTION:When the film thickness of insulating films 3, 4 is represented by d1 and d2, a plurality of gates 2 for inspection are formed while film- thickness ratios Dp=d2/d1 as structural ratios determined by the structure are changed. The gates 2 for inspection are formed, a plurality of probes are brought into contact with each gate 2 for inspection, voltage, by which at least one of the gates 2 is electrostatically broken, is applied, and the first insulating films 3 are electrostatically broken. Electrostatic breakdown is generated because field strength in the first insulating films 3 is increased by applied voltage. Accordingly, the structural ratios of the gates 2 for inspection, which are electrostatically broken, are compared with a prepared gate-breakdown calibration curve Cc, thus deciding the degree of the deterioration of reliability on the gate of a full-size device.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a method for inspecting a semiconductor device, and more specifically, when manufacturing a semiconductor device (actual device) on a semiconductor substrate, it is possible to inspect gates during the manufacturing process. The present invention relates to a semiconductor device inspection method for determining reliability deterioration (life shortening) due to added electrostatic damage without measuring TDDB characteristics.

(B) Conventional Technology In the manufacturing process of semiconductor devices, electrostatic breakdown of the insulating film of a gate having a MOS or MNOS structure due to charge-up often occurs. One way to suppress this is to neutralize the charge-up by irradiating it with an electron beam.

Conventionally, it has become difficult to measure electrostatic breakdown of gate insulating films or electrostatic damage to gates in actual devices because gates in LSIs and other devices have become finer and the number of gates has increased. ing. In contrast, in recent years, these measurements have been made: forming actual devices in the same process as actual devices formed on a wafer, and measuring the withstand voltage or reliability of gates formed on separate wafers. It is carried out.

The withstand voltage of the gate is measured by applying a plurality of probes to the gate, applying a voltage that will cause destruction through the probes, and measuring the voltage at the point when current flows.

Furthermore, the reliability of the gate is measured by applying a plurality of deep needles to the gate in the same manner as described above, applying a voltage that does not instantly cause breakdown, and measuring the time until breakdown occurs.

(c) Problems to be Solved by the Invention However, in the above method, it is difficult to determine the extent to which the gate of the actual device is electrostatically damaged during the so-called static charge process such as ion implantation and plasma treatment in the manufacturing process of the actual device. The only way to determine whether or not the electrostatic damage has been caused is by the presence or absence of damage to the gate, and it is unclear to what extent the lifespan of undamaged gates will be shortened by electrostatic damage.

In order to improve the accuracy of the above measurements, it was necessary to perform measurements using a large number of measurement targets in order to perform statistical processing.

This invention was made in consideration of the above circumstances, and it is possible to judge the reliability of a gate that does not cause electrostatic damage in an actual device by using a gate destruction calibration curve prepared in advance. This paper attempts to share an inspection method for the following.

B) Means and operation for solving the problems This invention forms an actual device on one semiconductor substrate, and at the same time, a second film with a large thickness is formed on a region of the semiconductor substrate where the actual device is not formed. a first inspection gate formed by continuously forming one insulating film and a second insulating film having a smaller thickness, and further stacking electrodes on these insulating films;
The first insulating film and the second insulating film in this first inspection gate have different film thickness ratios and/or area ratios, and electrodes are laminated thereon. Each inspection gate is provided, and the breakdown state of the inspection gate obtained by subjecting these multiple inspection gates to the same conditions as the charging process performed during the formation of the actual device, and the comparison gate prepared in advance. A semiconductor device inspection method is characterized in that the damage state of an actual device is detected by comparing the gate breakdown calibration curve with a gate breakdown calibration curve according to the present invention.

In this invention, at least one of the test gates formed on the semiconductor substrate on which the actual device is manufactured is electrostatically damaged due to processing conditions in a process that involves a build-up of electricity in the manufacturing process of the actual device. The structural ratio of the inspection gate that has been electrically destroyed is compared with a gate destruction calibration curve prepared in advance. Then, electrostatic damage to the gate in the actual device to be manufactured is determined from the calibration curve. Therefore, the degree of reliability deterioration (shortened life) due to electrostatic damage to the actual device during the charging process can be confirmed without measuring the breakdown voltage and reliability of the gate of the actual device.

(e) Examples Hereinafter, examples of the present invention will be described in detail with reference to the drawings, but the present invention is not limited to the following examples.

FIG. 1 is a diagram showing the structure of an inspection gate according to an embodiment of the present invention.

In the figure, l is a wafer made of Si which is a semiconductor substrate, and the area other than the area where the inspection gate 20 is formed is an actual semiconductor device, that is, MOS or MNOS.
A real device with a gate of +71 a is formed.

The inspection gate 2 consists of a thin first insulating film 3 formed on a wafer 1, and a second insulating film 4 formed continuously with the second insulating film 4, which is thicker than the first insulating film 3. , a first insulating film 3 and an electrode 5 formed on the upper surface of the second insulating film 4. The first insulating film 3 corresponds to a gate insulating film in an actual device, and the second insulating film 4 corresponds to a LOCOS oxide film in an actual device. These insulators @34 are formed approximately at the same time as the insulating film manufacturing process in the actual device.

That is, during actual device manufacturing, St ions are implanted into the wafer 1 using Renost masks corresponding to the first insulating film 3 and the second insulating film 4. At this time, by performing ion implantation while changing implantation conditions such as implantation energy and dose, the thickness of the damaged layer formed in the wafer 1 can be changed. By performing a thermal oxidation step in the subsequent manufacturing process of the actual device, the first insulating film 3 and the second insulating film 4 having different film thicknesses are formed.

Assuming that the film thicknesses of the respective insulating films 3.4 are dl and d, the inspection gate 2 is formed by changing the film thickness ratio Dp=dt/d, which is a structural ratio determined by its structure, for example, 1.
0 pieces are formed. The film thickness ratio Dp is appropriately set at a value of 10 to 10,000 in consideration of the film thickness ratio at the gate of the actual device.

After forming the above-mentioned inspection gates 2, a plurality of deep needles are brought into contact with each inspection gate 2, and at least one of them is applied at a voltage that causes electrostatic breakdown, i.e., a process involving a current stagnation in the actual device manufacturing process. A voltage set under the same processing conditions as in step 1 is applied to cause electrostatic breakdown of the first insulating film 3.

This occurs because the electric field strength in the first insulating film 3 increases due to the applied voltage. The structural ratio of the inspection gate 2 damaged by electrostatic discharge is compared with the gate destruction calibration curve (hereinafter referred to as calibration curve) Cc created in advance as shown in FIG. The degree of reliability deterioration is T D D B (Ti
me Dependent Dielectric B
It is created by plotting the correlation between the time required for electrostatic discharge breakdown (reakdown (electrostatic breakdown over time) and the structural ratio of the gate. TDDB characteristics are the relationship between the applied voltage and the time required to reach breakdown according to the lifespan of each gate when a constant voltage that does not cause instantaneous electrostatic breakdown is applied to the comparison gate (l) or multiple gates. The time obtained from this characteristic is used to create the calibration curve Cc.

In FIG. 2, a plurality of calibration curves Cc are created by plotting while changing the voltage applied to the comparison gate. In the figure, the TDDB whose time t to destruction is O is the one which has been permanently destroyed by electrostatic discharge, and for example, in the calibration curve Ccl, the structural ratio is 100.
A gate of 0 corresponds to this.

Therefore, using the calibration curve Ccl, for example, if the film thickness ratio op of the destroyed inspection gate 2 is 1000, the gate of an actual device with a structure ratio of 100 will be It can be seen that due to the electrostatic damage received, the time t required for TDDB to break down has become the time ta. In other words, the film thickness ratio D of the inspection gate 2
The degree of deterioration in reliability of the gate of an actual device having a structure ratio smaller than p is determined.

FIG. 3 is a diagram showing the case where the area ratio of each insulating film of the inspection gate is changed.

Insulating films with different area ratios are formed by making the opening areas of resist patterns different during production of actual devices.

In FIG. 3, the inspection gates 21, 22.23 have an area 'll+ of the first insulating film 31, 32, 33, respectively.
112+113 has a structure smaller than the area aye, att+a*3 of the second insulating film 41, 42, 43. In this case, the first insulating film 3+, 32°3:4
')'I'Q'S: 1 has the same name, and
This third insulating film 11. 〆12. =13 film thicknesses and are the same.

And the film thickness of the first edge 13+, 32.33 is the second edge +
It is thinner than the film thickness of 1q.11.42.43.

In this way, the area ratio A I) l”' a ?l/ a
ll+ A pta 22/ a 12.
, to l) Change 3''' a, z/a +3, use the f-2 test case 2+, 22.23, create a second child in the same manner as above, and use the f-calibration curve to determine the case of the actual device with a smaller structural ratio than this. Determine the degree of reliability deterioration.

It is better to form multiple inspection cages by changing the thickness and area of each insulating film.

Further, the thickness of each insulating film of the inspection gate may be changed by etching. That is, in the step of forming a thermal oxide film for an actual device, an oxide film is formed as it becomes the basis of the insulating film of each device. Next, a Renost mask is laminated on the thermal oxide film, and then the thermal oxide film is etched using HF. At this time, the thickness of the thermally oxidized film after etching is controlled by changing the etching treatment time.

(f) Effects of the Invention According to the present invention, a plurality of inspection gates having at least two types of insulating films having different film thicknesses and/or area ratios are formed on a semiconductor substrate at the same time as the actual device, with the ratios being changed. By comparing the calibration curve created in advance with the structural ratio of the destroyed inspection gate, it is possible to easily determine the degree of deterioration in gate reliability (life) in the actual device that has gone through the manufacturing process. That is, the reliability of the gate of an actual device can be evaluated without measuring reliability using the gate of the actual device.

[Brief explanation of drawings]

FIG. 1 is a vertical cross-sectional view of the main part showing the structure of the test gate in the embodiment of the present invention, FIG. 2 is a graph showing the calibration curve in the embodiment, and FIG. 3 is a plan view of the main part showing the structure of the test gate. It is a diagram. ... Wafer 2. 3... First insulating film, ... Electrode, Cc... Inspection gate, 4... Second insulating film, - Calibration curve. 41 Note 3 Figure 2 Z

Claims (1)

[Claims] 1. At the same time as forming an actual device on one semiconductor substrate, a first insulating film with a large thickness and a second insulating film with a smaller thickness are formed on a region of the semiconductor substrate where the actual device is not formed. A first inspection gate formed by continuously forming films and further laminating electrodes on these insulating films, and a film thickness ratio of the first insulating film and the second insulating film in this first inspection gate. And/or second, third or more multiple inspection gates having different area ratios and having electrodes stacked thereon are provided, and these multiple inspection gates are used to form the actual device. To detect the damage state of the actual device by comparing the destruction state of the inspection gate obtained by subjecting it to the same conditions as the charging process that is sometimes performed and the gate destruction calibration curve created in advance by the comparison gate. A semiconductor device inspection method characterized by: