JPH03266121A - Pipeline control system - Google Patents

Abstract

PURPOSE:To detect a confliction in real time without making control complicated by detecting the confliction and interlocking a register read stage when a register read address is matched with a register write address. CONSTITUTION:A register write flag 12 is set in the stage of the transition to the write stage 10-4 of a register. When the register write address of a precedent instruction which is already found is matched with the register lead address of a following instruction, a confliction detecting means 14 detects the confliction and informs the read stage 10-2 of the detection result to stop the register writing of the read register 10-2 (interlock the read stage 10-2). Consequently, the confliction between the register writing of the precedent instruction and the register writing of the precedent instruction and the register reading of the following instruction is detected in the real time to execute the instructions without any contradiction.

Description

[Detailed Description of the Invention] [Summary] Regarding a pipeline control method with a stage configuration that has a register write stage after the core register read stage and executes each stage divided into two or more cycles, the register write of the preceding instruction and the subsequent The purpose is to detect conflicts that occur when reading registers of instructions that execute registers, and to execute instructions without contradiction.A register write flag is set when the execution moves to the register write stage, and is reset when the write is completed. When the address matches the register read address and the register write flag is in a set state, a conflict is detected and the operation of the register read stage is stopped until the register write is completed.

[Industrial Application Field] The present invention relates to a pipeline control method for a processor that uses a multi-stage pipeline to decode and execute instructions.

When executing instructions using a pipeline, if the read stage and write stage of a general-purpose register are different, a register conflict may occur where register writes and reads are performed in the opposite order. be. Therefore, it is necessary to detect the occurrence of register conflict in advance and control the execution of each stage so that the correct order is achieved.

[Prior Art] In a conventional pipeline control method, for example, as shown in FIG. 5, instructions are sequentially decoded and executed using a pipeline having a four-stage structure from stage 1 to stage 4. . Stages 1 to 4 perform, for example, the following processing.

Stage 1; Instruction decode stage 2; Address calculation stage 3; Address conversion stage 4; Instruction execution Here, stage 2 functions as a read stage that reads the contents of the register address in the general-purpose register 16 obtained by address calculation, for example. Motsu. Furthermore, the stage 4 has a function as a write stage for writing the executed result to the address in the general-purpose register 16 that has already been obtained by the address calculation in the stage 2, for example.

[Problems to be Solved by the Invention] However, in a pipeline with a stage configuration in which the read stage and write stage of registers are different, there is a possibility that conflict in general-purpose registers will occur when consecutive instructions are executed. be.

The occurrence of conflict in general-purpose registers will be explained with reference to FIG. 5 as follows.

Suppose that two instructions A and B are consecutively given to the pipeline. The preceding instruction A reads the contents of an arbitrary address of the general-purpose register 16 as R■ in stage 2, which is a read stage, and then proceeds to stage 4, which is a write stage, and stores the result in the shaded address of the general-purpose register 16. do.

Here, it is assumed that the subsequent instruction B is an instruction to read the contents written to the shaded area of the general-purpose register 16 by executing the instruction A and calculate, for example, an address.

However, if instruction B is executed in stage 2 following instruction A and the content of the address in the shaded area of the general-purpose register 16 is read as R■, then the register of W■ in stage 4 due to the preceding instruction A No writing has been performed, and a conflict arises in which meaningless register contents are read with R.

Conventionally, no hardware has been specially prepared to detect the occurrence of conflicts in general-purpose registers. As a result, conflicts could not be detected when reading registers using firmware.

Therefore, in the conventional method, as shown in Figure 6, the timing of the register write W■ in the write stage is fixed, and the firmware in the read stage is configured to write the register if the preceding instruction is an instruction to write the register. , N about the read stage until the write W■ is completed.
Register read is made to wait by executing OP (non-operation), and register read R is performed upon completion of write W of the preceding instruction to prevent register conflicts.

However, in a control method that fixes the timing of register write, there is no flexibility in the timing of writing the register in the write stage, and therefore there is a problem in that the flexibility of pipeline control is impaired.

The present invention has been made in view of these conventional problems, and it is possible to detect conflicts that occur between a register write of a preceding instruction and a register read of a subsequent instruction in real time, so that instructions can be executed without conflict. The purpose of this paper is to provide a pipeline control method with

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

First, the present invention provides a read stage 10-2 for reading a general-purpose register, a read stage 10-2 for reading a general-purpose register, and a read stage
-4 is provided with a write stage 10-4 located after the write stage 10-4 for writing general-purpose registers, and each stage 10-1 to 1
The target is a pipeline control method for a processor in which the execution of instructions 0 to 4 is divided into two or more N cycles, for example, N=2 cycles.

Regarding such a pipe write control system, the present invention includes a register write flag 12 that is set when execution is transferred to the write stage 10-4, and is reset when the write stage 10-4 finishes writing the register; 10-2 and each register address in the write stage 10-4 are compared, and when both addresses match and the register write flag 12 is set, a register conflict is detected and the read stage 10-4
2 is provided with a conflict detection means 14 for stopping the execution of step 2 until the register write is completed.

[Operation] According to the pipeline control method of the present invention having such a configuration, the register write flag is set at the stage of transitioning to the register write stage, and at this time, the register write address of the preceding instruction and the register write address already obtained are set. If the register read address of the subsequent instruction matches, a conflict is detected, this detection result is notified to the read stage firmware, the register write of the read stage is stopped (read stage interlock), and the register controller is It is possible to prevent friction from occurring.

Such conflict detection requires N cycles (N2
In pipeline 2), register address stage N
The stage before the stage can be used as a read stage, and in the write stage, register writes can be performed at any timing without being subject to restrictions to avoid conflicts.

[Embodiment] FIG. 2 is a block diagram showing an embodiment of the present invention.

In FIG. 2, the pipeline is configured into four stages, stages 1 to 4, each consisting of a decoder 101, an address calculation unit 10-2, an address conversion unit (DAT unit) 10-3 that converts a virtual address into a real address, and an execution unit. It consists of a section 10-4.

Here, stage 2 as the address calculation unit 10-2 is a read stage, and the system storage (C8) 16
Specify the address of the general-purpose register on the side and read the contents of the register. Also, stage 4 as the execution unit 10-4
is the write stage, and writes the executed result to the general-purpose register on the system storage 16 side.

The address of the general-purpose register on the system storage 16 side in the read stage of stage 2 and the write stage of stage 4 is determined by the address calculation unit 10-2 as stage 2 in the opcode part of the instruction decoded by the decoder 10-1. It is calculated from the subsequent calculation of the value of the register address field.

Furthermore, when each of stages 1 to 4 executes an instruction that involves a register write and a subsequent register read that may cause a register conflict, each stage divides the instruction into two or more N cycles. In the embodiment shown in FIG. 2, the pipeline configuration is such that the process is executed in N=2 cycles.

In the present invention, such a pipeline is provided with a flag register 12-1 in which a register write flag 12 is set and a conflict detection circuit 14 in order to detect register conflicts.

The flag register 12-1 sets the register write flag 12 at the timing when processing is transferred from the address conversion unit 10-3 of stage 3 to the execution unit 10-4 of stage 4, which performs register write, and the register write flag 12-1 is set by - degrees. 12 is reset when the register write is completed in the execution unit 10-4.

On the other hand, the conflict detection circuit 14 receives the register address associated with the execution of the instruction by the address calculation unit 10-2 as a read stage, receives the register write address for the preceding instruction, and calculates the register read address for the next instruction. When received, the two addresses are compared, and when the two addresses match, the conflict detection signal C0NF is sent to the stage of the address calculation unit 10-2 on the condition that the set flag of the register write flag 12 has been obtained from the flag register 12-1. Output to firmware that performs transition control. The firmware of the address calculation unit 10-2 that receives the conflict detection signal C0NF from the conflict detection circuit 14 applies an interlock to stop stage transition control while the conflict detection signal C0NF is obtained. .

FIG. 3 shows a stage transition control signal STI for stages 1 to 4 in the pipeline shown in FIG.

ST2. 2 is a configuration diagram of an embodiment of a stage control circuit that generates ST3 and ST4, and the conflict detection signal C0 output from the conflict detection circuit 14 in FIG.
Equipped with stage 2 interlock function by NF.

In FIG. 3, the stage control circuit is AND game) 18,
32.36, D-FF20, 28.34.38 and OR
The gates 22, 24, and 30 are constructed as shown.

Here, ID0K input to one side of AND gate 18
The signal is a signal that notifies that the processing of stage 1 of the previous instruction has been completed, and if this ID0K signal is on and the stage transition control signal ST2 of stage 2 is off, the next instruction is decoded. You can start.

The conflict detection signal C0NF is input to one of the OR gates 24 that generate the stage transition control signal ST2 of the stage 2. When the conflict detection signal C0NF is turned on due to conflict detection, the stage 2
The stage transition control signal ST2 continues to extend in the on state,
This makes it possible to create an interlock that causes the execution of stage 2 to wait.

Next, referring to the operation timing chart in Figure 4, the second
The operation of the embodiment shown in FIG. 3 will be explained.

Now, as shown in the timing chart of the pipeline consisting of stages 1 to 4 in Figure 4, instructions ■ and ■ are consecutive, and the following instruction ■ is the preceding instruction in the second stage (lead stage). The process of reading the contents written in the fourth stage (write stage) of (2) is executed.

In response to such instructions (1) and (2), the stage control circuit 3 shown in FIG.
occurs. This stage transition control signal STI~ST4
Accordingly, the firmware at each stage divides the instructions (1) and (2) into two cycles and executes the processing. That is, in the first stage for the instruction (2), decoding is performed in two cycles as shown by Di and D2, and in the next second stage, A1. As shown in A2, the address calculation is divided into two cycles, and in the third stage, DATl, DA
Address conversion is performed separately in T2.

Subsequently, when the processing of the instruction (2) is transferred from the third stage to the fourth stage execution section, the register write flag 12 is set in the flag register 12-1 by the firmware of the execution section 10-4.

On the other hand, in the subsequent instruction ■, D
Lysocoded over two cycles as shown in I and D2,
A read address is obtained at A1 in the first cycle of the second stage and provided to the conflict detection circuit 14. The conflict detection circuit 14 compares the register write address obtained in the second stage processing of the preceding instruction ■ with the register read address obtained in the execution A1 of the instruction ■ in the second stage, and finds that the two match. If the register write flag 12 is set, the conflict detection signal C0NF
Turn on. In this way, the conflict detection signal C0
When the NF is turned on, the stage transition control signal ST2 of the stage 2 output from the D-FF 28 continues to extend the on state, as is clear from the stage control circuit of FIG.
As a result, address calculation processing by the stage 2 firmware is stopped.

On the other hand, in the fourth stage as the execution part, the command ■
In response to the address conversion DATI of the write stage, the instruction execution EX is executed, RGW is executed to write this result to the register in the next cycle, and an execution end ENDI is issued. During this time, stage 2 is placed in a stopped state. In the third stage, after receiving the address conversion DAT2 of the second cycle of the instruction (2), the NOP is executed since the instruction bone from the second stage is not passed.

When the register write RGW of the result of the execution EX■ of the instruction ■ is completed in the fourth stage, the register write flag 12 is reset, and therefore the conflict detection signal C0NF
is also turned off.

Therefore, after the end of the fourth stage ENDI, the processing of the second stage is restarted, and the address calculation A of the second cycle of the instruction
2, and in this address calculation, read the contents of the register written in the fourth stage of the preceding instruction ■,
Correct processing of reading the execution result of the preceding instruction (2) from the register can be performed.

Thereafter, after address conversion is similarly performed in the third stage, instruction (2) is executed in the fourth stage.

Since this instruction (2) is an instruction that does not involve a register write, an execution end ENDI is performed after the instruction execution (EX), and then an execution EX (2) for the subsequent instruction (2) is performed.

Incidentally, in the above embodiment, the case where stages 1 to 4 are divided into two cycles and executed is taken as an example.
N may be an appropriate number of cycles greater than or equal to 2.

[Effects of the Invention] As described above, according to the present invention, when transferring control to the register write stage, the register write flag for conflict detection is set and the register read address and register write address match. In order to detect conflict friction and interlock the register read stage, all that is required is to add an interlock function to the conflict detection signal to the firmware that controls the pipeline. By simply adding hardware, register conflicts can be detected in real time without complicating pipeline control, and pipeline control can be performed to avoid conflicts.

In addition, the register write flag used for conflict detection is set at the timing when control is transferred to the register write stage, so the register write timing in the register write stage is not subject to any restrictions and there is no need to be aware of conflict detection. It is possible to secure a high degree of freedom in writing registers at will without having to do so.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the principle of the present invention; Fig. 2 is a block diagram of an embodiment of the present invention; Fig. 3 is a block diagram of a stage control circuit of the present invention; Fig. 4 is an operation timing chart of the present invention; Fig. 5 6 is a diagram illustrating a conventional pipe chain control system that generates register conflict; FIG. 6 is an explanatory diagram of a conventional pipe chain control system. In the figure, 10-1: 1st stage (decoding) 10-2: 2nd stage (address calculation section; read stage) 10-3-: 3rd stage (address translation section) 10-4
: 4th stage (execution unit; write stage) 12 register write flag 12-1: Flag register 14: Conflict detection unit (circuit) 16: System storage (C5) 18.3236: AND gate 20, 2g, 34. 38:D-F F242230
: OR gate

Claims (1)

[Claims] (1) Among the multiple stages (10-1 to 10-4) that continuously process instructions in multiple stages, there is a read stage (10-2) that reads a general-purpose register, and a read stage (10-2) that reads a general-purpose register.
A write stage (10-4) for writing general-purpose registers is provided after the stage (10-4), and each stage (10-2)
In a processor pipeline control system that divides the execution of instructions (10-4) into two or more N cycles, this is set when the execution is transferred to the write stage (10-4), and -4) and the register write flag (12) that is reset upon completion of write to the external register; Compare each register address of the write stage (10-2) and the write stage (10-4), and determine whether both addresses are the same. and when the register write flag (12) is set, conflict detection means (14) detects a register conflict and stops execution of the second stage until the register write is completed.
) and ; A pipeline control method characterized by comprising: