JPH0326588B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for testing a three-party communication device that can economically and accurately test a three-party communication device connected to a digital switching system. .

Prior Art and Problems As is well known, a typical telephone call is a two-party conversation in which a calling party and a called party are connected through a network of exchanges. On the other hand, a three-way call is a call between three parties by connecting a three-way call device to a network of exchanges and connecting the three parties via the three-way call device. This three-way communication device has three input terminals and three
It has an output terminal and includes an adder circuit inside, and is tested at predetermined intervals to monitor the normality of its operation. Conventionally, this test was generally performed by maintenance personnel using the manual connection test function in the switchboard to perform voice confirmation, but recently, tone signals from a tone generator are input into a three-way communication device. This is done by receiving tone signals synthesized in a three-way communication device by a receiver.

In testing such three-way communication equipment, MF
(Multi-Frequency Signal) In order to receive and detect the signals synthesized by the three-way communication device using a receiver, the input signal to the three-way communication device must be a single-frequency signal. Therefore, a single frequency sound source is required. Since such a single-frequency sound source is not provided in an ordinary exchange, it has the disadvantage that it must be added only for testing three-way communication equipment. Furthermore, noise and intermittent failures that are lower than the detection accuracy of the receiver cannot be detected. In other words, even if the input tone signal is temporarily interrupted, the receiver is operating normally if it immediately returns to normal, so even if the input tone signal is interrupted due to an intermittent failure, it cannot be detected. There were flaws.

OBJECTS OF THE INVENTION It is an object of the present invention to enable accurate testing of a three-way communication device connected to a digital switching system without adding any special configuration.

Structure of the Invention The present invention tests a three-way communication device under the control of a processor, and transmits and receives control information between a time switch that changes time slots and a processor using a designated time slot. a transmitted signal memory and a received signal memory;
In a digital switching system including a multiplexer and a three-way communication device connected via a demultiplexer, three pieces of test information are written from the processor to the transmission signal memory, and the three pieces of test information are read from the transmission signal memory. The test information is read into each designated time slot and inputted to the three input terminals of the three-way communication device via the demultiplexer, and the test information is synthesized and output from the output terminal by the three-way communication device. writing the synthesis information to the received signal memory via the multiplexer, the processor reading the synthesis information from the reception signal memory,
The information to be originally output from the three-way communication device based on the test information is compared and verified with the composite information, and an embodiment will be described in detail below.

Embodiment of the Invention FIG. 1 is a block diagram of main parts of an embodiment of the present invention, in which a digital network NW writes information from a processor CPU and sends it to a terminal device such as a telephone at a designated time slot. It has a first memory SSM for transmitting information, and a second memory RSM in which information such as status information of a terminal device such as a telephone is transferred and written in a designated time slot and read out by the processor CPU. It also includes a configuration for exchanging time slots using a time switch, a space switch, etc. (not shown).

The three-way communication device TWT also includes a decoder DEC that converts the PCM signal compressed according to the companding law such as μ-law or A-law into a linear code, and an adder as shown in FIG. 2. It consists of a circuit ADD and a coder COD that compresses a linear code according to the companding law, and the signals input to input terminals a, b, and c are as follows:
The decoder DEC exchanges it into a linear code, and the adder circuit ADD adds it to the coder COD.
The data is compressed again according to the companding law and output from output terminals d, e, and f. That is, the adder circuit ADD
In this case, as shown by the solid line, dotted line, and chain line, addition is performed on the signals of the two input terminals (which can be realized with a simple OR circuit), so the input signals of input terminals b and c are added to the output terminal d. are combined and output, the input signals of input terminals a and c are combined and output to output terminal e, and the input signals of input terminals a and b are combined and output to output terminal f. become.

During testing, test data is written from the processor CPU to the memory SSM, read out at a designated time slot, and input to input terminals a, b, and c of the three-way communication device TWT. For example, input a certain pattern of test data only to input terminal a, and input silent data to other input terminals b and c.
When data is written from the processor CPU to the area corresponding to the input terminal of the memory SSM, this data is read out at a specific time slot and sent to the three-way communication device.
The silent data is input to the TWT, and the silent data is output to the output terminal d of this three-way communication device TWT, and the test data input to the input terminal a is output to the output terminals e and f.

The output signals of the respective output terminals d, e, f of the three-way communication device TWT are written into the areas corresponding to the output terminals of the second memory RSM. The processor CPU reads the contents of this memory RSM and connects it to the three-way communication device.
By comparing and verifying that the output signal at output terminal d of the TWT is silent data and the output signals at output terminals e and f are test data, the three-way communication device
TWT will be determined to be normal.

As mentioned above, test data is input only to a specific input terminal a of the three-way communication device TWT, silent data is input to the other input terminals b and c, and data is input from the output terminal d corresponding to the specific input terminal a. Test data is output from output terminals e and f corresponding to other input terminals b and c, and is written to the second memory RSM corresponding to each output terminal d, e and f. , the contents of this second memory RSM are processed by the processor.
By comparing and checking the data read by the CPU, it is possible to easily determine the normality of the three-way communication device TWT, but it is of course possible to use other test data instead of silent data. In other words, with respect to the data input to the three-way communication device TWT, the data that should originally be output to the output terminal is known in advance, so the processor CPU can distinguish between the data that should be output and the data that was actually output. You can easily compare and check with

FIG. 3 is a more detailed block diagram of an embodiment of the present invention, where TWT is a three-way communication device, a, b, c.
and d, e, f are input terminals and output terminals corresponding to the three-way communication device shown in Fig. 2, MPX1, MPX2
is a multiplexer, PTS is a primary time switch,
SSW is a spatial switch, STS is a secondary time switch,
RSM is a received signal memory, i.e. a second memory;
SSM is a transmit signal memory, i.e. a first memory;
PTC is primary time switch control memory, STC is secondary time switch control memory, SWC is spatial switch control memory, SRD is signal reception distribution device, CPU
is a processor, and DMPX1 and DMPX2 are demultiplexers.

The primary time switch PTS is a random write,
Sequential read, secondary time switch STS
The following describes the case of a sequential write and random read configuration. The primary time switch PTS can be used for sequential write and random read, and the secondary time switch STS can be used for random write and
Of course, sequential reading is also possible.

The primary time switch PTS is written with a signal from the multiplexer MPX2 according to the write address read from the primary time switch control memory PTC, and read out with a sequential address from a sequential address generator (not shown). . Further, the secondary time switch STS is written in accordance with the sequential address from the sequential address generator and read out in accordance with the read address read out from the secondary time switch control memory STC. In the spatial switch SSW, the crosspoint switch is controlled according to the address read from the spatial switch control memory SWC.

Addresses and control information according to the exchange connection information are written from the processor CPU to the primary time switch control memory PTC, the secondary time switch control memory STC, and the space switch control memory SWC via the signal reception and distribution device SRD. This control information indicates whether to control writing and reading of the primary time switch PTS and secondary time switch STS, or whether to control the received signal memory RSM and the transmitted signal memory SSM. , is written according to the write address read from the primary time switch control memory PTC, and is read according to the sequential address to perform time slot exchange, and spatial exchange is performed by controlling the cross point of the spatial switch SSW. The secondary time switch is controlled by a sequential address.
Written to STS, secondary time switch control memory
The time slots are read and time slots are exchanged according to the read address read from the STC. Also, since call information, etc. is transmitted by a specific time slot, the signal of this specific time slot is written into the received signal memory RSM by the primary time switch control memory PTC, and then sent to the signal reception distribution device SRD.
is transferred to the processor CPU via Further, a specific control signal is written into the transmission signal memory SSM from the processor CPU via the signal reception and distribution device SRD, and is sent out at a specific time slot.

In a three-party call, the call signal from the three parties read from the secondary time switch STS is demultiplexed.
Three-way communication device via DMPX2 and DMPX1
The signals applied to TWT by time slots TSi, TSj, and TSk and combined by the three-way communication device TWT are applied to the primary time switch PTS via multiplexers MPX1 and MPX2, and are applied to the spatial switch SSW and the secondary time switch STS. to each subscriber. Also, speech signals from each subscriber are applied to the three-way communication device TWT via the primary time switch PTS, the spatial switch SSW, the secondary time switch STS, and the demultiplexers DMPX2 and DMPX1.

When testing the three-way communication device TWT, the processor
A control signal and a write address and a read address for using the three-way communication device TWT are written from the CPU to the primary time switch control memory PTC and the secondary time switch control memory STC via the signal reception distribution device SRD. Also, test data is added to the transmission signal memory SSM from the processor CPU via the signal reception distribution device SRD. The test data corresponding to input terminals a, b, and c of the three-way communication device TWT are α,
When β and γ are assumed, they are written to the transmission signal memory SSM, for example, as shown in the figure. This test data α, β,
γ is read out to time slots TSi, TSj, and TSk, for example, by the read address written in the secondary time switch control memory STC.

The test data α, β, γ read out from the transmission signal memory SSM are sent to the demultiplexer DMPX2,
The combined signals A, B,
C is a multiplexer from output terminals d, e, f
Primary time switch via MPX1 and MPX2
Added to PTS and received signal memory RSM. A write address for accessing the received signal memory RSM is written in the primary time switch control memory PTC by a control signal, and the signals from the output terminals d, e, f of the three-way communication device TWT are transferred to the time slot.
If TSi', TSj', and TSk' are output from multiplexer MPX2, then the time slots TSi',
By the write address read from the primary time switch control memory PTC at the timing corresponding to TSj', TSk', the received signal memory is
Signals A, B, and C are written to RSM. These signals A, B, and C are transferred to the processor CPU via the signal reception distribution device RSD and stored in the transmission signal memory.
A comparison is performed to check the relationship with the test data α, β, and γ written in the SSM, and the three-way communication device
TWT normality testing is performed.

As mentioned above, if test data β and γ are silent data, signal A is silent data, and signals B and C are test data α. If signal A includes data other than silent data, and if signals B and C include data other than test data α, it is determined that the three-way communication device TWT is abnormal.

FIG. 4 is an explanatory diagram of the time slot, in which test data α, β, γ are transmitted from the transmission signal memory SSM.
Read to time slots TSi, TSj, TSk,
It is applied to input terminals a, b, and c of the three-way communication device TWT via demultiplexers DMPX2 and DMPX1. That is, in order to specify these time slots TSi, TSj, and TSk from the processor CPU, a read address is written into the secondary time switch control memory STC, and this read address causes the test data α, β, and
γ will be read out to time slots TSi, TSj, and TSk. Also, since the other time slots are used for normal call signals, they do not interfere with other calls for testing the three-way communication device TWT.

Figure 5 shows the processor that collates the test data.
This is a block diagram of the main parts of the CPU, and test data α,
β, γ are transferred to the transmission signal memory SSM via register REG1, signals A, B, C read out from reception signal memory RSM are set in register REG2, and test data α, β set in register REG1. , γ are added to the logical operation circuit LOG to perform calculations of β+γ, α+γ, and α+β, and the results of these calculations and the signals A, B, and C set in the register REG2 are applied to the collation circuit COMP to be compared. And A=β+γ, B=α+γ, C
In the case of =α+β, a signal DS indicating a matching match is output, and it is determined that the three-way communication device TWT is normal. By configuring the matching circuit COMP to perform bit-based matching, it is also possible to output a matching result signal indicating which bit position has an error. Note that the processor can be used without any special hardware configuration.
It is also possible to determine this using CPU software.

Effects of the Invention As explained above, the present invention provides a three-way communication device.
Since there is no need to add special equipment for TWT testing, testing can be done economically, and
Even if a fault such as a bit error occurs, it can be easily detected. Conventional testing methods have been unable to detect such faults such as one-bit errors. Also, depending on the bit error position,
Since it becomes possible to point out failure points to a certain extent, test accuracy improves. Furthermore, intermittent failures can be reliably detected by repeated tests using test data.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the main parts of an embodiment of the present invention, Fig. 2 is a block diagram of main parts of a three-way communication device, Fig. 3 is a more detailed block diagram of the embodiment of the invention, and Fig. 4 is a time stamp. FIG. 5, which is an explanatory diagram of the rotor, is a block diagram of the main part of the configuration for collating test data. NW is a digital network, TWT is a three-way communication device, DEC is a decoder, ADD is an adder circuit,
COD is a coder, MPX1 and MPX2 are multiplexers, PTS is a primary time switch, SSW is a spatial switch, STS is a secondary time switch, RSM is a received signal memory, i.e., the second memory, and SSM is a transmitted signal memory, i.e., the first Memory, PTC is primary time switch control memory, STC is secondary time switch control memory, SWC is spatial switch control memory,
SRD is a signal reception distribution device, CPU is a processor,
DMPX1 and DMPX2 are demultiplexers.

Claims (1)

[Scope of Claims] 1. A time switch for exchanging time slots, a transmission signal memory and a reception signal memory for transmitting and receiving control information to and from a processor using designated time slots, and a multiplexer and a demultiplexer. In a digital switching system including a connected three-way communication device, three pieces of test information are written from the processor into the transmission signal memory, and the three pieces of test information are written from the transmission signal memory into respective designated time slots. The test information is read out and input to the three input terminals of the three-way communication device through the demultiplexer, and the combined information from the output terminal where the test information is synthesized and output by the three-way communication device is sent to the multiplexer. The processor reads the combined information from the received signal memory, and compares the combined information with information that should originally be output from the three-way communication device based on the test information. A method for testing a three-party communication device characterized by verification.