JPH03265251A - Line address scanning circuit - Google Patents

Abstract

PURPOSE:To reduce the scan time of a priority line by latching an interruption signal of the priority line at scan of a non-priority line address and reading an interruption signal latched at the scan of the priority line address at a fast speed. CONSTITUTION:When a most significant bit MSB of a signal line 14 is '0', an interruption signal from a non-priority line is fed to a processor via a signal line 16 and an interrupt signal from a priority line scanned by a line adaptor is given to a read write control circuit 5 via a signal line 21 and the interrupt request for each line is written in an interruption latch register 4 via signal lines 181-18n. On the other hand, when the MSB bit represents logical '1b, a selector 3 selects a signal line 20 and the read write control circuit 5 outputs an interruption request of a priority line written in the interruption latch register 4 according to a high speed clock to a signal line 20 and sent to a processor via a signal line 16.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a line address scan circuit, particularly a top level (MS)
B) Two bits differing only in other bits or at the same address
The present invention relates to a line address scanning circuit provided in a communication control device to control a line adapter accommodating a group of lines.

[Conventional technology]

Conventionally, this type of line address scanning circuit has been equipped with a counter for sequentially outputting line addresses at a constant speed and a counter for scanning and monitoring all lines at a constant speed, and a counter for outputting line addresses sequentially at a constant speed, and a counter for scanning and monitoring all lines at a constant speed. and means for selecting an interrupt signal to be output to the processing section.

[Problem to be solved by the invention]

The conventional line address scan circuit described above originally
Two lines that differ only in the B bit are connected to a terminal, and the terminal gives priority to the line with the MSB bit of ``1°'' (hereinafter referred to as the upper line), and the line with the MSB bit of ``O'' to the lower line. However, since the scan of the upper line side and the scan of the lower line side are performed serially, the upper line is treated equally without priority in the address scan, and the upper line The drawback is that there is considerable waiting time for the interrupts from to be transmitted.

[Means to solve the problem]

The line address scan circuit of the present invention accommodates two priority and non-priority lines with the same address from each terminal, and each line has an interrupt signal to the processor and controls an independently controlled line adapter. In the line address scan circuit provided in the communication control device, there is a line address counter that generates a line address for scanning interrupts from the line, and a line address counter that generates a line address for scanning interrupts from the line, and a line address counter that is used during processing on the non-priority line side to update this line address scanter. A first sector that selects and provides a high-speed clock when processing a low-speed clock on the priority line side, and provides an interrupt signal to the processor by selecting an interrupt request on the priority line side and an interrupt request on the non-priority line side. a second selector; and an interrupt holding means that holds an interrupt request on the priority line side when scanning the non-priority line side, reads out the interrupt request held when scanning the priority line side, and supplies it to the second selector. By having W! be reprimanded.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, showing a low-speed clock signal line 11 and a high-speed clock signal line 1 from a processor.
2 is connected to the selector 2, and the selector 2 is connected to the line address counter 1 via an output signal line 13. The MSB bit of line address counter l is signal line 1
The bits other than the MSB bit of the line address counter 1 are connected to the read/write control circuit 5 and the line adapter via a signal line 15. ing. The selector 3 is connected to the processor via a signal line 16 and to a line adapter via a signal line 17. Further, the read/write control circuit 5 is connected to the line adapter via the signal line 21, and the signal lines 18□ to 18. and signal line 19+
~19. .

It is connected to the interrupt holding register 4 via. Furthermore, the interrupt holding register 4 is connected to the selector 3 via a signal line 20.

Selector 2 is for selecting the input clock of line address counter 1, and the MSB bit of line address counter 1 is “
O”, selects the low-speed clock signal line 11 and selects the MSB
When the bit is 1'', the high speed clock signal line 12 is selected and outputted to the signal line 13.The line address counter 1 is a +1 counter that counts up with the clock input from the signal line 13, and as described above, the MSB bit is The other outputs are output to the line adapter via the signal line 15, and the MSB
The bit is output to the signal line 14 as a signal for switching between processing on the priority line side and processing on the non-priority line side. Selector 3
is for selecting an interrupt signal, and M of line address counter 1
When the SB bit is "O"', the interrupt signal 17 on the non-priority line side is selected, and when the MSB bit is "1P", the interrupt signal line 20 on the priority line side is selected and output to the signal line 16. The interrupt register 4 is a register for holding interrupt signals on the priority line side for each line, and has n-bit flags for the number of lines n.Read/write control circuit 5
is used to control the interrupt register 4, and when the MSB bit of the line address counter 1 is "'0", the signal line which is the interrupt signal on the priority line side is placed in the bit position corresponding to the line address indicated by the signal line 15. Write the value of 21. At this time, signal lines 181-18° are used for writing for each line address. Further, when the MSB bit of the line address counter 1 is "'1'°," a read operation is performed from the interrupt holding register 4, and the value at the bit position corresponding to the line address indicated by the signal line 15 is output to the signal line 20. At this time, the signal lines 19 to 19Il are used for reading out each line address.

FIG. 2 is a time chart showing an example of each signal during the operation of FIG. 1, and the operation of FIG. 1 will be explained below with reference to FIG.

When scanning a non-priority line where the MSB of line address counter 1 is "O", a low-speed clock is input from signal line 11 to line address counter 1 via selector 2, and M
When scanning the priority line side with SB '1', signal line 1
2, a high-speed clock is input to the line address counter 1 via the selector 2. According to the line address outputted from the line address counter 1 to the line adapter via the signal line 15, non-priority and priority lines from "1" to "n" are scanned in the line adapter. At this time, when the MSB bit indicated by the signal line 14 is "O", processing is performed on the non-priority line side, and when the MSB bit is "1", processing is performed on the priority line side. In other words, when the MSB bit is "'' When it is 0, the selector 3 selects the signal line 17 and sends the interrupt signal from the non-priority line to the processor via the signal line 16, and furthermore, the interrupt signal from the priority line scanned by the line adapter is sent to the signal line 21. are applied to the read/write control circuit 5 via signal lines 181-18. An interrupt request for each line is written to the interrupt holding register 4 via the interrupt holding register 4. On the other hand, when the MSB bit is "1", the selector 3 selects the signal line 20, and the read/write control circuit 5 transmits the priority line interrupt request written in the interrupt holding register 4 to the signal line 20. output according to high-speed clock,
It will be sent to the processor via the signal line 16.

[Effects of the Invention] As explained above, the line address scanning circuit of the present invention holds the priority line side interrupt signal when scanning the non-priority line side address, and uses this held interrupt signal when scanning the priority line side address. By reading signals at high speed, the scan time on the priority line side can be shortened and line processing efficiency can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
5 is a time chart showing an example of each signal during the operation shown in the figure. 1... Line address counter, 2.3... Selector, 4... Interrupt holding register, 5... Read/write W circuit.

Claims (1)

[Claims] A line provided in the communication control device to accommodate two priority and non-priority lines with the same address from each terminal, and each line has an interrupt signal to the processor and controls the line adapter which is controlled independently. In the address scan circuit, there is a line address counter that generates a line address for scanning interrupts from the line, and a low-speed clock is used during processing on the non-priority line to update this line address counter. a first sector that selects and provides a high-speed clock, a second selector that selects and provides an interrupt request to the processor between an interrupt request on the priority line side and an interrupt request on the non-priority line side; A line address scan circuit characterized by having an interrupt holding means for holding an interrupt request on a priority line side during scanning, reading out the interrupt request held during scanning on the priority line side, and applying it to the second selector. .