JPH03265121A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03265121A
JPH03265121A JP6510190A JP6510190A JPH03265121A JP H03265121 A JPH03265121 A JP H03265121A JP 6510190 A JP6510190 A JP 6510190A JP 6510190 A JP6510190 A JP 6510190A JP H03265121 A JPH03265121 A JP H03265121A
Authority
JP
Japan
Prior art keywords
film
wafer
main surface
exposure
reverse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6510190A
Other languages
Japanese (ja)
Inventor
Ayako Matsui
松井 亜也子
Kazunori Imaoka
今岡 和典
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6510190A priority Critical patent/JPH03265121A/en
Publication of JPH03265121A publication Critical patent/JPH03265121A/en
Pending legal-status Critical Current

Links

Landscapes

  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To improve the resolution and dimension accuracy in exposure of photolithography by forming films of nearly the same thickness, respectively, on the obverse and the reverse of a substrate, and stacking a protective layer on the obverse, and etching the film at the reverse so as to expose the flat face, and then installing a vacuum chuck. CONSTITUTION:SiO2 films and films 3 are formed, in nearly the same thicknesses, on each of the obverse and the reverse of an Si substrate, and further a resist to become a protective film is stacked on the obverse side, and the films 2 and 3 on the reverse side are etched until the flat face is exposed. Next, the film 4 is removed, and an organic photosensitive film 5 is applied, and then a vacuum chuck 6 is installed, and by photolithography method the film 5 is exposed and baked to form a pattern. By this method, the partial thickness value 13 becomes large synthetically without polishing the reverse, and the resolution and dimension accuracy in exposure is elevated, and minute pattern is made.

Description

【発明の詳細な説明】 〔概要〕 半導体装置の製造方法に関し、特に半導体ウェハにフォ
トリソグラフィを施す際の微細パターンを形成する方法
に関し、ウェハ裏面に研磨剤やダストが付着しないよう
に効率良くウェハ裏面を平坦化し、露光領域のLTVを
小さく抑えて、かつウェハ裏面の凸凹による露光フォー
カスのずれや露光の不均一化を防止して安定した解像度
及び転写パターンの寸法精度が得られる方法を提供する
ことを目的とし、半導体基板の第1の主面上に膜を形成
し、該膜の上に感光性レジスト膜を形成し、前記半導体
基板の第1の主面に対向する第2の主面を支持具の平坦
面に密着させた状態で露光を行う半導体装置の製造方法
に右いて、第2の主面が平坦な半導体基板(1)の第2
の主面と第1の主面上Gこ厚さが略一様な膜を少なくと
も1層以上形成する工程と、第1の主面上に形成した膜
上に保護膜(4)を形成する工程と、第2の主面上の膜
を半導体基板と同程度に平坦な面が出るまで選択的にエ
ツチング除去する工程と、しかる後、該保護膜(4)を
除去した後、前記第1の主面側に被着・形成した膜(3
)上に感光性レジスト膜(5)を形成し、該半導体基板
(1)の前記第2の主面側を前記支持具(6)の平坦面
に密着させるように保持して露光を行う工程とを含むよ
うに構成する。
[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, particularly regarding a method for forming a fine pattern when photolithography is applied to a semiconductor wafer, the wafer can be efficiently processed to prevent abrasives and dust from adhering to the back surface of the wafer. To provide a method in which stable resolution and dimensional accuracy of a transferred pattern can be obtained by flattening the back surface, suppressing the LTV of the exposure area to a small value, and preventing shifts in exposure focus and non-uniform exposure due to unevenness on the back surface of the wafer. A film is formed on a first main surface of a semiconductor substrate, a photosensitive resist film is formed on the film, and a second main surface opposite to the first main surface of the semiconductor substrate is formed. According to a method of manufacturing a semiconductor device in which exposure is performed while the semiconductor substrate (1) is in close contact with the flat surface of the support, the second main surface of the semiconductor substrate (1) is
forming at least one layer of a film having a substantially uniform thickness on the main surface and the first main surface; and forming a protective film (4) on the film formed on the first main surface. a step of selectively etching away the film on the second main surface until a surface as flat as that of the semiconductor substrate is exposed; and then, after removing the protective film (4), The film (3) adhered and formed on the main surface side of
) A step of forming a photosensitive resist film (5) on the semiconductor substrate (1) and performing exposure while holding the second main surface side of the semiconductor substrate (1) in close contact with the flat surface of the support (6). Configure it to include.

〔産業上の利用分野] 本発明は、半導体装置の製造方法に関し、特に半導体ウ
ェハにフォトリソグラフィを施す際の微細パターンを形
成する方法に関する。
[Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a fine pattern when photolithography is applied to a semiconductor wafer.

近年の半導体装置の製造方法の高集積化の要求に伴い、
半導体ウェハに微細パターンを形成できるフォトリソグ
ラフィ工程が求められている。その工程の中でもウェハ
表面に塗布された感光性レジスト膜に所定のパターンを
焼きつける露光工程はパターンの精度を向上させる上で
特に重要な工程である。露光工程はウェハ表面に焦点を
合わせてパターンの焼きっけが行われるが、その際表面
に凸凹が存在すると、焦点を合わせにくくなってしまう
。半導体ウェハの半導体素子を形成すべき面にさまざま
な膜を成長させるウェハプロセスにおいて、特に、CV
D膜を成長させた場合、ウェハ裏面は回り込むガスの流
量を一定にできないため、膜の面内分布が不均一に形成
されやすくウェハ周辺に異常成長しやすい。従って、特
にウェハ裏面に形成した膜の膜厚のばらつきがプロセス
が進むにつれてウェハ表面より大きくなる。それに加え
て、ウェハ裏面はウェハ表面にさまざまな膜を成長させ
る際に発生するダストも付着しているので凸凹がより生
しやすい。この様子を示したものが第2図(a)である
。同図では上がウェハ表面10で下がウェハ裏面11で
ある。尚、この図では半導体ウェハ内部については省略
し、表面状態を表す断面図を示しである。フォトリソグ
ラフィ工程においては、平坦な真空チャック上にウェハ
を搬送し、該ウェハを真空吸着して露光を行う構成にな
っているため、ウェハ裏面に以上述べた原因による凸凹
が存在すると、真空チャックにウェハを吸着させた際、
ウェハ裏面の凸凹がウェハ表面に転写される。従って、
たとえウェハ表面側が−様な厚さに膜がついていてもウ
ェハ裏面の凸凹がウェハ表面に反映されてしまいウェハ
表面が凸凹になってしまう。もちろん、もともとウェハ
表面に凸凹が存在すればウェハ表面の凸凹はさらに大き
くなってしまう。例えば、ウェハ表面にCVDポリシリ
コン膜を4000人程度成長させた場合、真空チャック
6に固定する前の第2図(a)においてウェハ表面側の
膜厚分布を表す凸凹の差の絶対値、すなわちLTV (
Loca I  Th1ckness  Value)
13は約o・8μmであるのに対して、第2図(b)の
ようにウェハ裏面を真空チャック6に吸着させるとLT
V13は約1.8μmになりウェハ表面の凸凹をより大
きくしてしまう。このようにウェハ表面の凸凹がひどく
なると、露光領域内での焦点の合う深さの許容範囲、す
なわち被写体深度1.5μm内にLTVがおさまらなく
なり、露光領域内に焦点のあわない部分ができて露光は
けが生ずる。従って、転写パターンの解像度が低下し、
また転写パターンの寸法が不均一になるのでウェハ上に
微細パターンを形成するのが困難になる。これは、素子
の微細化を進める上で問題となり何らかの解決策が望ま
れる。
With the recent demand for higher integration in semiconductor device manufacturing methods,
There is a need for a photolithography process that can form fine patterns on semiconductor wafers. Among these steps, the exposure step of printing a predetermined pattern on a photosensitive resist film coated on the wafer surface is a particularly important step for improving pattern accuracy. In the exposure process, a pattern is baked by focusing on the wafer surface, but if there are irregularities on the surface, it becomes difficult to focus. In wafer processes in which various films are grown on the surface of a semiconductor wafer on which semiconductor elements are to be formed, CV
When the D film is grown, since the flow rate of the gas that goes around the back surface of the wafer cannot be made constant, the in-plane distribution of the film tends to be uneven and abnormal growth tends to occur around the wafer. Therefore, in particular, as the process progresses, the variation in film thickness of the film formed on the back surface of the wafer becomes larger than that on the front surface of the wafer. In addition, dust generated when various films are grown on the wafer surface is also attached to the back surface of the wafer, so unevenness is more likely to occur. This situation is shown in FIG. 2(a). In the figure, the top side is the wafer front surface 10, and the bottom side is the wafer back side 11. In this figure, the interior of the semiconductor wafer is omitted, and a cross-sectional view showing the surface state is shown. In the photolithography process, the wafer is transported onto a flat vacuum chuck, and the wafer is vacuum-adsorbed for exposure. When adsorbing the wafer,
The unevenness on the back side of the wafer is transferred to the front side of the wafer. Therefore,
Even if the film is deposited on the front side of the wafer to a uniform thickness, the unevenness on the back side of the wafer will be reflected on the front surface of the wafer, resulting in an uneven surface. Of course, if there are any irregularities on the wafer surface, the irregularities on the wafer surface will become even larger. For example, when approximately 4,000 CVD polysilicon films are grown on the wafer surface, the absolute value of the difference between the unevenness representing the film thickness distribution on the wafer surface side in FIG. 2(a) before being fixed to the vacuum chuck 6, LTV (
Loca I Th1ckness Value)
13 is about 0.8 μm, whereas when the back surface of the wafer is attracted to the vacuum chuck 6 as shown in FIG. 2(b), the LT
V13 is about 1.8 μm, which makes the wafer surface even more uneven. When the unevenness of the wafer surface becomes severe in this way, the LTV cannot be kept within the allowable range of the depth of focus within the exposure area, that is, the depth of field is 1.5 μm, and out-of-focus areas are created within the exposure area. Exposure will cause scratches. Therefore, the resolution of the transferred pattern decreases,
Furthermore, since the dimensions of the transferred pattern become non-uniform, it becomes difficult to form fine patterns on the wafer. This becomes a problem in advancing the miniaturization of elements, and some kind of solution is desired.

〔従来の技術] このため従来は、一つの方法として露光する前にあらか
しめウェハ裏面を研磨して平坦化しておく方法(特開昭
62−26814号)等が提案されていた。
[Prior Art] For this reason, conventionally, a method has been proposed in which the back surface of the wafer is polished and flattened before exposure (Japanese Patent Laid-Open No. 62-26814).

〔発明が解決しようとする課題] しかし、この方法ではウェハ裏面を研磨する際研磨剤を
用いるので、ウェハ裏面にこの研磨剤が付着し、さらに
この研磨により2次的に発生したダストがウェハ表面に
付着してしまうという不都合があった。従って、この研
磨剤やダストを落とすためにウェハ表面を洗浄する必要
があり、さらに個々のウェハの凹凸の度合いによってウ
ェハを一枚一枚研磨するために研磨時間がかかりスルー
プットが悪くなってしまう。
[Problems to be Solved by the Invention] However, since this method uses an abrasive when polishing the back side of the wafer, this abrasive adheres to the back side of the wafer, and furthermore, the dust generated secondary to this polishing is transferred to the wafer surface. There was an inconvenience that it would stick to the surface. Therefore, it is necessary to clean the wafer surface to remove the abrasive and dust, and furthermore, depending on the degree of unevenness of each wafer, it takes time to polish each wafer one by one, resulting in poor throughput.

本発明は、ウェハ裏面に研磨剤やダストが付着しないよ
うに効率良くウェハ裏面を平坦化し、露光領域のLTV
を小さく抑えて、かつウェハ裏面の凸凹による露光フォ
ーカスのずれや露光の不均一化を防止して安定した解像
度及び転写パターンの寸法精度が得られる方法を提供す
ることを目的とする。
The present invention efficiently flattens the back surface of the wafer to prevent abrasives and dust from adhering to the back surface of the wafer, and improves the LTV of the exposed area.
It is an object of the present invention to provide a method in which stable resolution and dimensional accuracy of a transferred pattern can be obtained by suppressing the exposure to a small value and preventing deviations in exposure focus and non-uniformity of exposure due to irregularities on the back surface of a wafer.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、半導体基板の第1の主面上に膜を形成し、該
膜の上に感光性レジスト膜を形成し、前記半導体基板の
第】の主面に対向する第2の主面を支持具の平坦面に密
着させた状態で露光を行う半導体装置の製造方法におい
て、第2の主面が平坦な半導体基+F!、(1)の第2
の主面と第1の主面上に厚さが略一様な膜をルなくとも
1層以上形成する工程と、第1の主面上に形成した膜上
に保護膜(4)を形成する工程と、第2の主面上の膜を
半導体基板と同程度に平坦な面が出るまで選択的にエツ
チング除去する工程と、しかる後、該保護膜(4)を除
去した後、前記第1の主面側に被着・形成した膜(3)
上に感光性レジスト膜(5)を形成し、該半導体基板(
1)の前記第2の主面側を前記支持具(6)の平坦面に
密着させるように保持して露光を行う工程とを含むよう
に構成する。
The present invention includes forming a film on a first main surface of a semiconductor substrate, forming a photosensitive resist film on the film, and forming a second main surface opposite to the main surface of the semiconductor substrate. In a method for manufacturing a semiconductor device in which exposure is performed in close contact with a flat surface of a support, a semiconductor substrate +F! having a flat second principal surface is used. , the second of (1)
forming at least one layer of substantially uniform thickness on the main surface and the first main surface; and forming a protective film (4) on the film formed on the first main surface. a step of selectively etching the film on the second main surface until a surface as flat as that of the semiconductor substrate is exposed; and then, after removing the protective film (4), Film (3) adhered and formed on the main surface side of 1
A photosensitive resist film (5) is formed on the semiconductor substrate (
1) of holding the second main surface side in close contact with the flat surface of the support (6) and performing exposure.

[作用] 本発明ではパターンを焼きつける前にエツチング法を用
いてウェハ裏面の膜を除去している。従って、研磨によ
ってウェハ裏面を平坦化する従来法と比べてウェハ表面
に研磨剤やダストが付着しない。すなわち、発塵を伴わ
ない方法でウェハ裏面に平坦な面を表出させて、ウェハ
裏面のばらつきによるウェハ裏面のLTVに対する影響
をなくし、ウェハ表面のLTVを小さく抑えることがで
きる。従って、露光極小領域での被写体深度の範囲内に
LTVがおさまり焦点ぼけがなくなる。
[Operation] In the present invention, the film on the back surface of the wafer is removed using an etching method before the pattern is printed. Therefore, compared to the conventional method in which the back surface of the wafer is flattened by polishing, abrasives and dust do not adhere to the wafer surface. That is, it is possible to expose a flat surface on the back surface of the wafer using a method that does not involve dust generation, eliminate the influence of variations in the back surface of the wafer on the LTV of the back surface of the wafer, and suppress the LTV of the front surface of the wafer to a small value. Therefore, the LTV falls within the range of the depth of field in the minimum exposure area, and defocus is eliminated.

また、本発明は個々のウェハの凹凸の度合いによって一
枚一枚、ウェハ裏面を平坦化する必要はな(、エツチン
グ速度の差を利用してウェハ裏面の膜の選択的な除去が
できるので、−度に数十枚のウェハを処理できる。また
、発塵を伴わないので洗浄する必要もない。従って、本
発明ではスループットも良くウェハ裏面の平坦化を実現
できる。
Furthermore, in the present invention, there is no need to planarize the back surface of each wafer one by one depending on the degree of unevenness of each wafer (because the film on the back surface of the wafer can be selectively removed by using the difference in etching speed, - Several tens of wafers can be processed at a time. Also, since no dust is generated, there is no need for cleaning. Therefore, the present invention has a good throughput and can realize flattening of the back surface of the wafer.

〔実施例〕〔Example〕

第1図は本発明の詳細な説明するための要部断面図であ
る。
FIG. 1 is a sectional view of a main part for explaining the present invention in detail.

第1図(a)参照。See Figure 1(a).

半導体基板として例えば厚さ600μm程度のシリコン
(Si)基板1の両面に厚さ例えば200〜300人程
度の熱酸成長(二酸化シリコン、SiO2)2を形成す
る。この際、熱酸化膜2はSi基板1上を均一に成長す
るため熱酸化膜2の面内分布番よ一定であり、平坦に保
たれている。次に、この熱酸化膜2の上に目的に応して
両面に膜3を形成する。膜3としてはいろいろな例が掲
げられる。例えば、シラン(SiH,)とアンモニアを
含むガス雰囲気中でCVD (Ch em j c a
l  Vapour  Deposition)法を用
いて、窒化シリコン(Si、N4)等の窒化膜を厚さ例
えぽ1000六程度形成する。また、この窒化膜の代わ
りにシランを含むガス雰囲気中で同しCVD法を用いて
ポリシリコンを厚さ1.5μm程度形成する。他にこの
膜3の例としてはシラン(SIH4)とN20を含むガ
ス雰囲気中で同じ< CV D法を用いて5iOzを厚
さ例えば2500〜3000Å程度形成したり、またP
SG膜を1.0um程度形成してもよい。このように、
膜3はそれぞれの目的に応して材質や厚さ等を適宜選択
して形成する。しかし、いずれにしても膜3はCV D
法で形成された膜であるかまたはスパッタリング法によ
る膜なのでウェハの表面も裏面も凸凹が存在し、特にウ
ェハ裏面の凸凹は大きく面内分布が均一ではない。例え
ば、上記ポリシリコンの場合、ウェハ表面のLTV13
Gi0・8μm程度である。ここでウェハを真空チャッ
クに固定すると、前に述べたようにウェハ表面のLTV
は拡大してしまう。このようすを第3図に示す。
Thermal acid growth (silicon dioxide, SiO2) 2 is formed to a thickness of, for example, about 200 to 300 on both sides of a silicon (Si) substrate 1 having a thickness of, for example, about 600 μm as a semiconductor substrate. At this time, since the thermal oxide film 2 grows uniformly on the Si substrate 1, the in-plane distribution number of the thermal oxide film 2 is constant and kept flat. Next, films 3 are formed on both sides of the thermal oxide film 2 depending on the purpose. Various examples can be given for the membrane 3. For example, CVD (Chem j a c a ) in a gas atmosphere containing silane (SiH) and ammonia
A nitride film such as silicon nitride (Si, N4) is formed to a thickness of about 1,000 mm using a vapor deposition method. Moreover, instead of this nitride film, polysilicon is formed to a thickness of about 1.5 μm using the same CVD method in a gas atmosphere containing silane. Other examples of this film 3 include forming 5iOz to a thickness of about 2,500 to 3,000 Å using the same CVD method in a gas atmosphere containing silane (SIH4) and N20, or
The SG film may be formed to a thickness of about 1.0 um. in this way,
The film 3 is formed by appropriately selecting the material, thickness, etc. according to each purpose. However, in any case, the film 3 is CVD
Since the film is formed by a sputtering method or a sputtering method, there are irregularities on both the front and back surfaces of the wafer, and the irregularities on the back surface of the wafer are particularly large and the in-plane distribution is not uniform. For example, in the case of polysilicon, LTV13 on the wafer surface
Gi is about 0.8 μm. At this point, when the wafer is fixed on a vacuum chuck, the LTV of the wafer surface is
will expand. This situation is shown in Figure 3.

第3図(a)はウェハを真空チャックに吸着させる前の
状態を示しており、同図(b)は真空チャックムこ吸着
させた状態を示している。(b)に示すように、(a)
の状態のまま真空チャック6にウェハを吸着させるとウ
ェハ裏面の凸凹がウェハ表面に転写されLTVは1・8
μm程度に拡大する。この表面に有機感光膜5を被着す
ると、有機感光膜5が厚く形成された部分と薄く形成さ
れた部分の差が大きくなり露光の際の被写体深度にLT
Vがおさまらなくなり解像度が低下してしまう。
FIG. 3(a) shows the state before the wafer is attracted to the vacuum chuck, and FIG. 3(b) shows the state after the wafer is attracted to the vacuum chuck. As shown in (b), (a)
If the wafer is attracted to the vacuum chuck 6 in this state, the unevenness on the back side of the wafer will be transferred to the front side of the wafer, and the LTV will be 1.8.
Expand to about μm. When the organic photoresist film 5 is applied to this surface, the difference between the parts where the organic photoresist film 5 is thick and the parts where it is thin becomes large, and the depth of field during exposure increases.
V will not settle down and the resolution will drop.

これは転写パターンの寸法精度を損なう原因となる。This causes loss of dimensional accuracy of the transferred pattern.

第1図(b)参照。See Figure 1(b).

次に、後のウェハ裏面エツチング除去の際生しるダスト
の付着を防止するために、ウェハ表面にのみレジスト4
を塗布する。
Next, in order to prevent the adhesion of dust that would occur during the subsequent etching removal of the backside of the wafer, a resist layer 4 was applied only to the front surface of the wafer.
Apply.

第1図(c)参照。See Figure 1(c).

そして、ウェットエツチングまたはドライエツチングを
施して熱酸化膜2をエツチングストッパーにしてウェハ
裏面の膜3を除去する。ここで、ドライエツチングを施
した場合、膜3がポリシリコンならば熱酸化膜2とのエ
ツチングレート比は20程度あり、膜3が窒化膜ならば
、熱酸化膜2とのエツチングレート比は3〜4程度にな
る。また、膜3がPSGなら熱酸化膜2とのエッチレー
ト比は1〜2程度になる。従って、膜3が窒化膜やPS
Gの場合にはドライエ・ノチングよりもウェットエンチ
ングの方がエッチレート比が得られるので好ましい。窒
化膜ならばリン酸を含む水溶液を用いてウェットエツチ
ングすれば熱酸化膜2に対して数百のエッチレート比が
とれるし、PSG膜ならばフン酸を含む水溶液中かまた
はいわゆるバッフアートフン酸水溶液中でウェットエツ
チングすれば、これも熱酸化膜2に対して数百のエッチ
レート比が得られ、膜3のみを選択的に除去できる。尚
、膜3にSi○2膜3を形成した場合は膜2も5i02
膜なので膜3とSi○2膜2は同時にエツチングされ第
1図(C゛ )のようにウェハ裏面はSi基板が表出す
る。いずれにしてもウェハ裏面は熱酸化膜2か或いはS
i基板1が表出した状態なので平坦化される。但し、熱
酸化膜2は残っていた方がウェハ裏面に傷がつくのを防
げる。尚、この際、熱酸化膜2は窒化膜であってもよい
。すなわち、膜2が膜3をエツチング除去する際のエツ
チングストッパーになればよい。そして、その場合、上
に述べてきたように膜3だけを選択的に除去できるよう
にドライエツチング或いはウェットエンチング等を施し
ウェハ裏面を平坦化すればよい。尚、このエツチング除
去の際、ウェハ表面のレジスト膜4にダストが付着する
可能性がある。しかし、次に示す第1図(d)の工程で
レジスト膜4を除去し、代わりに有機感光膜5を再塗布
するので、この際レジス1−M4に付着したダストは取
り除かれる。
Then, wet etching or dry etching is performed to remove the film 3 on the back surface of the wafer using the thermal oxide film 2 as an etching stopper. Here, when dry etching is performed, if the film 3 is polysilicon, the etching rate ratio with the thermal oxide film 2 is about 20, and if the film 3 is a nitride film, the etching rate ratio with the thermal oxide film 2 is about 3. It will be about 4. Further, if the film 3 is PSG, the etch rate ratio with respect to the thermal oxide film 2 will be about 1 to 2. Therefore, the film 3 is a nitride film or a PS film.
In the case of G, wet etching is preferable to dry etching because it provides a better etch rate ratio. If a nitride film is wet-etched using an aqueous solution containing phosphoric acid, an etch rate ratio of several hundred can be obtained with respect to the thermal oxide film 2, and if a PSG film is wet-etched using an aqueous solution containing hydrofluoric acid or a so-called buffered hydrofluoric acid. If wet etching is performed in an aqueous solution, an etch rate ratio of several hundred to the thermal oxide film 2 can be obtained, and only the film 3 can be selectively removed. Note that when the Si○2 film 3 is formed on the film 3, the film 2 is also 5i02.
Since the film is a film, the film 3 and the Si○2 film 2 are etched at the same time, and the Si substrate is exposed on the back side of the wafer as shown in FIG. 1 (C). In any case, the backside of the wafer is covered with thermal oxide film 2 or S.
Since the i-substrate 1 is in an exposed state, it is flattened. However, if the thermal oxide film 2 remains, it is possible to prevent the back surface of the wafer from being scratched. In this case, the thermal oxide film 2 may be a nitride film. That is, it is sufficient if the film 2 serves as an etching stopper when removing the film 3 by etching. In that case, as described above, the back surface of the wafer may be flattened by dry etching or wet etching so that only the film 3 can be selectively removed. Incidentally, during this etching removal, there is a possibility that dust may adhere to the resist film 4 on the wafer surface. However, in the next step shown in FIG. 1(d), the resist film 4 is removed and the organic photoresist film 5 is recoated instead, so that the dust attached to the resist 1-M4 is removed at this time.

第1図(d)参照。See Figure 1(d).

最後にウェハ表面のレジスト膜4を通常の方法で除去し
て、その代わりに有機感光膜5を再塗布する。これでウ
ェハ裏面を平坦化する際に生した、すなわちウェハ裏面
の膜3を除去する際に生したレジスト膜4上に付着した
ダストを取り除け、新しく有機感光膜を形成できる。尚
、第1図(C゛)の工程をとった場合は、第1図(d”
)のようになる。
Finally, the resist film 4 on the wafer surface is removed by a conventional method, and an organic photoresist film 5 is reapplied in its place. This removes the dust adhering to the resist film 4 that was generated when the back surface of the wafer was flattened, that is, when the film 3 on the back surface of the wafer was removed, and a new organic photoresist film can be formed. In addition, if the process shown in Figure 1 (C゛) is taken, the process shown in Figure 1 (d''
)become that way.

そして、このウェハを真空チャックに吸着させてパター
ンを焼きつける。これでウェハ裏面は平坦化された状態
で真空チャンクに取りつけられるので、ウェハ裏面の凸
凹が吸着の際ウェハ表面に転写されてウェハ表面の凸凹
が増幅されることもなくなる。従って、膜3としてポリ
シリコンを選んだ場合は第1図(a)で示した初期のL
TV  O・8μm程度で露光を行える。すなわち、有
機感光膜5を第3図(b)のように厚く形成せずに、厚
さむらなく蒲<形成できるのでLTVは被写体深度1.
5μm内におさまり、解像度を低下させずにすむ。従っ
て、微細パターンを鮮明に焼きつけられ、転写パターン
の寸法精度は従来より向上する。
The wafer is then attracted to a vacuum chuck and a pattern is printed on it. With this, the back surface of the wafer is attached to the vacuum chunk in a flattened state, so that the unevenness on the back surface of the wafer will not be transferred to the front surface of the wafer during suction and the unevenness on the wafer surface will not be amplified. Therefore, if polysilicon is selected as the film 3, the initial L shown in FIG.
Exposure can be performed at TV O.about 8 μm. That is, since the organic photoresist film 5 can be formed with an even thickness without forming it thickly as shown in FIG. 3(b), the LTV has a depth of field of 1.
It is within 5 μm, so there is no need to reduce the resolution. Therefore, a fine pattern can be clearly printed, and the dimensional accuracy of the transferred pattern is improved compared to the conventional method.

〔発明の効果〕〔Effect of the invention〕

以上、説明したように本発明によればフォトリソグラフ
ィ技術における露光の際、安定した解像度及び転写パタ
ーンの寸法精度が得られるので、半導体素子の微細パタ
ーンを容易に焼きつけられるようになる。従って、半導
体素子の微細化に寄与するところが大きい。
As described above, according to the present invention, stable resolution and dimensional accuracy of a transferred pattern can be obtained during exposure in photolithography technology, so that fine patterns of semiconductor elements can be easily printed. Therefore, it greatly contributes to the miniaturization of semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の詳細な説明するための要部断面図、第
2図は半導体ウェハの断面図、第3図はウェハ裏面を除
去せずに真空チャック上に固定した状態を説明するため
のウェハ断面図である。 図中、 1:半導体基板 2:熱酸化膜 3:膜 4ニレジスト膜 5:有機感光膜 6:真空チャック 10:ウェハ表面 11:ウェハ裏面 12:半導体ウェハ 13 : LTV :$−会J力の工程kま在明するr二めの要g昏護カ′
面節第1 図(:fの1) 本発明の工禾至を説、朗するための要ぶ壇弁面図第1 
図(その2)
Fig. 1 is a cross-sectional view of a main part for explaining the present invention in detail, Fig. 2 is a cross-sectional view of a semiconductor wafer, and Fig. 3 is a cross-sectional view of a wafer fixed on a vacuum chuck without removing the back side of the wafer. FIG. In the figure: 1: Semiconductor substrate 2: Thermal oxide film 3: Film 4 Resist film 5: Organic photoresist film 6: Vacuum chuck 10: Wafer front side 11: Wafer back side 12: Semiconductor wafer 13: LTV: $-Metal process I'm here, and I'm in the second place.
Table 1 Diagram 1 (: f 1) Key points for explaining and reciting the technical merits of the present invention 1
Diagram (Part 2)

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の第1の主面上に膜を形成し、該膜の上に感
光性レジスト膜を形成し、前記半導体基板の第1の主面
に対向する第2の主面を支持具の平坦面に密着させた状
態で露光を行う半導体装置の製造方法において、第2の
主面が平坦な半導体基板(1)の第2の主面と第1の主
面上に厚さが略一様な膜を少なくとも1層以上形成する
工程と、第1の主面上に形成した膜上に保護膜(4)を
形成する工程と、第2の主面上の膜を半導体基板と同程
度に平坦な面が出るまで選択的にエッチング除去する工
程と、しかる後、該保護膜(4)を除去した後、前記第
1の主面側に被着・形成した膜(3)上に感光性レジス
ト膜(5)を形成し、該半導体基板(1)の前記第2の
主面側を前記支持具(6)の平坦面に密着させるように
保持して露光を行う工程とを含むことを特徴とする半導
体装置の製造方法。
A film is formed on a first main surface of a semiconductor substrate, a photosensitive resist film is formed on the film, and a second main surface opposite to the first main surface of the semiconductor substrate is formed on a flat surface of a support. In a method of manufacturing a semiconductor device in which exposure is performed in close contact with a surface, the thickness is substantially uniform on the second main surface and the first main surface of a semiconductor substrate (1) whose second main surface is flat. forming a protective film (4) on the film formed on the first main surface; and forming the film on the second main surface to the same extent as the semiconductor substrate. A process of selectively etching and removing until a flat surface is obtained, and then, after removing the protective film (4), a photosensitive layer is applied to the film (3) deposited and formed on the first main surface side. forming a resist film (5) and performing exposure while holding the second main surface side of the semiconductor substrate (1) in close contact with the flat surface of the support (6); A method for manufacturing a featured semiconductor device.
JP6510190A 1990-03-15 1990-03-15 Manufacture of semiconductor device Pending JPH03265121A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6510190A JPH03265121A (en) 1990-03-15 1990-03-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6510190A JPH03265121A (en) 1990-03-15 1990-03-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03265121A true JPH03265121A (en) 1991-11-26

Family

ID=13277180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6510190A Pending JPH03265121A (en) 1990-03-15 1990-03-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03265121A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005039155A (en) * 2003-07-18 2005-02-10 Matsushita Electric Ind Co Ltd Method of manufacturing semiconductor device and method of manufacturing semiconductor substrate used for the device
JP2008177468A (en) * 2007-01-22 2008-07-31 Tokyo Electron Ltd Processing method of substrate, coater and substrate treatment system
JP2015180953A (en) * 2008-05-21 2015-10-15 ケーエルエー−テンカー・コーポレーションKla−Tencor Corporation Substrate matrix to decouple tool and process effects

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005039155A (en) * 2003-07-18 2005-02-10 Matsushita Electric Ind Co Ltd Method of manufacturing semiconductor device and method of manufacturing semiconductor substrate used for the device
JP2008177468A (en) * 2007-01-22 2008-07-31 Tokyo Electron Ltd Processing method of substrate, coater and substrate treatment system
JP2015180953A (en) * 2008-05-21 2015-10-15 ケーエルエー−テンカー・コーポレーションKla−Tencor Corporation Substrate matrix to decouple tool and process effects
JP2017201402A (en) * 2008-05-21 2017-11-09 ケーエルエー−テンカー・コーポレーションKla−Tencor Corporation Substrate matrix to decouple tool and process effects

Similar Documents

Publication Publication Date Title
US7125783B2 (en) Dielectric anti-reflective coating surface treatment to prevent defect generation in associated wet clean
US9281251B2 (en) Substrate backside texturing
JPH05211140A (en) Method for removal of material around substrate
US6090688A (en) Method for fabricating an SOI substrate
JPH069194B2 (en) Integrated circuits from wafers with improved flatness
JP4220229B2 (en) Mask blank for charged particle beam exposure and method for manufacturing mask for charged particle beam exposure
US20050142804A1 (en) Method for fabricating shallow trench isolation structure of semiconductor device
US7541293B2 (en) Method for manufacturing semiconductor device
JPH03265121A (en) Manufacture of semiconductor device
US20040067654A1 (en) Method of reducing wafer etching defect
KR100420559B1 (en) Semiconductor manufacturing method for reducing particle
JP2000286330A (en) Substrate holding chuck and its manufacture, method of exposure, manufacture of semiconductor device, and aligner
JP2009010071A (en) Method for polishing wafer
JPH08167587A (en) Flattening method of semiconductor wafer
TWI700778B (en) Edge handling method of semiconductor substrate
JPH06215993A (en) Composite semiconductor substrate and manufacture thereof
US5902706A (en) Mask for making a semiconductor device and fabrication method thereof
JPH08236506A (en) Manufacture of semiconductor device
JPH05109702A (en) Manufacture of semiconductor device
JPH03188648A (en) Manufacture of semiconductor device
JP2000286329A (en) Substrate-holding chuck, manufacture thereof, exposure method, manufacture of semiconductor device and aligner
JPH098126A (en) Method for manufacturing semiconductor substrate
JPH02237066A (en) Manufacture of semiconductor device
KR20050032837A (en) A manufacturing method for epitaxial wafer
KR100342392B1 (en) a method of forming a gate of a semiconductor device