JPH03262148A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03262148A JPH03262148A JP6154290A JP6154290A JPH03262148A JP H03262148 A JPH03262148 A JP H03262148A JP 6154290 A JP6154290 A JP 6154290A JP 6154290 A JP6154290 A JP 6154290A JP H03262148 A JPH03262148 A JP H03262148A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring layer
- polyimide
- layer
- polyimide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims 2
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000001312 dry etching Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 5
- 239000002952 polymeric resin Substances 0.000 claims description 12
- 229920003002 synthetic resin Polymers 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 abstract description 35
- 239000000428 dust Substances 0.000 abstract description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 5
- 238000000992 sputter etching Methods 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 4
- 230000001681 protective effect Effects 0.000 abstract description 4
- 229920005989 resin Polymers 0.000 abstract description 2
- 239000011347 resin Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 57
- 239000010410 layer Substances 0.000 description 32
- 230000002265 prevention Effects 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 5
- 239000012528 membrane Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 229910001220 stainless steel Inorganic materials 0.000 description 3
- 239000010935 stainless steel Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】 〔概要〕 本発明は、半導体装置の多層配線の層間構造に関し。[Detailed description of the invention] 〔overview〕 The present invention relates to an interlayer structure of multilayer wiring of a semiconductor device.
多層配線層中のポリイミド膜を変質させることなく、配
線層を実現させることを目的とし半導体基板上の下層ア
ルミニウム配線層の表面に高分子樹脂膜を被覆する工程
と、該高分子樹脂膜(3)の表面に金属膜を被覆する工
程と、該金属膜及び該高分子樹脂膜を通して、電極配線
接続用のスルーホールを開口する工程と、該スルーホー
ル内をドライエツチングして、該アルミニウム配線層の
表面酸化膜を除去する工程と、該基板上にアルミニウム
膜を被覆し、パタニングして上層配線層(6)を形成す
る工程とを含むように構成する。A process of coating a polymer resin film on the surface of a lower aluminum wiring layer on a semiconductor substrate with the aim of realizing a wiring layer without altering the polyimide film in the multilayer wiring layer; ), a step of opening a through hole for electrode wiring connection through the metal film and the polymer resin film, and dry etching the inside of the through hole to remove the aluminum wiring layer. The structure includes a step of removing a surface oxide film of the substrate, and a step of covering the substrate with an aluminum film and patterning it to form an upper wiring layer (6).
本発明は、半導体装置の多層配線の層間構造に関する。 The present invention relates to an interlayer structure of multilayer wiring of a semiconductor device.
近年、LSIの多層配線の層間絶縁膜には、従来の燐珪
酸ガラス(PSG)膜などに代わって、ポリイミド膜等
の高分子樹脂膜やスピン・オン・グラス(SOG)膜等
のガラス膜が、コストや平坦化が容易なこと、工程が簡
略化できる事などのために多く使用されるように成って
きた。In recent years, polymer resin films such as polyimide films and glass films such as spin-on-glass (SOG) films have been used as interlayer insulating films for multilayer wiring in LSIs, instead of conventional phosphosilicate glass (PSG) films. , it has come to be widely used due to its cost, ease of flattening, and simplification of the process.
第4図は従来例の説明図である。 FIG. 4 is an explanatory diagram of a conventional example.
図において、19はフィールド酸化膜、20はAN膜、
21はポリイミド膜、22は^l自然酸化膜、23は反
応チャンバ、24はスパッタ電極、25はウェハ、26
は防着板、27はポリイミド膜である。In the figure, 19 is a field oxide film, 20 is an AN film,
21 is a polyimide film, 22 is a natural oxide film, 23 is a reaction chamber, 24 is a sputtering electrode, 25 is a wafer, 26
2 is an adhesion prevention plate, and 27 is a polyimide film.
ド酸化膜19上に形成された電極配線のAj2膜2膜上
0上リイミド膜21を塗布し、エツチングにより下層の
AN膜上に上層配線接続のためのスルーホールを開口す
る。A liimide film 21 is coated on the Aj2 film 2 film of the electrode wiring formed on the doped oxide film 19, and a through hole for connecting the upper layer wiring is opened on the lower layer AN film by etching.
次に、多層配線の上層のAffi膜をスパッタ法により
被覆するが、その前処理として、スパッタエッチングや
イオンミリング等のドライエツチングによりアルゴン(
Ar)イオンで開口されたへ!膜20の上に自然にでき
た薄いアルミニウム酸化膜22の示すように、エツチン
グされたポリイミド膜21が反応チャンバ23内の防着
板26の表面に付着するがステンレス製であるために密
着が悪く、ポリイミド膜21が剥がれて、ウェハー25
の表面に付着し不良の原因となるので、防着板26の表
面にへ!膜を被覆して、密着性を改善している。Next, the Affi film on the upper layer of the multilayer wiring is coated by sputtering, but as a pretreatment, dry etching such as sputter etching or ion milling is performed to cover the Affi film with argon (
Ar) Opened by ions! As shown by the thin aluminum oxide film 22 naturally formed on the film 20, the etched polyimide film 21 adheres to the surface of the adhesion prevention plate 26 in the reaction chamber 23, but since it is made of stainless steel, the adhesion is poor. , the polyimide film 21 is peeled off and the wafer 25
If it adheres to the surface of the adhesion prevention plate 26, it may cause defects. The film is coated to improve adhesion.
前記のように、 Arイオンにより、スルーホール内の
へ!膜表面のみならず5層間絶縁膜であるポリイミド膜
の表面をも叩くことになる。As mentioned above, the Ar ions cause the inside of the through-hole! This hits not only the film surface but also the surface of the polyimide film, which is the five-layer insulating film.
このため、ポリイミド膜の樹脂構造を変化させて、ポリ
イミド膜自体の耐湿性、絶縁性を劣化させることとなる
。Therefore, the resin structure of the polyimide film is changed, and the moisture resistance and insulation properties of the polyimide film itself are deteriorated.
また、 Arイオンに叩かれたポリイミド膜は装置内の
防着板の表面に付着して、ポリイミド膜が積層していく
と、ポリイミド膜とポリイミド′膜の間から剥離して飛
散し、ごみ発生の原因となる。In addition, the polyimide film hit by the Ar ions adheres to the surface of the anti-adhesion plate inside the device, and as the polyimide films are stacked, they peel off from between the polyimide films and scatter, creating dust. It causes
本発明は1以上の点に鑑み、ポリイミド膜を変質させる
事なく、多層配線を実現させるとともに装置内のごみ発
生を防止することを目的として提供されるものである。In view of one or more points, the present invention is provided for the purpose of realizing multilayer wiring without deteriorating the polyimide film and preventing the generation of dust within the device.
4を被覆する工程と、該金属膜4及び該高分子樹脂膜3
を通して、電極配線接続用のスルーホール5を開口する
工程と、該スルーホール5内をドライエツチングして、
該アルミニウム配線層2の表面酸化膜を除去する工程と
、該基板上にアルミニウム膜を被覆し、パタニングして
上層配線層6を形成する工程とを含むことにより達成さ
れる。4, and the step of coating the metal film 4 and the polymer resin film 3.
a step of opening a through hole 5 for electrode wiring connection through the through hole, and dry etching the inside of the through hole 5,
This is accomplished by including the steps of removing the surface oxide film of the aluminum wiring layer 2, and covering the substrate with an aluminum film and patterning it to form the upper wiring layer 6.
第1図は本発明の原理説明図である。 FIG. 1 is a diagram explaining the principle of the present invention.
図において、1はフィールド酸化膜、2は下層AI!、
配線層、3は高分子樹脂膜、4は金属膜、5はスルーポ
ール、6は上層へβ配線層である。In the figure, 1 is the field oxide film, 2 is the lower layer AI! ,
The wiring layers include a polymer resin film 3, a metal film 4, a through pole 5, and a β wiring layer 6 to the upper layer.
解決手段として、上層配線層のへ!膜をスパッタにより
被覆する前に、ポリイミド等の高分子樹脂膜の表面に薄
いΔN膜等の金属保護膜を被覆する。As a solution, go to the upper wiring layer! Before coating the film by sputtering, the surface of the polymer resin film such as polyimide is coated with a thin metal protective film such as a ΔN film.
即ち1本発明の目的は、半導体基板上の下層アルミニウ
ム配線層2の表面に高分子樹脂膜3を被覆する工程と、
該高分子樹脂膜3の表面に金属膜〔作用〕
本発明では、スルーホール内のへ!膜及びポリイミド保
護用の金属保護膜のみが前処理のArイオンで叩かれる
ために、ポリイミド膜の変質が防止されるとともに、防
着板についたポリイミド膜の剥離が防がれ、ごみの発生
を抑えることができる。That is, one object of the present invention is to cover the surface of a lower aluminum wiring layer 2 on a semiconductor substrate with a polymer resin film 3;
Metal film on the surface of the polymer resin film 3 [Function] In the present invention, the inside of the through-hole! Since only the metal protective film for protecting the film and polyimide is bombarded with pre-treated Ar ions, deterioration of the polyimide film is prevented, and peeling of the polyimide film attached to the anti-adhesion plate is also prevented, reducing the generation of dust. It can be suppressed.
第2図は本発明の一実施例の工程順模式断面図第3図は
本発明の一実施例の防着板である。FIG. 2 is a schematic sectional view of an embodiment of the present invention in the order of steps. FIG. 3 is an anti-adhesion plate of an embodiment of the present invention.
図において、7は5i02膜、8は下層7/2配線層。In the figure, 7 is a 5i02 film, and 8 is a lower 7/2 wiring layer.
9は第1のポリイミド膜、lOはAI!、膜、11はス
ルホール、12は上層^ρ配線層、13は第2のポリイ
ミド膜、14はへl被覆のステンレス製防着板。9 is the first polyimide film, lO is AI! , membrane, 11 is a through hole, 12 is an upper layer ^ρ wiring layer, 13 is a second polyimide film, and 14 is a stainless steel adhesion prevention plate coated with aluminum.
15はポリイミド膜、16はへ!膜、 17はポリイミ
ド膜、18はl!膜である。15 is polyimide film, 16 is to! membrane, 17 is a polyimide membrane, 18 is l! It is a membrane.
第2図により一実施例を説明する。One embodiment will be explained with reference to FIG.
第2図(a)に示すように、半導体栽板のフィールドS
iO□膜7上に下層へ!配線層8を1μmの厚さに形成
する。As shown in Fig. 2(a), the field S of the semiconductor planting board
To the lower layer on the iO□ film 7! Wiring layer 8 is formed to have a thickness of 1 μm.
第2図(b)に示すように、第1のポリイミド膜を3μ
mの厚さに被覆する。As shown in Figure 2(b), the first polyimide film was
Coat to a thickness of m.
第2図(C)に示すように、第1のポリイミド膜9上に
、500人の厚さにAn膜10を被覆する。As shown in FIG. 2C, the first polyimide film 9 is coated with an An film 10 to a thickness of 500 mm.
第2図(d)に示すように、 へl膜10及びボタイミ
ド膜9をエツチングして、スルーホール11を開口する
。As shown in FIG. 2(d), the helium film 10 and the botaimide film 9 are etched to open a through hole 11.
スパッタエツチングにより、下層へl配線上に自然に薄
くできた八!の酸化膜を、RFエツチングにより、 4
00〜500Vで60〜90秒間、 Arイオンのドラ
イエツチングで除去する。この時、ポリイミド膜9の表
面はAffi膜で覆われているので、 /1ffi膜
が多少削られても、損傷することはない。By sputter etching, a thin layer was created naturally on the lower layer wiring. The oxide film of 4 is etched by RF etching.
Remove by dry etching with Ar ions at 00 to 500 V for 60 to 90 seconds. At this time, since the surface of the polyimide film 9 is covered with the Affi film, even if the /1ffi film is scraped to some extent, it will not be damaged.
尚、コのスパックエツチングは反応性スパッタエツチン
グに代えても良い。Incidentally, the spuck etching described above may be replaced with reactive sputter etching.
第2図(e)に示すように、へ!膜を1μmの厚さにス
パッタ蒸着し、パタニングして上層Ap。As shown in Figure 2(e), to! A film was sputter-deposited to a thickness of 1 μm and patterned to form the upper layer Ap.
配線層12を形成する。A wiring layer 12 is formed.
第2図(f)に示すように、全面に第2のポリイミド膜
13を2μmの厚さに被覆する。As shown in FIG. 2(f), the entire surface is coated with a second polyimide film 13 to a thickness of 2 μm.
この時、第3図に示すように、装置内の装置内のへ!被
覆のステンレス製の防着板14の上もポリイミド膜とへ
l膜が交互に重ね合わさって付くので、これらの膜が剥
離することはなく、半導体基板上にごみとして付着する
ことがなくなる。At this time, as shown in FIG. Since polyimide films and Hel films are alternately superimposed on the coating stainless steel adhesion prevention plate 14, these films will not peel off and will not adhere as dust on the semiconductor substrate.
以上説明したように9本発明によれば1層間絶縁膜とし
て用いているポリイミド膜の変質を防止し、防着板から
のごみの発生もなく、多層配線技術の信頬性の向上に寄
与するところが大きい。As explained above, according to the present invention, deterioration of the polyimide film used as an interlayer insulating film is prevented, no dust is generated from the adhesion prevention plate, and the reliability of multilayer wiring technology is improved. However, it is large.
第1図は本発明の原理説明図。
第2図は本発明の一実施例の工程順模式断面図第3図は
本発明の一実施例の防着板
第4図は従来例の説明図
である。
図において。
1はフィールド酸化膜。
2は下層AI配線層、3は高分子樹脂膜。
4は金属膜、 5はスルーポール6は上層へl
配線層、7は5iOz膜
8は下層へ!配線層、9は第1のポリイミド膜。
10はへ!膜、11はスルーホール
12は上層Aff配線層、13は第2のポリイミド膜1
4はSUS製防製板着板5はポリイミド膜16はへl膜
、17はポリイミド膜
18は八!膜
−〇
■FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a schematic cross-sectional view of the steps of an embodiment of the present invention; FIG. 3 is an adhesion prevention plate of an embodiment of the present invention; FIG. 4 is an explanatory diagram of a conventional example. In fig. 1 is a field oxide film. 2 is a lower AI wiring layer, and 3 is a polymer resin film. 4 is a metal film, 5 is a through pole 6 is to the upper layer
Wiring layer 7 is 5iOz film 8 is on the lower layer! A wiring layer 9 is a first polyimide film. 10 ha! 11 is a through hole 12 is an upper Aff wiring layer, 13 is a second polyimide film 1
4 is a SUS-made protective board plate 5 is a polyimide film 16 is a thin film, 17 is a polyimide film 18 is a 8! Membrane -〇■
Claims (1)
に高分子樹脂膜(3)を被覆する工程と、該高分子樹脂
膜(3)の表面に金属膜(4)を被覆する工程と、 該金属膜(4)及び該高分子樹脂膜(3)を通して、電
極配線接続用のスルーホール(5)を開口する工程と、
該スルーホール(5)内をドライエッチングして、該ア
ルミニウム配線層(2)の表面酸化膜を除去する工程と
、 該基板上にアルミニウム膜を被覆し、パタニングして上
層配線層(6)を形成する工程とを含むことを特徴とす
る半導体装置の製造方法。[Claims] A step of coating a surface of a lower aluminum wiring layer (2) on a semiconductor substrate with a polymer resin film (3), and a step of coating a metal film (4) on the surface of the polymer resin film (3). a step of coating, a step of opening a through hole (5) for electrode wiring connection through the metal film (4) and the polymer resin film (3);
Dry etching the inside of the through hole (5) to remove the surface oxide film of the aluminum wiring layer (2); coating the substrate with an aluminum film and patterning it to form an upper wiring layer (6); 1. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6154290A JPH03262148A (en) | 1990-03-13 | 1990-03-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6154290A JPH03262148A (en) | 1990-03-13 | 1990-03-13 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03262148A true JPH03262148A (en) | 1991-11-21 |
Family
ID=13174108
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6154290A Pending JPH03262148A (en) | 1990-03-13 | 1990-03-13 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03262148A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05326385A (en) * | 1992-05-25 | 1993-12-10 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61214538A (en) * | 1985-03-20 | 1986-09-24 | Hitachi Ltd | Wiring structure and its manufacture |
JPS62245650A (en) * | 1986-04-18 | 1987-10-26 | Hitachi Ltd | Manufacture of multilayer interconnection structure |
-
1990
- 1990-03-13 JP JP6154290A patent/JPH03262148A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61214538A (en) * | 1985-03-20 | 1986-09-24 | Hitachi Ltd | Wiring structure and its manufacture |
JPS62245650A (en) * | 1986-04-18 | 1987-10-26 | Hitachi Ltd | Manufacture of multilayer interconnection structure |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05326385A (en) * | 1992-05-25 | 1993-12-10 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
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